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-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg.h_shipped567
1 files changed, 133 insertions, 434 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
index c21ceab8e913..cdcead071ef6 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
@@ -34,13 +34,6 @@ ahd_reg_print_t ahd_seqintcode_print;
34#endif 34#endif
35 35
36#if AIC_DEBUG_REGISTERS 36#if AIC_DEBUG_REGISTERS
37ahd_reg_print_t ahd_clrint_print;
38#else
39#define ahd_clrint_print(regvalue, cur_col, wrap) \
40 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
41#endif
42
43#if AIC_DEBUG_REGISTERS
44ahd_reg_print_t ahd_error_print; 37ahd_reg_print_t ahd_error_print;
45#else 38#else
46#define ahd_error_print(regvalue, cur_col, wrap) \ 39#define ahd_error_print(regvalue, cur_col, wrap) \
@@ -48,20 +41,6 @@ ahd_reg_print_t ahd_error_print;
48#endif 41#endif
49 42
50#if AIC_DEBUG_REGISTERS 43#if AIC_DEBUG_REGISTERS
51ahd_reg_print_t ahd_hcntrl_print;
52#else
53#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
54 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap)
55#endif
56
57#if AIC_DEBUG_REGISTERS
58ahd_reg_print_t ahd_hnscb_qoff_print;
59#else
60#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \
61 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap)
62#endif
63
64#if AIC_DEBUG_REGISTERS
65ahd_reg_print_t ahd_hescb_qoff_print; 44ahd_reg_print_t ahd_hescb_qoff_print;
66#else 45#else
67#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 46#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \
@@ -97,13 +76,6 @@ ahd_reg_print_t ahd_swtimer_print;
97#endif 76#endif
98 77
99#if AIC_DEBUG_REGISTERS 78#if AIC_DEBUG_REGISTERS
100ahd_reg_print_t ahd_snscb_qoff_print;
101#else
102#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \
103 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap)
104#endif
105
106#if AIC_DEBUG_REGISTERS
107ahd_reg_print_t ahd_sescb_qoff_print; 79ahd_reg_print_t ahd_sescb_qoff_print;
108#else 80#else
109#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 81#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \
@@ -111,20 +83,6 @@ ahd_reg_print_t ahd_sescb_qoff_print;
111#endif 83#endif
112 84
113#if AIC_DEBUG_REGISTERS 85#if AIC_DEBUG_REGISTERS
114ahd_reg_print_t ahd_sdscb_qoff_print;
115#else
116#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \
117 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap)
118#endif
119
120#if AIC_DEBUG_REGISTERS
121ahd_reg_print_t ahd_qoff_ctlsta_print;
122#else
123#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \
124 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap)
125#endif
126
127#if AIC_DEBUG_REGISTERS
128ahd_reg_print_t ahd_intctl_print; 86ahd_reg_print_t ahd_intctl_print;
129#else 87#else
130#define ahd_intctl_print(regvalue, cur_col, wrap) \ 88#define ahd_intctl_print(regvalue, cur_col, wrap) \
@@ -139,13 +97,6 @@ ahd_reg_print_t ahd_dfcntrl_print;
139#endif 97#endif
140 98
141#if AIC_DEBUG_REGISTERS 99#if AIC_DEBUG_REGISTERS
142ahd_reg_print_t ahd_dscommand0_print;
143#else
144#define ahd_dscommand0_print(regvalue, cur_col, wrap) \
145 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap)
146#endif
147
148#if AIC_DEBUG_REGISTERS
149ahd_reg_print_t ahd_dfstatus_print; 100ahd_reg_print_t ahd_dfstatus_print;
150#else 101#else
151#define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 102#define ahd_dfstatus_print(regvalue, cur_col, wrap) \
@@ -160,13 +111,6 @@ ahd_reg_print_t ahd_sg_cache_shadow_print;
160#endif 111#endif
161 112
162#if AIC_DEBUG_REGISTERS 113#if AIC_DEBUG_REGISTERS
163ahd_reg_print_t ahd_sg_cache_pre_print;
164#else
165#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
166 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap)
167#endif
168
169#if AIC_DEBUG_REGISTERS
170ahd_reg_print_t ahd_lqin_print; 114ahd_reg_print_t ahd_lqin_print;
171#else 115#else
172#define ahd_lqin_print(regvalue, cur_col, wrap) \ 116#define ahd_lqin_print(regvalue, cur_col, wrap) \
@@ -293,13 +237,6 @@ ahd_reg_print_t ahd_sxfrctl0_print;
293#endif 237#endif
294 238
295#if AIC_DEBUG_REGISTERS 239#if AIC_DEBUG_REGISTERS
296ahd_reg_print_t ahd_sxfrctl1_print;
297#else
298#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
299 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahd_reg_print_t ahd_dffstat_print; 240ahd_reg_print_t ahd_dffstat_print;
304#else 241#else
305#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 242#define ahd_dffstat_print(regvalue, cur_col, wrap) \
@@ -314,13 +251,6 @@ ahd_reg_print_t ahd_multargid_print;
314#endif 251#endif
315 252
316#if AIC_DEBUG_REGISTERS 253#if AIC_DEBUG_REGISTERS
317ahd_reg_print_t ahd_scsisigo_print;
318#else
319#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
320 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
321#endif
322
323#if AIC_DEBUG_REGISTERS
324ahd_reg_print_t ahd_scsisigi_print; 254ahd_reg_print_t ahd_scsisigi_print;
325#else 255#else
326#define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 256#define ahd_scsisigi_print(regvalue, cur_col, wrap) \
@@ -363,13 +293,6 @@ ahd_reg_print_t ahd_selid_print;
363#endif 293#endif
364 294
365#if AIC_DEBUG_REGISTERS 295#if AIC_DEBUG_REGISTERS
366ahd_reg_print_t ahd_optionmode_print;
367#else
368#define ahd_optionmode_print(regvalue, cur_col, wrap) \
369 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
370#endif
371
372#if AIC_DEBUG_REGISTERS
373ahd_reg_print_t ahd_sblkctl_print; 296ahd_reg_print_t ahd_sblkctl_print;
374#else 297#else
375#define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 298#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
@@ -391,13 +314,6 @@ ahd_reg_print_t ahd_simode0_print;
391#endif 314#endif
392 315
393#if AIC_DEBUG_REGISTERS 316#if AIC_DEBUG_REGISTERS
394ahd_reg_print_t ahd_clrsint0_print;
395#else
396#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
397 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
398#endif
399
400#if AIC_DEBUG_REGISTERS
401ahd_reg_print_t ahd_sstat1_print; 317ahd_reg_print_t ahd_sstat1_print;
402#else 318#else
403#define ahd_sstat1_print(regvalue, cur_col, wrap) \ 319#define ahd_sstat1_print(regvalue, cur_col, wrap) \
@@ -405,13 +321,6 @@ ahd_reg_print_t ahd_sstat1_print;
405#endif 321#endif
406 322
407#if AIC_DEBUG_REGISTERS 323#if AIC_DEBUG_REGISTERS
408ahd_reg_print_t ahd_clrsint1_print;
409#else
410#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
411 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
412#endif
413
414#if AIC_DEBUG_REGISTERS
415ahd_reg_print_t ahd_sstat2_print; 324ahd_reg_print_t ahd_sstat2_print;
416#else 325#else
417#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 326#define ahd_sstat2_print(regvalue, cur_col, wrap) \
@@ -461,17 +370,17 @@ ahd_reg_print_t ahd_lqistat0_print;
461#endif 370#endif
462 371
463#if AIC_DEBUG_REGISTERS 372#if AIC_DEBUG_REGISTERS
464ahd_reg_print_t ahd_lqimode0_print; 373ahd_reg_print_t ahd_clrlqiint0_print;
465#else 374#else
466#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 375#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
467 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 376 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
468#endif 377#endif
469 378
470#if AIC_DEBUG_REGISTERS 379#if AIC_DEBUG_REGISTERS
471ahd_reg_print_t ahd_clrlqiint0_print; 380ahd_reg_print_t ahd_lqimode0_print;
472#else 381#else
473#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 382#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
474 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 383 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
475#endif 384#endif
476 385
477#if AIC_DEBUG_REGISTERS 386#if AIC_DEBUG_REGISTERS
@@ -629,17 +538,17 @@ ahd_reg_print_t ahd_seqintsrc_print;
629#endif 538#endif
630 539
631#if AIC_DEBUG_REGISTERS 540#if AIC_DEBUG_REGISTERS
632ahd_reg_print_t ahd_seqimode_print; 541ahd_reg_print_t ahd_currscb_print;
633#else 542#else
634#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 543#define ahd_currscb_print(regvalue, cur_col, wrap) \
635 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 544 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
636#endif 545#endif
637 546
638#if AIC_DEBUG_REGISTERS 547#if AIC_DEBUG_REGISTERS
639ahd_reg_print_t ahd_currscb_print; 548ahd_reg_print_t ahd_seqimode_print;
640#else 549#else
641#define ahd_currscb_print(regvalue, cur_col, wrap) \ 550#define ahd_seqimode_print(regvalue, cur_col, wrap) \
642 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 551 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
643#endif 552#endif
644 553
645#if AIC_DEBUG_REGISTERS 554#if AIC_DEBUG_REGISTERS
@@ -657,13 +566,6 @@ ahd_reg_print_t ahd_lastscb_print;
657#endif 566#endif
658 567
659#if AIC_DEBUG_REGISTERS 568#if AIC_DEBUG_REGISTERS
660ahd_reg_print_t ahd_shaddr_print;
661#else
662#define ahd_shaddr_print(regvalue, cur_col, wrap) \
663 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
664#endif
665
666#if AIC_DEBUG_REGISTERS
667ahd_reg_print_t ahd_negoaddr_print; 569ahd_reg_print_t ahd_negoaddr_print;
668#else 570#else
669#define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 571#define ahd_negoaddr_print(regvalue, cur_col, wrap) \
@@ -748,27 +650,6 @@ ahd_reg_print_t ahd_seloid_print;
748#endif 650#endif
749 651
750#if AIC_DEBUG_REGISTERS 652#if AIC_DEBUG_REGISTERS
751ahd_reg_print_t ahd_haddr_print;
752#else
753#define ahd_haddr_print(regvalue, cur_col, wrap) \
754 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap)
755#endif
756
757#if AIC_DEBUG_REGISTERS
758ahd_reg_print_t ahd_hcnt_print;
759#else
760#define ahd_hcnt_print(regvalue, cur_col, wrap) \
761 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap)
762#endif
763
764#if AIC_DEBUG_REGISTERS
765ahd_reg_print_t ahd_sghaddr_print;
766#else
767#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
768 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
769#endif
770
771#if AIC_DEBUG_REGISTERS
772ahd_reg_print_t ahd_scbhaddr_print; 653ahd_reg_print_t ahd_scbhaddr_print;
773#else 654#else
774#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 655#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
@@ -776,10 +657,10 @@ ahd_reg_print_t ahd_scbhaddr_print;
776#endif 657#endif
777 658
778#if AIC_DEBUG_REGISTERS 659#if AIC_DEBUG_REGISTERS
779ahd_reg_print_t ahd_sghcnt_print; 660ahd_reg_print_t ahd_sghaddr_print;
780#else 661#else
781#define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 662#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
782 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 663 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
783#endif 664#endif
784 665
785#if AIC_DEBUG_REGISTERS 666#if AIC_DEBUG_REGISTERS
@@ -790,10 +671,10 @@ ahd_reg_print_t ahd_scbhcnt_print;
790#endif 671#endif
791 672
792#if AIC_DEBUG_REGISTERS 673#if AIC_DEBUG_REGISTERS
793ahd_reg_print_t ahd_dff_thrsh_print; 674ahd_reg_print_t ahd_sghcnt_print;
794#else 675#else
795#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 676#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
796 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 677 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
797#endif 678#endif
798 679
799#if AIC_DEBUG_REGISTERS 680#if AIC_DEBUG_REGISTERS
@@ -867,13 +748,6 @@ ahd_reg_print_t ahd_targpcistat_print;
867#endif 748#endif
868 749
869#if AIC_DEBUG_REGISTERS 750#if AIC_DEBUG_REGISTERS
870ahd_reg_print_t ahd_scbptr_print;
871#else
872#define ahd_scbptr_print(regvalue, cur_col, wrap) \
873 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
874#endif
875
876#if AIC_DEBUG_REGISTERS
877ahd_reg_print_t ahd_scbautoptr_print; 751ahd_reg_print_t ahd_scbautoptr_print;
878#else 752#else
879#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 753#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
@@ -881,13 +755,6 @@ ahd_reg_print_t ahd_scbautoptr_print;
881#endif 755#endif
882 756
883#if AIC_DEBUG_REGISTERS 757#if AIC_DEBUG_REGISTERS
884ahd_reg_print_t ahd_ccsgaddr_print;
885#else
886#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \
887 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap)
888#endif
889
890#if AIC_DEBUG_REGISTERS
891ahd_reg_print_t ahd_ccscbaddr_print; 758ahd_reg_print_t ahd_ccscbaddr_print;
892#else 759#else
893#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 760#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
@@ -909,13 +776,6 @@ ahd_reg_print_t ahd_ccsgctl_print;
909#endif 776#endif
910 777
911#if AIC_DEBUG_REGISTERS 778#if AIC_DEBUG_REGISTERS
912ahd_reg_print_t ahd_ccsgram_print;
913#else
914#define ahd_ccsgram_print(regvalue, cur_col, wrap) \
915 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap)
916#endif
917
918#if AIC_DEBUG_REGISTERS
919ahd_reg_print_t ahd_ccscbram_print; 779ahd_reg_print_t ahd_ccscbram_print;
920#else 780#else
921#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 781#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
@@ -930,13 +790,6 @@ ahd_reg_print_t ahd_brddat_print;
930#endif 790#endif
931 791
932#if AIC_DEBUG_REGISTERS 792#if AIC_DEBUG_REGISTERS
933ahd_reg_print_t ahd_brdctl_print;
934#else
935#define ahd_brdctl_print(regvalue, cur_col, wrap) \
936 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahd_reg_print_t ahd_seeadr_print; 793ahd_reg_print_t ahd_seeadr_print;
941#else 794#else
942#define ahd_seeadr_print(regvalue, cur_col, wrap) \ 795#define ahd_seeadr_print(regvalue, cur_col, wrap) \
@@ -972,13 +825,6 @@ ahd_reg_print_t ahd_dspdatactl_print;
972#endif 825#endif
973 826
974#if AIC_DEBUG_REGISTERS 827#if AIC_DEBUG_REGISTERS
975ahd_reg_print_t ahd_dfdat_print;
976#else
977#define ahd_dfdat_print(regvalue, cur_col, wrap) \
978 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap)
979#endif
980
981#if AIC_DEBUG_REGISTERS
982ahd_reg_print_t ahd_dspselect_print; 828ahd_reg_print_t ahd_dspselect_print;
983#else 829#else
984#define ahd_dspselect_print(regvalue, cur_col, wrap) \ 830#define ahd_dspselect_print(regvalue, cur_col, wrap) \
@@ -1000,13 +846,6 @@ ahd_reg_print_t ahd_seqctl0_print;
1000#endif 846#endif
1001 847
1002#if AIC_DEBUG_REGISTERS 848#if AIC_DEBUG_REGISTERS
1003ahd_reg_print_t ahd_flags_print;
1004#else
1005#define ahd_flags_print(regvalue, cur_col, wrap) \
1006 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahd_reg_print_t ahd_seqintctl_print; 849ahd_reg_print_t ahd_seqintctl_print;
1011#else 850#else
1012#define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 851#define ahd_seqintctl_print(regvalue, cur_col, wrap) \
@@ -1014,13 +853,6 @@ ahd_reg_print_t ahd_seqintctl_print;
1014#endif 853#endif
1015 854
1016#if AIC_DEBUG_REGISTERS 855#if AIC_DEBUG_REGISTERS
1017ahd_reg_print_t ahd_seqram_print;
1018#else
1019#define ahd_seqram_print(regvalue, cur_col, wrap) \
1020 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap)
1021#endif
1022
1023#if AIC_DEBUG_REGISTERS
1024ahd_reg_print_t ahd_prgmcnt_print; 856ahd_reg_print_t ahd_prgmcnt_print;
1025#else 857#else
1026#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 858#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \
@@ -1028,41 +860,6 @@ ahd_reg_print_t ahd_prgmcnt_print;
1028#endif 860#endif
1029 861
1030#if AIC_DEBUG_REGISTERS 862#if AIC_DEBUG_REGISTERS
1031ahd_reg_print_t ahd_accum_print;
1032#else
1033#define ahd_accum_print(regvalue, cur_col, wrap) \
1034 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahd_reg_print_t ahd_sindex_print;
1039#else
1040#define ahd_sindex_print(regvalue, cur_col, wrap) \
1041 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahd_reg_print_t ahd_dindex_print;
1046#else
1047#define ahd_dindex_print(regvalue, cur_col, wrap) \
1048 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap)
1049#endif
1050
1051#if AIC_DEBUG_REGISTERS
1052ahd_reg_print_t ahd_allones_print;
1053#else
1054#define ahd_allones_print(regvalue, cur_col, wrap) \
1055 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap)
1056#endif
1057
1058#if AIC_DEBUG_REGISTERS
1059ahd_reg_print_t ahd_allzeros_print;
1060#else
1061#define ahd_allzeros_print(regvalue, cur_col, wrap) \
1062 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap)
1063#endif
1064
1065#if AIC_DEBUG_REGISTERS
1066ahd_reg_print_t ahd_none_print; 863ahd_reg_print_t ahd_none_print;
1067#else 864#else
1068#define ahd_none_print(regvalue, cur_col, wrap) \ 865#define ahd_none_print(regvalue, cur_col, wrap) \
@@ -1070,27 +867,6 @@ ahd_reg_print_t ahd_none_print;
1070#endif 867#endif
1071 868
1072#if AIC_DEBUG_REGISTERS 869#if AIC_DEBUG_REGISTERS
1073ahd_reg_print_t ahd_sindir_print;
1074#else
1075#define ahd_sindir_print(regvalue, cur_col, wrap) \
1076 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap)
1077#endif
1078
1079#if AIC_DEBUG_REGISTERS
1080ahd_reg_print_t ahd_dindir_print;
1081#else
1082#define ahd_dindir_print(regvalue, cur_col, wrap) \
1083 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap)
1084#endif
1085
1086#if AIC_DEBUG_REGISTERS
1087ahd_reg_print_t ahd_stack_print;
1088#else
1089#define ahd_stack_print(regvalue, cur_col, wrap) \
1090 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap)
1091#endif
1092
1093#if AIC_DEBUG_REGISTERS
1094ahd_reg_print_t ahd_intvec1_addr_print; 870ahd_reg_print_t ahd_intvec1_addr_print;
1095#else 871#else
1096#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 872#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \
@@ -1126,17 +902,17 @@ ahd_reg_print_t ahd_accum_save_print;
1126#endif 902#endif
1127 903
1128#if AIC_DEBUG_REGISTERS 904#if AIC_DEBUG_REGISTERS
1129ahd_reg_print_t ahd_sram_base_print; 905ahd_reg_print_t ahd_waiting_scb_tails_print;
1130#else 906#else
1131#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 907#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1132 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 908 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1133#endif 909#endif
1134 910
1135#if AIC_DEBUG_REGISTERS 911#if AIC_DEBUG_REGISTERS
1136ahd_reg_print_t ahd_waiting_scb_tails_print; 912ahd_reg_print_t ahd_sram_base_print;
1137#else 913#else
1138#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 914#define ahd_sram_base_print(regvalue, cur_col, wrap) \
1139 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 915 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1140#endif 916#endif
1141 917
1142#if AIC_DEBUG_REGISTERS 918#if AIC_DEBUG_REGISTERS
@@ -1224,13 +1000,6 @@ ahd_reg_print_t ahd_msg_out_print;
1224#endif 1000#endif
1225 1001
1226#if AIC_DEBUG_REGISTERS 1002#if AIC_DEBUG_REGISTERS
1227ahd_reg_print_t ahd_dmaparams_print;
1228#else
1229#define ahd_dmaparams_print(regvalue, cur_col, wrap) \
1230 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap)
1231#endif
1232
1233#if AIC_DEBUG_REGISTERS
1234ahd_reg_print_t ahd_seq_flags_print; 1003ahd_reg_print_t ahd_seq_flags_print;
1235#else 1004#else
1236#define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 1005#define ahd_seq_flags_print(regvalue, cur_col, wrap) \
@@ -1238,20 +1007,6 @@ ahd_reg_print_t ahd_seq_flags_print;
1238#endif 1007#endif
1239 1008
1240#if AIC_DEBUG_REGISTERS 1009#if AIC_DEBUG_REGISTERS
1241ahd_reg_print_t ahd_saved_scsiid_print;
1242#else
1243#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \
1244 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap)
1245#endif
1246
1247#if AIC_DEBUG_REGISTERS
1248ahd_reg_print_t ahd_saved_lun_print;
1249#else
1250#define ahd_saved_lun_print(regvalue, cur_col, wrap) \
1251 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap)
1252#endif
1253
1254#if AIC_DEBUG_REGISTERS
1255ahd_reg_print_t ahd_lastphase_print; 1010ahd_reg_print_t ahd_lastphase_print;
1256#else 1011#else
1257#define ahd_lastphase_print(regvalue, cur_col, wrap) \ 1012#define ahd_lastphase_print(regvalue, cur_col, wrap) \
@@ -1273,20 +1028,6 @@ ahd_reg_print_t ahd_kernel_tqinpos_print;
1273#endif 1028#endif
1274 1029
1275#if AIC_DEBUG_REGISTERS 1030#if AIC_DEBUG_REGISTERS
1276ahd_reg_print_t ahd_tqinpos_print;
1277#else
1278#define ahd_tqinpos_print(regvalue, cur_col, wrap) \
1279 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap)
1280#endif
1281
1282#if AIC_DEBUG_REGISTERS
1283ahd_reg_print_t ahd_shared_data_addr_print;
1284#else
1285#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \
1286 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap)
1287#endif
1288
1289#if AIC_DEBUG_REGISTERS
1290ahd_reg_print_t ahd_qoutfifo_next_addr_print; 1031ahd_reg_print_t ahd_qoutfifo_next_addr_print;
1291#else 1032#else
1292#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 1033#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \
@@ -1294,20 +1035,6 @@ ahd_reg_print_t ahd_qoutfifo_next_addr_print;
1294#endif 1035#endif
1295 1036
1296#if AIC_DEBUG_REGISTERS 1037#if AIC_DEBUG_REGISTERS
1297ahd_reg_print_t ahd_arg_1_print;
1298#else
1299#define ahd_arg_1_print(regvalue, cur_col, wrap) \
1300 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap)
1301#endif
1302
1303#if AIC_DEBUG_REGISTERS
1304ahd_reg_print_t ahd_arg_2_print;
1305#else
1306#define ahd_arg_2_print(regvalue, cur_col, wrap) \
1307 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap)
1308#endif
1309
1310#if AIC_DEBUG_REGISTERS
1311ahd_reg_print_t ahd_last_msg_print; 1038ahd_reg_print_t ahd_last_msg_print;
1312#else 1039#else
1313#define ahd_last_msg_print(regvalue, cur_col, wrap) \ 1040#define ahd_last_msg_print(regvalue, cur_col, wrap) \
@@ -1406,13 +1133,6 @@ ahd_reg_print_t ahd_mk_message_scsiid_print;
1406#endif 1133#endif
1407 1134
1408#if AIC_DEBUG_REGISTERS 1135#if AIC_DEBUG_REGISTERS
1409ahd_reg_print_t ahd_scb_residual_datacnt_print;
1410#else
1411#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
1412 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
1413#endif
1414
1415#if AIC_DEBUG_REGISTERS
1416ahd_reg_print_t ahd_scb_base_print; 1136ahd_reg_print_t ahd_scb_base_print;
1417#else 1137#else
1418#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 1138#define ahd_scb_base_print(regvalue, cur_col, wrap) \
@@ -1420,17 +1140,10 @@ ahd_reg_print_t ahd_scb_base_print;
1420#endif 1140#endif
1421 1141
1422#if AIC_DEBUG_REGISTERS 1142#if AIC_DEBUG_REGISTERS
1423ahd_reg_print_t ahd_scb_residual_sgptr_print; 1143ahd_reg_print_t ahd_scb_residual_datacnt_print;
1424#else
1425#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
1426 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap)
1427#endif
1428
1429#if AIC_DEBUG_REGISTERS
1430ahd_reg_print_t ahd_scb_scsi_status_print;
1431#else 1144#else
1432#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 1145#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
1433 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 1146 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
1434#endif 1147#endif
1435 1148
1436#if AIC_DEBUG_REGISTERS 1149#if AIC_DEBUG_REGISTERS
@@ -1476,13 +1189,6 @@ ahd_reg_print_t ahd_scb_task_attribute_print;
1476#endif 1189#endif
1477 1190
1478#if AIC_DEBUG_REGISTERS 1191#if AIC_DEBUG_REGISTERS
1479ahd_reg_print_t ahd_scb_cdb_len_print;
1480#else
1481#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \
1482 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap)
1483#endif
1484
1485#if AIC_DEBUG_REGISTERS
1486ahd_reg_print_t ahd_scb_task_management_print; 1192ahd_reg_print_t ahd_scb_task_management_print;
1487#else 1193#else
1488#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 1194#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \
@@ -1518,13 +1224,6 @@ ahd_reg_print_t ahd_scb_busaddr_print;
1518#endif 1224#endif
1519 1225
1520#if AIC_DEBUG_REGISTERS 1226#if AIC_DEBUG_REGISTERS
1521ahd_reg_print_t ahd_scb_next_print;
1522#else
1523#define ahd_scb_next_print(regvalue, cur_col, wrap) \
1524 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap)
1525#endif
1526
1527#if AIC_DEBUG_REGISTERS
1528ahd_reg_print_t ahd_scb_next2_print; 1227ahd_reg_print_t ahd_scb_next2_print;
1529#else 1228#else
1530#define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 1229#define ahd_scb_next2_print(regvalue, cur_col, wrap) \
@@ -1717,10 +1416,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1717 1416
1718#define SG_CACHE_PRE 0x1b 1417#define SG_CACHE_PRE 0x1b
1719 1418
1720#define TYPEPTR 0x20
1721
1722#define LQIN 0x20 1419#define LQIN 0x20
1723 1420
1421#define TYPEPTR 0x20
1422
1724#define TAGPTR 0x21 1423#define TAGPTR 0x21
1725 1424
1726#define LUNPTR 0x22 1425#define LUNPTR 0x22
@@ -1780,6 +1479,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1780#define SINGLECMD 0x02 1479#define SINGLECMD 0x02
1781#define ABORTPENDING 0x01 1480#define ABORTPENDING 0x01
1782 1481
1482#define SCSBIST0 0x39
1483#define GSBISTERR 0x40
1484#define GSBISTDONE 0x20
1485#define GSBISTRUN 0x10
1486#define OSBISTERR 0x04
1487#define OSBISTDONE 0x02
1488#define OSBISTRUN 0x01
1489
1783#define LQCTL2 0x39 1490#define LQCTL2 0x39
1784#define LQIRETRY 0x80 1491#define LQIRETRY 0x80
1785#define LQICONTINUE 0x40 1492#define LQICONTINUE 0x40
@@ -1790,13 +1497,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1790#define LQOTOIDLE 0x02 1497#define LQOTOIDLE 0x02
1791#define LQOPAUSE 0x01 1498#define LQOPAUSE 0x01
1792 1499
1793#define SCSBIST0 0x39 1500#define SCSBIST1 0x3a
1794#define GSBISTERR 0x40 1501#define NTBISTERR 0x04
1795#define GSBISTDONE 0x20 1502#define NTBISTDONE 0x02
1796#define GSBISTRUN 0x10 1503#define NTBISTRUN 0x01
1797#define OSBISTERR 0x04
1798#define OSBISTDONE 0x02
1799#define OSBISTRUN 0x01
1800 1504
1801#define SCSISEQ0 0x3a 1505#define SCSISEQ0 0x3a
1802#define TEMODEO 0x80 1506#define TEMODEO 0x80
@@ -1805,15 +1509,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1805#define FORCEBUSFREE 0x10 1509#define FORCEBUSFREE 0x10
1806#define SCSIRSTO 0x01 1510#define SCSIRSTO 0x01
1807 1511
1808#define SCSBIST1 0x3a
1809#define NTBISTERR 0x04
1810#define NTBISTDONE 0x02
1811#define NTBISTRUN 0x01
1812
1813#define SCSISEQ1 0x3b 1512#define SCSISEQ1 0x3b
1814 1513
1815#define BUSINITID 0x3c
1816
1817#define SXFRCTL0 0x3c 1514#define SXFRCTL0 0x3c
1818#define DFON 0x80 1515#define DFON 0x80
1819#define DFPEXP 0x40 1516#define DFPEXP 0x40
@@ -1822,6 +1519,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1822 1519
1823#define DLCOUNT 0x3c 1520#define DLCOUNT 0x3c
1824 1521
1522#define BUSINITID 0x3c
1523
1825#define SXFRCTL1 0x3d 1524#define SXFRCTL1 0x3d
1826#define BITBUCKET 0x80 1525#define BITBUCKET 0x80
1827#define ENSACHK 0x40 1526#define ENSACHK 0x40
@@ -1846,8 +1545,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1846#define CURRFIFO_1 0x01 1545#define CURRFIFO_1 0x01
1847#define CURRFIFO_0 0x00 1546#define CURRFIFO_0 0x00
1848 1547
1849#define MULTARGID 0x40
1850
1851#define SCSISIGO 0x40 1548#define SCSISIGO 0x40
1852#define CDO 0x80 1549#define CDO 0x80
1853#define IOO 0x40 1550#define IOO 0x40
@@ -1858,6 +1555,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1858#define REQO 0x02 1555#define REQO 0x02
1859#define ACKO 0x01 1556#define ACKO 0x01
1860 1557
1558#define MULTARGID 0x40
1559
1861#define SCSISIGI 0x41 1560#define SCSISIGI 0x41
1862#define ATNI 0x10 1561#define ATNI 0x10
1863#define SELI 0x08 1562#define SELI 0x08
@@ -1904,6 +1603,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1904#define ENAB20 0x04 1603#define ENAB20 0x04
1905#define SELWIDE 0x02 1604#define SELWIDE 0x02
1906 1605
1606#define CLRSINT0 0x4b
1607#define CLRSELDO 0x40
1608#define CLRSELDI 0x20
1609#define CLRSELINGO 0x10
1610#define CLRIOERR 0x08
1611#define CLROVERRUN 0x04
1612#define CLRSPIORDY 0x02
1613#define CLRARBDO 0x01
1614
1907#define SSTAT0 0x4b 1615#define SSTAT0 0x4b
1908#define TARGET 0x80 1616#define TARGET 0x80
1909#define SELDO 0x40 1617#define SELDO 0x40
@@ -1923,14 +1631,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1923#define ENSPIORDY 0x02 1631#define ENSPIORDY 0x02
1924#define ENARBDO 0x01 1632#define ENARBDO 0x01
1925 1633
1926#define CLRSINT0 0x4b 1634#define CLRSINT1 0x4c
1927#define CLRSELDO 0x40 1635#define CLRSELTIMEO 0x80
1928#define CLRSELDI 0x20 1636#define CLRATNO 0x40
1929#define CLRSELINGO 0x10 1637#define CLRSCSIRSTI 0x20
1930#define CLRIOERR 0x08 1638#define CLRBUSFREE 0x08
1931#define CLROVERRUN 0x04 1639#define CLRSCSIPERR 0x04
1932#define CLRSPIORDY 0x02 1640#define CLRSTRB2FAST 0x02
1933#define CLRARBDO 0x01 1641#define CLRREQINIT 0x01
1934 1642
1935#define SSTAT1 0x4c 1643#define SSTAT1 0x4c
1936#define SELTO 0x80 1644#define SELTO 0x80
@@ -1942,15 +1650,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1942#define STRB2FAST 0x02 1650#define STRB2FAST 0x02
1943#define REQINIT 0x01 1651#define REQINIT 0x01
1944 1652
1945#define CLRSINT1 0x4c
1946#define CLRSELTIMEO 0x80
1947#define CLRATNO 0x40
1948#define CLRSCSIRSTI 0x20
1949#define CLRBUSFREE 0x08
1950#define CLRSCSIPERR 0x04
1951#define CLRSTRB2FAST 0x02
1952#define CLRREQINIT 0x01
1953
1954#define SSTAT2 0x4d 1653#define SSTAT2 0x4d
1955#define BUSFREETIME 0xc0 1654#define BUSFREETIME 0xc0
1956#define NONPACKREQ 0x20 1655#define NONPACKREQ 0x20
@@ -1998,14 +1697,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
1998#define LQIATNLQ 0x02 1697#define LQIATNLQ 0x02
1999#define LQIATNCMD 0x01 1698#define LQIATNCMD 0x01
2000 1699
2001#define LQIMODE0 0x50
2002#define ENLQIATNQASK 0x20
2003#define ENLQICRCT1 0x10
2004#define ENLQICRCT2 0x08
2005#define ENLQIBADLQT 0x04
2006#define ENLQIATNLQ 0x02
2007#define ENLQIATNCMD 0x01
2008
2009#define CLRLQIINT0 0x50 1700#define CLRLQIINT0 0x50
2010#define CLRLQIATNQAS 0x20 1701#define CLRLQIATNQAS 0x20
2011#define CLRLQICRCT1 0x10 1702#define CLRLQICRCT1 0x10
@@ -2014,6 +1705,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2014#define CLRLQIATNLQ 0x02 1705#define CLRLQIATNLQ 0x02
2015#define CLRLQIATNCMD 0x01 1706#define CLRLQIATNCMD 0x01
2016 1707
1708#define LQIMODE0 0x50
1709#define ENLQIATNQASK 0x20
1710#define ENLQICRCT1 0x10
1711#define ENLQICRCT2 0x08
1712#define ENLQIBADLQT 0x04
1713#define ENLQIATNLQ 0x02
1714#define ENLQIATNCMD 0x01
1715
2017#define LQIMODE1 0x51 1716#define LQIMODE1 0x51
2018#define ENLQIPHASE_LQ 0x80 1717#define ENLQIPHASE_LQ 0x80
2019#define ENLQIPHASE_NLQ 0x40 1718#define ENLQIPHASE_NLQ 0x40
@@ -2160,6 +1859,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2160#define CFG4ICMD 0x02 1859#define CFG4ICMD 0x02
2161#define CFG4TCMD 0x01 1860#define CFG4TCMD 0x01
2162 1861
1862#define CURRSCB 0x5c
1863
2163#define SEQIMODE 0x5c 1864#define SEQIMODE 0x5c
2164#define ENCTXTDONE 0x40 1865#define ENCTXTDONE 0x40
2165#define ENSAVEPTRS 0x20 1866#define ENSAVEPTRS 0x20
@@ -2169,8 +1870,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2169#define ENCFG4ICMD 0x02 1870#define ENCFG4ICMD 0x02
2170#define ENCFG4TCMD 0x01 1871#define ENCFG4TCMD 0x01
2171 1872
2172#define CURRSCB 0x5c
2173
2174#define MDFFSTAT 0x5d 1873#define MDFFSTAT 0x5d
2175#define SHCNTNEGATIVE 0x40 1874#define SHCNTNEGATIVE 0x40
2176#define SHCNTMINUS1 0x20 1875#define SHCNTMINUS1 0x20
@@ -2185,29 +1884,29 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2185 1884
2186#define DFFTAG 0x5e 1885#define DFFTAG 0x5e
2187 1886
1887#define LASTSCB 0x5e
1888
2188#define SCSITEST 0x5e 1889#define SCSITEST 0x5e
2189#define CNTRTEST 0x08 1890#define CNTRTEST 0x08
2190#define SEL_TXPLL_DEBUG 0x04 1891#define SEL_TXPLL_DEBUG 0x04
2191 1892
2192#define LASTSCB 0x5e
2193
2194#define IOPDNCTL 0x5f 1893#define IOPDNCTL 0x5f
2195#define DISABLE_OE 0x80 1894#define DISABLE_OE 0x80
2196#define PDN_IDIST 0x04 1895#define PDN_IDIST 0x04
2197#define PDN_DIFFSENSE 0x01 1896#define PDN_DIFFSENSE 0x01
2198 1897
2199#define DGRPCRCI 0x60
2200
2201#define SHADDR 0x60 1898#define SHADDR 0x60
2202 1899
2203#define NEGOADDR 0x60 1900#define NEGOADDR 0x60
2204 1901
2205#define NEGPERIOD 0x61 1902#define DGRPCRCI 0x60
2206 1903
2207#define NEGOFFSET 0x62 1904#define NEGPERIOD 0x61
2208 1905
2209#define PACKCRCI 0x62 1906#define PACKCRCI 0x62
2210 1907
1908#define NEGOFFSET 0x62
1909
2211#define NEGPPROPTS 0x63 1910#define NEGPPROPTS 0x63
2212#define PPROPT_PACE 0x08 1911#define PPROPT_PACE 0x08
2213#define PPROPT_QAS 0x04 1912#define PPROPT_QAS 0x04
@@ -2253,8 +1952,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2253 1952
2254#define SELOID 0x6b 1953#define SELOID 0x6b
2255 1954
2256#define FAIRNESS 0x6c
2257
2258#define PLL400CTL0 0x6c 1955#define PLL400CTL0 0x6c
2259#define PLL_VCOSEL 0x80 1956#define PLL_VCOSEL 0x80
2260#define PLL_PWDN 0x40 1957#define PLL_PWDN 0x40
@@ -2264,6 +1961,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2264#define PLL_DLPF 0x02 1961#define PLL_DLPF 0x02
2265#define PLL_ENFBM 0x01 1962#define PLL_ENFBM 0x01
2266 1963
1964#define FAIRNESS 0x6c
1965
2267#define PLL400CTL1 0x6d 1966#define PLL400CTL1 0x6d
2268#define PLL_CNTEN 0x80 1967#define PLL_CNTEN 0x80
2269#define PLL_CNTCLR 0x40 1968#define PLL_CNTCLR 0x40
@@ -2275,25 +1974,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2275 1974
2276#define HADDR 0x70 1975#define HADDR 0x70
2277 1976
2278#define HODMAADR 0x70
2279
2280#define PLLDELAY 0x70 1977#define PLLDELAY 0x70
2281#define SPLIT_DROP_REQ 0x80 1978#define SPLIT_DROP_REQ 0x80
2282 1979
2283#define HCNT 0x78 1980#define HODMAADR 0x70
2284 1981
2285#define HODMACNT 0x78 1982#define HODMACNT 0x78
2286 1983
2287#define HODMAEN 0x7a 1984#define HCNT 0x78
2288 1985
2289#define SGHADDR 0x7c 1986#define HODMAEN 0x7a
2290 1987
2291#define SCBHADDR 0x7c 1988#define SCBHADDR 0x7c
2292 1989
2293#define SGHCNT 0x84 1990#define SGHADDR 0x7c
2294 1991
2295#define SCBHCNT 0x84 1992#define SCBHCNT 0x84
2296 1993
1994#define SGHCNT 0x84
1995
2297#define DFF_THRSH 0x88 1996#define DFF_THRSH 0x88
2298#define WR_DFTHRSH 0x70 1997#define WR_DFTHRSH 0x70
2299#define RD_DFTHRSH 0x07 1998#define RD_DFTHRSH 0x07
@@ -2326,10 +2025,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2326 2025
2327#define CMCRXMSG0 0x90 2026#define CMCRXMSG0 0x90
2328 2027
2329#define OVLYRXMSG0 0x90
2330
2331#define DCHRXMSG0 0x90
2332
2333#define ROENABLE 0x90 2028#define ROENABLE 0x90
2334#define MSIROEN 0x20 2029#define MSIROEN 0x20
2335#define OVLYROEN 0x10 2030#define OVLYROEN 0x10
@@ -2338,11 +2033,11 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2338#define DCH1ROEN 0x02 2033#define DCH1ROEN 0x02
2339#define DCH0ROEN 0x01 2034#define DCH0ROEN 0x01
2340 2035
2341#define OVLYRXMSG1 0x91 2036#define OVLYRXMSG0 0x90
2342 2037
2343#define CMCRXMSG1 0x91 2038#define DCHRXMSG0 0x90
2344 2039
2345#define DCHRXMSG1 0x91 2040#define OVLYRXMSG1 0x91
2346 2041
2347#define NSENABLE 0x91 2042#define NSENABLE 0x91
2348#define MSINSEN 0x20 2043#define MSINSEN 0x20
@@ -2352,6 +2047,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2352#define DCH1NSEN 0x02 2047#define DCH1NSEN 0x02
2353#define DCH0NSEN 0x01 2048#define DCH0NSEN 0x01
2354 2049
2050#define CMCRXMSG1 0x91
2051
2052#define DCHRXMSG1 0x91
2053
2355#define DCHRXMSG2 0x92 2054#define DCHRXMSG2 0x92
2356 2055
2357#define CMCRXMSG2 0x92 2056#define CMCRXMSG2 0x92
@@ -2375,24 +2074,24 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2375#define TSCSERREN 0x02 2074#define TSCSERREN 0x02
2376#define CMPABCDIS 0x01 2075#define CMPABCDIS 0x01
2377 2076
2378#define CMCSEQBCNT 0x94
2379
2380#define OVLYSEQBCNT 0x94 2077#define OVLYSEQBCNT 0x94
2381 2078
2382#define DCHSEQBCNT 0x94 2079#define DCHSEQBCNT 0x94
2383 2080
2081#define CMCSEQBCNT 0x94
2082
2083#define CMCSPLTSTAT0 0x96
2084
2384#define DCHSPLTSTAT0 0x96 2085#define DCHSPLTSTAT0 0x96
2385 2086
2386#define OVLYSPLTSTAT0 0x96 2087#define OVLYSPLTSTAT0 0x96
2387 2088
2388#define CMCSPLTSTAT0 0x96 2089#define CMCSPLTSTAT1 0x97
2389 2090
2390#define OVLYSPLTSTAT1 0x97 2091#define OVLYSPLTSTAT1 0x97
2391 2092
2392#define DCHSPLTSTAT1 0x97 2093#define DCHSPLTSTAT1 0x97
2393 2094
2394#define CMCSPLTSTAT1 0x97
2395
2396#define SGRXMSG0 0x98 2095#define SGRXMSG0 0x98
2397#define CDNUM 0xf8 2096#define CDNUM 0xf8
2398#define CFNUM 0x07 2097#define CFNUM 0x07
@@ -2420,15 +2119,18 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2420#define TAG_NUM 0x1f 2119#define TAG_NUM 0x1f
2421#define RLXORD 0x10 2120#define RLXORD 0x10
2422 2121
2122#define SGSEQBCNT 0x9c
2123
2423#define SLVSPLTOUTATTR0 0x9c 2124#define SLVSPLTOUTATTR0 0x9c
2424#define LOWER_BCNT 0xff 2125#define LOWER_BCNT 0xff
2425 2126
2426#define SGSEQBCNT 0x9c
2427
2428#define SLVSPLTOUTATTR1 0x9d 2127#define SLVSPLTOUTATTR1 0x9d
2429#define CMPLT_DNUM 0xf8 2128#define CMPLT_DNUM 0xf8
2430#define CMPLT_FNUM 0x07 2129#define CMPLT_FNUM 0x07
2431 2130
2131#define SLVSPLTOUTATTR2 0x9e
2132#define CMPLT_BNUM 0xff
2133
2432#define SGSPLTSTAT0 0x9e 2134#define SGSPLTSTAT0 0x9e
2433#define STAETERM 0x80 2135#define STAETERM 0x80
2434#define SCBCERR 0x40 2136#define SCBCERR 0x40
@@ -2439,9 +2141,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2439#define RXSCEMSG 0x02 2141#define RXSCEMSG 0x02
2440#define RXSPLTRSP 0x01 2142#define RXSPLTRSP 0x01
2441 2143
2442#define SLVSPLTOUTATTR2 0x9e
2443#define CMPLT_BNUM 0xff
2444
2445#define SGSPLTSTAT1 0x9f 2144#define SGSPLTSTAT1 0x9f
2446#define RXDATABUCKET 0x01 2145#define RXDATABUCKET 0x01
2447 2146
@@ -2497,10 +2196,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2497 2196
2498#define CCSGADDR 0xac 2197#define CCSGADDR 0xac
2499 2198
2500#define CCSCBADDR 0xac
2501
2502#define CCSCBADR_BK 0xac 2199#define CCSCBADR_BK 0xac
2503 2200
2201#define CCSCBADDR 0xac
2202
2504#define CMC_RAMBIST 0xad 2203#define CMC_RAMBIST 0xad
2505#define SG_ELEMENT_SIZE 0x80 2204#define SG_ELEMENT_SIZE 0x80
2506#define SCBRAMBIST_FAIL 0x40 2205#define SCBRAMBIST_FAIL 0x40
@@ -2554,9 +2253,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2554#define SEEDAT 0xbc 2253#define SEEDAT 0xbc
2555 2254
2556#define SEECTL 0xbe 2255#define SEECTL 0xbe
2557#define SEEOP_EWDS 0x40
2558#define SEEOP_WALL 0x40 2256#define SEEOP_WALL 0x40
2559#define SEEOP_EWEN 0x40 2257#define SEEOP_EWEN 0x40
2258#define SEEOP_EWDS 0x40
2560#define SEEOPCODE 0x70 2259#define SEEOPCODE 0x70
2561#define SEERST 0x02 2260#define SEERST 0x02
2562#define SEESTART 0x01 2261#define SEESTART 0x01
@@ -2573,25 +2272,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2573 2272
2574#define SCBCNT 0xbf 2273#define SCBCNT 0xbf
2575 2274
2275#define DFWADDR 0xc0
2276
2576#define DSPFLTRCTL 0xc0 2277#define DSPFLTRCTL 0xc0
2577#define FLTRDISABLE 0x20 2278#define FLTRDISABLE 0x20
2578#define EDGESENSE 0x10 2279#define EDGESENSE 0x10
2579#define DSPFCNTSEL 0x0f 2280#define DSPFCNTSEL 0x0f
2580 2281
2581#define DFWADDR 0xc0
2582
2583#define DSPDATACTL 0xc1 2282#define DSPDATACTL 0xc1
2584#define BYPASSENAB 0x80 2283#define BYPASSENAB 0x80
2585#define DESQDIS 0x10 2284#define DESQDIS 0x10
2586#define RCVROFFSTDIS 0x04 2285#define RCVROFFSTDIS 0x04
2587#define XMITOFFSTDIS 0x02 2286#define XMITOFFSTDIS 0x02
2588 2287
2288#define DFRADDR 0xc2
2289
2589#define DSPREQCTL 0xc2 2290#define DSPREQCTL 0xc2
2590#define MANREQCTL 0xc0 2291#define MANREQCTL 0xc0
2591#define MANREQDLY 0x3f 2292#define MANREQDLY 0x3f
2592 2293
2593#define DFRADDR 0xc2
2594
2595#define DSPACKCTL 0xc3 2294#define DSPACKCTL 0xc3
2596#define MANACKCTL 0xc0 2295#define MANACKCTL 0xc0
2597#define MANACKDLY 0x3f 2296#define MANACKDLY 0x3f
@@ -2612,14 +2311,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2612 2311
2613#define WRTBIASCALC 0xc7 2312#define WRTBIASCALC 0xc7
2614 2313
2615#define DFPTRS 0xc8
2616
2617#define RCVRBIASCALC 0xc8 2314#define RCVRBIASCALC 0xc8
2618 2315
2619#define DFBKPTR 0xc9 2316#define DFPTRS 0xc8
2620 2317
2621#define SKEWCALC 0xc9 2318#define SKEWCALC 0xc9
2622 2319
2320#define DFBKPTR 0xc9
2321
2623#define DFDBCTL 0xcb 2322#define DFDBCTL 0xcb
2624#define DFF_CIO_WR_RDY 0x20 2323#define DFF_CIO_WR_RDY 0x20
2625#define DFF_CIO_RD_RDY 0x10 2324#define DFF_CIO_RD_RDY 0x10
@@ -2704,12 +2403,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2704 2403
2705#define ACCUM_SAVE 0xfa 2404#define ACCUM_SAVE 0xfa
2706 2405
2406#define WAITING_SCB_TAILS 0x100
2407
2707#define AHD_PCI_CONFIG_BASE 0x100 2408#define AHD_PCI_CONFIG_BASE 0x100
2708 2409
2709#define SRAM_BASE 0x100 2410#define SRAM_BASE 0x100
2710 2411
2711#define WAITING_SCB_TAILS 0x100
2712
2713#define WAITING_TID_HEAD 0x120 2412#define WAITING_TID_HEAD 0x120
2714 2413
2715#define WAITING_TID_TAIL 0x122 2414#define WAITING_TID_TAIL 0x122
@@ -2738,8 +2437,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2738#define PRELOADEN 0x80 2437#define PRELOADEN 0x80
2739#define WIDEODD 0x40 2438#define WIDEODD 0x40
2740#define SCSIEN 0x20 2439#define SCSIEN 0x20
2741#define SDMAENACK 0x10
2742#define SDMAEN 0x10 2440#define SDMAEN 0x10
2441#define SDMAENACK 0x10
2743#define HDMAEN 0x08 2442#define HDMAEN 0x08
2744#define HDMAENACK 0x08 2443#define HDMAENACK 0x08
2745#define DIRECTION 0x04 2444#define DIRECTION 0x04
@@ -2837,12 +2536,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2837 2536
2838#define MK_MESSAGE_SCSIID 0x162 2537#define MK_MESSAGE_SCSIID 0x162
2839 2538
2539#define SCB_BASE 0x180
2540
2840#define SCB_RESIDUAL_DATACNT 0x180 2541#define SCB_RESIDUAL_DATACNT 0x180
2841#define SCB_CDB_STORE 0x180 2542#define SCB_CDB_STORE 0x180
2842#define SCB_HOST_CDB_PTR 0x180 2543#define SCB_HOST_CDB_PTR 0x180
2843 2544
2844#define SCB_BASE 0x180
2845
2846#define SCB_RESIDUAL_SGPTR 0x184 2545#define SCB_RESIDUAL_SGPTR 0x184
2847#define SG_ADDR_MASK 0xf8 2546#define SG_ADDR_MASK 0xf8
2848#define SG_OVERRUN_RESID 0x02 2547#define SG_OVERRUN_RESID 0x02
@@ -2910,17 +2609,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2910#define SCB_DISCONNECTED_LISTS 0x1b8 2609#define SCB_DISCONNECTED_LISTS 0x1b8
2911 2610
2912 2611
2913#define CMD_GROUP_CODE_SHIFT 0x05
2914#define STIMESEL_MIN 0x18
2915#define STIMESEL_SHIFT 0x03
2916#define INVALID_ADDR 0x80
2917#define AHD_PRECOMP_MASK 0x07
2918#define TARGET_DATA_IN 0x01
2919#define CCSCBADDR_MAX 0x80
2920#define NUMDSPS 0x14
2921#define SEEOP_EWEN_ADDR 0xc0
2922#define AHD_ANNEXCOL_PER_DEV0 0x04
2923#define DST_MODE_SHIFT 0x04
2924#define AHD_TIMER_MAX_US 0x18ffe7 2612#define AHD_TIMER_MAX_US 0x18ffe7
2925#define AHD_TIMER_MAX_TICKS 0xffff 2613#define AHD_TIMER_MAX_TICKS 0xffff
2926#define AHD_SENSE_BUFSIZE 0x100 2614#define AHD_SENSE_BUFSIZE 0x100
@@ -2955,32 +2643,43 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2955#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 2643#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
2956#define NVRAM_SCB_OFFSET 0x2c 2644#define NVRAM_SCB_OFFSET 0x2c
2957#define STATUS_PKT_SENSE 0xff 2645#define STATUS_PKT_SENSE 0xff
2646#define CMD_GROUP_CODE_SHIFT 0x05
2958#define MAX_OFFSET_PACED_BUG 0x7f 2647#define MAX_OFFSET_PACED_BUG 0x7f
2959#define STIMESEL_BUG_ADJ 0x08 2648#define STIMESEL_BUG_ADJ 0x08
2649#define STIMESEL_MIN 0x18
2650#define STIMESEL_SHIFT 0x03
2960#define CCSGRAM_MAXSEGS 0x10 2651#define CCSGRAM_MAXSEGS 0x10
2652#define INVALID_ADDR 0x80
2961#define SEEOP_ERAL_ADDR 0x80 2653#define SEEOP_ERAL_ADDR 0x80
2962#define AHD_SLEWRATE_DEF_REVB 0x08 2654#define AHD_SLEWRATE_DEF_REVB 0x08
2963#define AHD_PRECOMP_CUTBACK_17 0x04 2655#define AHD_PRECOMP_CUTBACK_17 0x04
2656#define AHD_PRECOMP_MASK 0x07
2964#define SRC_MODE_SHIFT 0x00 2657#define SRC_MODE_SHIFT 0x00
2965#define PKT_OVERRUN_BUFSIZE 0x200 2658#define PKT_OVERRUN_BUFSIZE 0x200
2966#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 2659#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
2660#define TARGET_DATA_IN 0x01
2967#define HOST_MSG 0xff 2661#define HOST_MSG 0xff
2968#define MAX_OFFSET 0xfe 2662#define MAX_OFFSET 0xfe
2969#define BUS_16_BIT 0x01 2663#define BUS_16_BIT 0x01
2664#define CCSCBADDR_MAX 0x80
2665#define NUMDSPS 0x14
2666#define SEEOP_EWEN_ADDR 0xc0
2667#define AHD_ANNEXCOL_PER_DEV0 0x04
2668#define DST_MODE_SHIFT 0x04
2970 2669
2971 2670
2972/* Downloaded Constant Definitions */ 2671/* Downloaded Constant Definitions */
2973#define SG_SIZEOF 0x04
2974#define SG_PREFETCH_ALIGN_MASK 0x02
2975#define SG_PREFETCH_CNT_LIMIT 0x01
2976#define CACHELINE_MASK 0x07 2672#define CACHELINE_MASK 0x07
2977#define SCB_TRANSFER_SIZE 0x06 2673#define SCB_TRANSFER_SIZE 0x06
2978#define PKT_OVERRUN_BUFOFFSET 0x05 2674#define PKT_OVERRUN_BUFOFFSET 0x05
2675#define SG_SIZEOF 0x04
2979#define SG_PREFETCH_ADDR_MASK 0x03 2676#define SG_PREFETCH_ADDR_MASK 0x03
2677#define SG_PREFETCH_ALIGN_MASK 0x02
2678#define SG_PREFETCH_CNT_LIMIT 0x01
2980#define SG_PREFETCH_CNT 0x00 2679#define SG_PREFETCH_CNT 0x00
2981#define DOWNLOAD_CONST_COUNT 0x08 2680#define DOWNLOAD_CONST_COUNT 0x08
2982 2681
2983 2682
2984/* Exported Labels */ 2683/* Exported Labels */
2985#define LABEL_timer_isr 0x28b
2986#define LABEL_seq_isr 0x28f 2684#define LABEL_seq_isr 0x28f
2685#define LABEL_timer_isr 0x28b
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-14 04:32:32 -0400