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-rw-r--r--drivers/scsi/aic7xxx/aic79xx_reg.h_shipped1145
1 files changed, 154 insertions, 991 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
index 2068e00d2c75..c21ceab8e913 100644
--- a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
+++ b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped
@@ -48,13 +48,6 @@ ahd_reg_print_t ahd_error_print;
48#endif 48#endif
49 49
50#if AIC_DEBUG_REGISTERS 50#if AIC_DEBUG_REGISTERS
51ahd_reg_print_t ahd_clrerr_print;
52#else
53#define ahd_clrerr_print(regvalue, cur_col, wrap) \
54 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap)
55#endif
56
57#if AIC_DEBUG_REGISTERS
58ahd_reg_print_t ahd_hcntrl_print; 51ahd_reg_print_t ahd_hcntrl_print;
59#else 52#else
60#define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 53#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
@@ -167,13 +160,6 @@ ahd_reg_print_t ahd_sg_cache_shadow_print;
167#endif 160#endif
168 161
169#if AIC_DEBUG_REGISTERS 162#if AIC_DEBUG_REGISTERS
170ahd_reg_print_t ahd_arbctl_print;
171#else
172#define ahd_arbctl_print(regvalue, cur_col, wrap) \
173 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
174#endif
175
176#if AIC_DEBUG_REGISTERS
177ahd_reg_print_t ahd_sg_cache_pre_print; 163ahd_reg_print_t ahd_sg_cache_pre_print;
178#else 164#else
179#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 165#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
@@ -188,20 +174,6 @@ ahd_reg_print_t ahd_lqin_print;
188#endif 174#endif
189 175
190#if AIC_DEBUG_REGISTERS 176#if AIC_DEBUG_REGISTERS
191ahd_reg_print_t ahd_typeptr_print;
192#else
193#define ahd_typeptr_print(regvalue, cur_col, wrap) \
194 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
195#endif
196
197#if AIC_DEBUG_REGISTERS
198ahd_reg_print_t ahd_tagptr_print;
199#else
200#define ahd_tagptr_print(regvalue, cur_col, wrap) \
201 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap)
202#endif
203
204#if AIC_DEBUG_REGISTERS
205ahd_reg_print_t ahd_lunptr_print; 177ahd_reg_print_t ahd_lunptr_print;
206#else 178#else
207#define ahd_lunptr_print(regvalue, cur_col, wrap) \ 179#define ahd_lunptr_print(regvalue, cur_col, wrap) \
@@ -209,20 +181,6 @@ ahd_reg_print_t ahd_lunptr_print;
209#endif 181#endif
210 182
211#if AIC_DEBUG_REGISTERS 183#if AIC_DEBUG_REGISTERS
212ahd_reg_print_t ahd_datalenptr_print;
213#else
214#define ahd_datalenptr_print(regvalue, cur_col, wrap) \
215 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap)
216#endif
217
218#if AIC_DEBUG_REGISTERS
219ahd_reg_print_t ahd_statlenptr_print;
220#else
221#define ahd_statlenptr_print(regvalue, cur_col, wrap) \
222 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap)
223#endif
224
225#if AIC_DEBUG_REGISTERS
226ahd_reg_print_t ahd_cmdlenptr_print; 184ahd_reg_print_t ahd_cmdlenptr_print;
227#else 185#else
228#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 186#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
@@ -258,13 +216,6 @@ ahd_reg_print_t ahd_qnextptr_print;
258#endif 216#endif
259 217
260#if AIC_DEBUG_REGISTERS 218#if AIC_DEBUG_REGISTERS
261ahd_reg_print_t ahd_idptr_print;
262#else
263#define ahd_idptr_print(regvalue, cur_col, wrap) \
264 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap)
265#endif
266
267#if AIC_DEBUG_REGISTERS
268ahd_reg_print_t ahd_abrtbyteptr_print; 219ahd_reg_print_t ahd_abrtbyteptr_print;
269#else 220#else
270#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 221#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
@@ -279,27 +230,6 @@ ahd_reg_print_t ahd_abrtbitptr_print;
279#endif 230#endif
280 231
281#if AIC_DEBUG_REGISTERS 232#if AIC_DEBUG_REGISTERS
282ahd_reg_print_t ahd_maxcmdbytes_print;
283#else
284#define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \
285 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap)
286#endif
287
288#if AIC_DEBUG_REGISTERS
289ahd_reg_print_t ahd_maxcmd2rcv_print;
290#else
291#define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \
292 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap)
293#endif
294
295#if AIC_DEBUG_REGISTERS
296ahd_reg_print_t ahd_shortthresh_print;
297#else
298#define ahd_shortthresh_print(regvalue, cur_col, wrap) \
299 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahd_reg_print_t ahd_lunlen_print; 233ahd_reg_print_t ahd_lunlen_print;
304#else 234#else
305#define ahd_lunlen_print(regvalue, cur_col, wrap) \ 235#define ahd_lunlen_print(regvalue, cur_col, wrap) \
@@ -328,41 +258,6 @@ ahd_reg_print_t ahd_maxcmdcnt_print;
328#endif 258#endif
329 259
330#if AIC_DEBUG_REGISTERS 260#if AIC_DEBUG_REGISTERS
331ahd_reg_print_t ahd_lqrsvd01_print;
332#else
333#define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \
334 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap)
335#endif
336
337#if AIC_DEBUG_REGISTERS
338ahd_reg_print_t ahd_lqrsvd16_print;
339#else
340#define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \
341 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap)
342#endif
343
344#if AIC_DEBUG_REGISTERS
345ahd_reg_print_t ahd_lqrsvd17_print;
346#else
347#define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \
348 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap)
349#endif
350
351#if AIC_DEBUG_REGISTERS
352ahd_reg_print_t ahd_cmdrsvd0_print;
353#else
354#define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \
355 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap)
356#endif
357
358#if AIC_DEBUG_REGISTERS
359ahd_reg_print_t ahd_lqctl0_print;
360#else
361#define ahd_lqctl0_print(regvalue, cur_col, wrap) \
362 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap)
363#endif
364
365#if AIC_DEBUG_REGISTERS
366ahd_reg_print_t ahd_lqctl1_print; 261ahd_reg_print_t ahd_lqctl1_print;
367#else 262#else
368#define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 263#define ahd_lqctl1_print(regvalue, cur_col, wrap) \
@@ -370,13 +265,6 @@ ahd_reg_print_t ahd_lqctl1_print;
370#endif 265#endif
371 266
372#if AIC_DEBUG_REGISTERS 267#if AIC_DEBUG_REGISTERS
373ahd_reg_print_t ahd_scsbist0_print;
374#else
375#define ahd_scsbist0_print(regvalue, cur_col, wrap) \
376 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap)
377#endif
378
379#if AIC_DEBUG_REGISTERS
380ahd_reg_print_t ahd_lqctl2_print; 268ahd_reg_print_t ahd_lqctl2_print;
381#else 269#else
382#define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 270#define ahd_lqctl2_print(regvalue, cur_col, wrap) \
@@ -384,13 +272,6 @@ ahd_reg_print_t ahd_lqctl2_print;
384#endif 272#endif
385 273
386#if AIC_DEBUG_REGISTERS 274#if AIC_DEBUG_REGISTERS
387ahd_reg_print_t ahd_scsbist1_print;
388#else
389#define ahd_scsbist1_print(regvalue, cur_col, wrap) \
390 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap)
391#endif
392
393#if AIC_DEBUG_REGISTERS
394ahd_reg_print_t ahd_scsiseq0_print; 275ahd_reg_print_t ahd_scsiseq0_print;
395#else 276#else
396#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 277#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
@@ -412,20 +293,6 @@ ahd_reg_print_t ahd_sxfrctl0_print;
412#endif 293#endif
413 294
414#if AIC_DEBUG_REGISTERS 295#if AIC_DEBUG_REGISTERS
415ahd_reg_print_t ahd_dlcount_print;
416#else
417#define ahd_dlcount_print(regvalue, cur_col, wrap) \
418 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
419#endif
420
421#if AIC_DEBUG_REGISTERS
422ahd_reg_print_t ahd_businitid_print;
423#else
424#define ahd_businitid_print(regvalue, cur_col, wrap) \
425 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap)
426#endif
427
428#if AIC_DEBUG_REGISTERS
429ahd_reg_print_t ahd_sxfrctl1_print; 296ahd_reg_print_t ahd_sxfrctl1_print;
430#else 297#else
431#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 298#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
@@ -433,20 +300,6 @@ ahd_reg_print_t ahd_sxfrctl1_print;
433#endif 300#endif
434 301
435#if AIC_DEBUG_REGISTERS 302#if AIC_DEBUG_REGISTERS
436ahd_reg_print_t ahd_bustargid_print;
437#else
438#define ahd_bustargid_print(regvalue, cur_col, wrap) \
439 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap)
440#endif
441
442#if AIC_DEBUG_REGISTERS
443ahd_reg_print_t ahd_sxfrctl2_print;
444#else
445#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
446 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
447#endif
448
449#if AIC_DEBUG_REGISTERS
450ahd_reg_print_t ahd_dffstat_print; 303ahd_reg_print_t ahd_dffstat_print;
451#else 304#else
452#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 305#define ahd_dffstat_print(regvalue, cur_col, wrap) \
@@ -454,17 +307,17 @@ ahd_reg_print_t ahd_dffstat_print;
454#endif 307#endif
455 308
456#if AIC_DEBUG_REGISTERS 309#if AIC_DEBUG_REGISTERS
457ahd_reg_print_t ahd_scsisigo_print; 310ahd_reg_print_t ahd_multargid_print;
458#else 311#else
459#define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 312#define ahd_multargid_print(regvalue, cur_col, wrap) \
460 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 313 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
461#endif 314#endif
462 315
463#if AIC_DEBUG_REGISTERS 316#if AIC_DEBUG_REGISTERS
464ahd_reg_print_t ahd_multargid_print; 317ahd_reg_print_t ahd_scsisigo_print;
465#else 318#else
466#define ahd_multargid_print(regvalue, cur_col, wrap) \ 319#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
467 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 320 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
468#endif 321#endif
469 322
470#if AIC_DEBUG_REGISTERS 323#if AIC_DEBUG_REGISTERS
@@ -482,13 +335,6 @@ ahd_reg_print_t ahd_scsiphase_print;
482#endif 335#endif
483 336
484#if AIC_DEBUG_REGISTERS 337#if AIC_DEBUG_REGISTERS
485ahd_reg_print_t ahd_scsidat0_img_print;
486#else
487#define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \
488 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap)
489#endif
490
491#if AIC_DEBUG_REGISTERS
492ahd_reg_print_t ahd_scsidat_print; 338ahd_reg_print_t ahd_scsidat_print;
493#else 339#else
494#define ahd_scsidat_print(regvalue, cur_col, wrap) \ 340#define ahd_scsidat_print(regvalue, cur_col, wrap) \
@@ -531,13 +377,6 @@ ahd_reg_print_t ahd_sblkctl_print;
531#endif 377#endif
532 378
533#if AIC_DEBUG_REGISTERS 379#if AIC_DEBUG_REGISTERS
534ahd_reg_print_t ahd_clrsint0_print;
535#else
536#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
537 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
538#endif
539
540#if AIC_DEBUG_REGISTERS
541ahd_reg_print_t ahd_sstat0_print; 380ahd_reg_print_t ahd_sstat0_print;
542#else 381#else
543#define ahd_sstat0_print(regvalue, cur_col, wrap) \ 382#define ahd_sstat0_print(regvalue, cur_col, wrap) \
@@ -552,10 +391,10 @@ ahd_reg_print_t ahd_simode0_print;
552#endif 391#endif
553 392
554#if AIC_DEBUG_REGISTERS 393#if AIC_DEBUG_REGISTERS
555ahd_reg_print_t ahd_clrsint1_print; 394ahd_reg_print_t ahd_clrsint0_print;
556#else 395#else
557#define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 396#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
558 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 397 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
559#endif 398#endif
560 399
561#if AIC_DEBUG_REGISTERS 400#if AIC_DEBUG_REGISTERS
@@ -566,17 +405,17 @@ ahd_reg_print_t ahd_sstat1_print;
566#endif 405#endif
567 406
568#if AIC_DEBUG_REGISTERS 407#if AIC_DEBUG_REGISTERS
569ahd_reg_print_t ahd_sstat2_print; 408ahd_reg_print_t ahd_clrsint1_print;
570#else 409#else
571#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 410#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
572 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 411 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
573#endif 412#endif
574 413
575#if AIC_DEBUG_REGISTERS 414#if AIC_DEBUG_REGISTERS
576ahd_reg_print_t ahd_simode2_print; 415ahd_reg_print_t ahd_sstat2_print;
577#else 416#else
578#define ahd_simode2_print(regvalue, cur_col, wrap) \ 417#define ahd_sstat2_print(regvalue, cur_col, wrap) \
579 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 418 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
580#endif 419#endif
581 420
582#if AIC_DEBUG_REGISTERS 421#if AIC_DEBUG_REGISTERS
@@ -622,17 +461,17 @@ ahd_reg_print_t ahd_lqistat0_print;
622#endif 461#endif
623 462
624#if AIC_DEBUG_REGISTERS 463#if AIC_DEBUG_REGISTERS
625ahd_reg_print_t ahd_clrlqiint0_print; 464ahd_reg_print_t ahd_lqimode0_print;
626#else 465#else
627#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 466#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
628 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 467 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
629#endif 468#endif
630 469
631#if AIC_DEBUG_REGISTERS 470#if AIC_DEBUG_REGISTERS
632ahd_reg_print_t ahd_lqimode0_print; 471ahd_reg_print_t ahd_clrlqiint0_print;
633#else 472#else
634#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 473#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
635 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 474 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
636#endif 475#endif
637 476
638#if AIC_DEBUG_REGISTERS 477#if AIC_DEBUG_REGISTERS
@@ -790,13 +629,6 @@ ahd_reg_print_t ahd_seqintsrc_print;
790#endif 629#endif
791 630
792#if AIC_DEBUG_REGISTERS 631#if AIC_DEBUG_REGISTERS
793ahd_reg_print_t ahd_currscb_print;
794#else
795#define ahd_currscb_print(regvalue, cur_col, wrap) \
796 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
797#endif
798
799#if AIC_DEBUG_REGISTERS
800ahd_reg_print_t ahd_seqimode_print; 632ahd_reg_print_t ahd_seqimode_print;
801#else 633#else
802#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 634#define ahd_seqimode_print(regvalue, cur_col, wrap) \
@@ -804,24 +636,17 @@ ahd_reg_print_t ahd_seqimode_print;
804#endif 636#endif
805 637
806#if AIC_DEBUG_REGISTERS 638#if AIC_DEBUG_REGISTERS
807ahd_reg_print_t ahd_mdffstat_print; 639ahd_reg_print_t ahd_currscb_print;
808#else
809#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
810 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
811#endif
812
813#if AIC_DEBUG_REGISTERS
814ahd_reg_print_t ahd_crccontrol_print;
815#else 640#else
816#define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 641#define ahd_currscb_print(regvalue, cur_col, wrap) \
817 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 642 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
818#endif 643#endif
819 644
820#if AIC_DEBUG_REGISTERS 645#if AIC_DEBUG_REGISTERS
821ahd_reg_print_t ahd_dfftag_print; 646ahd_reg_print_t ahd_mdffstat_print;
822#else 647#else
823#define ahd_dfftag_print(regvalue, cur_col, wrap) \ 648#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
824 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 649 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
825#endif 650#endif
826 651
827#if AIC_DEBUG_REGISTERS 652#if AIC_DEBUG_REGISTERS
@@ -832,20 +657,6 @@ ahd_reg_print_t ahd_lastscb_print;
832#endif 657#endif
833 658
834#if AIC_DEBUG_REGISTERS 659#if AIC_DEBUG_REGISTERS
835ahd_reg_print_t ahd_scsitest_print;
836#else
837#define ahd_scsitest_print(regvalue, cur_col, wrap) \
838 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap)
839#endif
840
841#if AIC_DEBUG_REGISTERS
842ahd_reg_print_t ahd_iopdnctl_print;
843#else
844#define ahd_iopdnctl_print(regvalue, cur_col, wrap) \
845 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap)
846#endif
847
848#if AIC_DEBUG_REGISTERS
849ahd_reg_print_t ahd_shaddr_print; 660ahd_reg_print_t ahd_shaddr_print;
850#else 661#else
851#define ahd_shaddr_print(regvalue, cur_col, wrap) \ 662#define ahd_shaddr_print(regvalue, cur_col, wrap) \
@@ -860,13 +671,6 @@ ahd_reg_print_t ahd_negoaddr_print;
860#endif 671#endif
861 672
862#if AIC_DEBUG_REGISTERS 673#if AIC_DEBUG_REGISTERS
863ahd_reg_print_t ahd_dgrpcrci_print;
864#else
865#define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \
866 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap)
867#endif
868
869#if AIC_DEBUG_REGISTERS
870ahd_reg_print_t ahd_negperiod_print; 674ahd_reg_print_t ahd_negperiod_print;
871#else 675#else
872#define ahd_negperiod_print(regvalue, cur_col, wrap) \ 676#define ahd_negperiod_print(regvalue, cur_col, wrap) \
@@ -874,13 +678,6 @@ ahd_reg_print_t ahd_negperiod_print;
874#endif 678#endif
875 679
876#if AIC_DEBUG_REGISTERS 680#if AIC_DEBUG_REGISTERS
877ahd_reg_print_t ahd_packcrci_print;
878#else
879#define ahd_packcrci_print(regvalue, cur_col, wrap) \
880 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap)
881#endif
882
883#if AIC_DEBUG_REGISTERS
884ahd_reg_print_t ahd_negoffset_print; 681ahd_reg_print_t ahd_negoffset_print;
885#else 682#else
886#define ahd_negoffset_print(regvalue, cur_col, wrap) \ 683#define ahd_negoffset_print(regvalue, cur_col, wrap) \
@@ -930,13 +727,6 @@ ahd_reg_print_t ahd_iownid_print;
930#endif 727#endif
931 728
932#if AIC_DEBUG_REGISTERS 729#if AIC_DEBUG_REGISTERS
933ahd_reg_print_t ahd_pll960ctl0_print;
934#else
935#define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \
936 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahd_reg_print_t ahd_shcnt_print; 730ahd_reg_print_t ahd_shcnt_print;
941#else 731#else
942#define ahd_shcnt_print(regvalue, cur_col, wrap) \ 732#define ahd_shcnt_print(regvalue, cur_col, wrap) \
@@ -951,27 +741,6 @@ ahd_reg_print_t ahd_townid_print;
951#endif 741#endif
952 742
953#if AIC_DEBUG_REGISTERS 743#if AIC_DEBUG_REGISTERS
954ahd_reg_print_t ahd_pll960ctl1_print;
955#else
956#define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \
957 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap)
958#endif
959
960#if AIC_DEBUG_REGISTERS
961ahd_reg_print_t ahd_pll960cnt0_print;
962#else
963#define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \
964 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap)
965#endif
966
967#if AIC_DEBUG_REGISTERS
968ahd_reg_print_t ahd_xsig_print;
969#else
970#define ahd_xsig_print(regvalue, cur_col, wrap) \
971 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap)
972#endif
973
974#if AIC_DEBUG_REGISTERS
975ahd_reg_print_t ahd_seloid_print; 744ahd_reg_print_t ahd_seloid_print;
976#else 745#else
977#define ahd_seloid_print(regvalue, cur_col, wrap) \ 746#define ahd_seloid_print(regvalue, cur_col, wrap) \
@@ -979,41 +748,6 @@ ahd_reg_print_t ahd_seloid_print;
979#endif 748#endif
980 749
981#if AIC_DEBUG_REGISTERS 750#if AIC_DEBUG_REGISTERS
982ahd_reg_print_t ahd_pll400ctl0_print;
983#else
984#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
985 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
986#endif
987
988#if AIC_DEBUG_REGISTERS
989ahd_reg_print_t ahd_fairness_print;
990#else
991#define ahd_fairness_print(regvalue, cur_col, wrap) \
992 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
993#endif
994
995#if AIC_DEBUG_REGISTERS
996ahd_reg_print_t ahd_pll400ctl1_print;
997#else
998#define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \
999 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap)
1000#endif
1001
1002#if AIC_DEBUG_REGISTERS
1003ahd_reg_print_t ahd_unfairness_print;
1004#else
1005#define ahd_unfairness_print(regvalue, cur_col, wrap) \
1006 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahd_reg_print_t ahd_pll400cnt0_print;
1011#else
1012#define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \
1013 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap)
1014#endif
1015
1016#if AIC_DEBUG_REGISTERS
1017ahd_reg_print_t ahd_haddr_print; 751ahd_reg_print_t ahd_haddr_print;
1018#else 752#else
1019#define ahd_haddr_print(regvalue, cur_col, wrap) \ 753#define ahd_haddr_print(regvalue, cur_col, wrap) \
@@ -1021,27 +755,6 @@ ahd_reg_print_t ahd_haddr_print;
1021#endif 755#endif
1022 756
1023#if AIC_DEBUG_REGISTERS 757#if AIC_DEBUG_REGISTERS
1024ahd_reg_print_t ahd_plldelay_print;
1025#else
1026#define ahd_plldelay_print(regvalue, cur_col, wrap) \
1027 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap)
1028#endif
1029
1030#if AIC_DEBUG_REGISTERS
1031ahd_reg_print_t ahd_hodmaadr_print;
1032#else
1033#define ahd_hodmaadr_print(regvalue, cur_col, wrap) \
1034 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahd_reg_print_t ahd_hodmacnt_print;
1039#else
1040#define ahd_hodmacnt_print(regvalue, cur_col, wrap) \
1041 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahd_reg_print_t ahd_hcnt_print; 758ahd_reg_print_t ahd_hcnt_print;
1046#else 759#else
1047#define ahd_hcnt_print(regvalue, cur_col, wrap) \ 760#define ahd_hcnt_print(regvalue, cur_col, wrap) \
@@ -1049,10 +762,10 @@ ahd_reg_print_t ahd_hcnt_print;
1049#endif 762#endif
1050 763
1051#if AIC_DEBUG_REGISTERS 764#if AIC_DEBUG_REGISTERS
1052ahd_reg_print_t ahd_hodmaen_print; 765ahd_reg_print_t ahd_sghaddr_print;
1053#else 766#else
1054#define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 767#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
1055 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 768 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
1056#endif 769#endif
1057 770
1058#if AIC_DEBUG_REGISTERS 771#if AIC_DEBUG_REGISTERS
@@ -1063,10 +776,10 @@ ahd_reg_print_t ahd_scbhaddr_print;
1063#endif 776#endif
1064 777
1065#if AIC_DEBUG_REGISTERS 778#if AIC_DEBUG_REGISTERS
1066ahd_reg_print_t ahd_sghaddr_print; 779ahd_reg_print_t ahd_sghcnt_print;
1067#else 780#else
1068#define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 781#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1069 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 782 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1070#endif 783#endif
1071 784
1072#if AIC_DEBUG_REGISTERS 785#if AIC_DEBUG_REGISTERS
@@ -1077,13 +790,6 @@ ahd_reg_print_t ahd_scbhcnt_print;
1077#endif 790#endif
1078 791
1079#if AIC_DEBUG_REGISTERS 792#if AIC_DEBUG_REGISTERS
1080ahd_reg_print_t ahd_sghcnt_print;
1081#else
1082#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1083 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1084#endif
1085
1086#if AIC_DEBUG_REGISTERS
1087ahd_reg_print_t ahd_dff_thrsh_print; 793ahd_reg_print_t ahd_dff_thrsh_print;
1088#else 794#else
1089#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 795#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
@@ -1091,132 +797,6 @@ ahd_reg_print_t ahd_dff_thrsh_print;
1091#endif 797#endif
1092 798
1093#if AIC_DEBUG_REGISTERS 799#if AIC_DEBUG_REGISTERS
1094ahd_reg_print_t ahd_romaddr_print;
1095#else
1096#define ahd_romaddr_print(regvalue, cur_col, wrap) \
1097 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap)
1098#endif
1099
1100#if AIC_DEBUG_REGISTERS
1101ahd_reg_print_t ahd_romcntrl_print;
1102#else
1103#define ahd_romcntrl_print(regvalue, cur_col, wrap) \
1104 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap)
1105#endif
1106
1107#if AIC_DEBUG_REGISTERS
1108ahd_reg_print_t ahd_romdata_print;
1109#else
1110#define ahd_romdata_print(regvalue, cur_col, wrap) \
1111 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap)
1112#endif
1113
1114#if AIC_DEBUG_REGISTERS
1115ahd_reg_print_t ahd_cmcrxmsg0_print;
1116#else
1117#define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \
1118 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap)
1119#endif
1120
1121#if AIC_DEBUG_REGISTERS
1122ahd_reg_print_t ahd_roenable_print;
1123#else
1124#define ahd_roenable_print(regvalue, cur_col, wrap) \
1125 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
1126#endif
1127
1128#if AIC_DEBUG_REGISTERS
1129ahd_reg_print_t ahd_ovlyrxmsg0_print;
1130#else
1131#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
1132 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap)
1133#endif
1134
1135#if AIC_DEBUG_REGISTERS
1136ahd_reg_print_t ahd_dchrxmsg0_print;
1137#else
1138#define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \
1139 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap)
1140#endif
1141
1142#if AIC_DEBUG_REGISTERS
1143ahd_reg_print_t ahd_ovlyrxmsg1_print;
1144#else
1145#define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \
1146 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap)
1147#endif
1148
1149#if AIC_DEBUG_REGISTERS
1150ahd_reg_print_t ahd_nsenable_print;
1151#else
1152#define ahd_nsenable_print(regvalue, cur_col, wrap) \
1153 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
1154#endif
1155
1156#if AIC_DEBUG_REGISTERS
1157ahd_reg_print_t ahd_cmcrxmsg1_print;
1158#else
1159#define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \
1160 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap)
1161#endif
1162
1163#if AIC_DEBUG_REGISTERS
1164ahd_reg_print_t ahd_dchrxmsg1_print;
1165#else
1166#define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \
1167 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap)
1168#endif
1169
1170#if AIC_DEBUG_REGISTERS
1171ahd_reg_print_t ahd_dchrxmsg2_print;
1172#else
1173#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
1174 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap)
1175#endif
1176
1177#if AIC_DEBUG_REGISTERS
1178ahd_reg_print_t ahd_cmcrxmsg2_print;
1179#else
1180#define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \
1181 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap)
1182#endif
1183
1184#if AIC_DEBUG_REGISTERS
1185ahd_reg_print_t ahd_ost_print;
1186#else
1187#define ahd_ost_print(regvalue, cur_col, wrap) \
1188 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap)
1189#endif
1190
1191#if AIC_DEBUG_REGISTERS
1192ahd_reg_print_t ahd_ovlyrxmsg2_print;
1193#else
1194#define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \
1195 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap)
1196#endif
1197
1198#if AIC_DEBUG_REGISTERS
1199ahd_reg_print_t ahd_dchrxmsg3_print;
1200#else
1201#define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \
1202 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap)
1203#endif
1204
1205#if AIC_DEBUG_REGISTERS
1206ahd_reg_print_t ahd_ovlyrxmsg3_print;
1207#else
1208#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
1209 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
1210#endif
1211
1212#if AIC_DEBUG_REGISTERS
1213ahd_reg_print_t ahd_cmcrxmsg3_print;
1214#else
1215#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
1216 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap)
1217#endif
1218
1219#if AIC_DEBUG_REGISTERS
1220ahd_reg_print_t ahd_pcixctl_print; 800ahd_reg_print_t ahd_pcixctl_print;
1221#else 801#else
1222#define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 802#define ahd_pcixctl_print(regvalue, cur_col, wrap) \
@@ -1224,34 +804,6 @@ ahd_reg_print_t ahd_pcixctl_print;
1224#endif 804#endif
1225 805
1226#if AIC_DEBUG_REGISTERS 806#if AIC_DEBUG_REGISTERS
1227ahd_reg_print_t ahd_ovlyseqbcnt_print;
1228#else
1229#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
1230 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap)
1231#endif
1232
1233#if AIC_DEBUG_REGISTERS
1234ahd_reg_print_t ahd_dchseqbcnt_print;
1235#else
1236#define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \
1237 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap)
1238#endif
1239
1240#if AIC_DEBUG_REGISTERS
1241ahd_reg_print_t ahd_cmcseqbcnt_print;
1242#else
1243#define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \
1244 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap)
1245#endif
1246
1247#if AIC_DEBUG_REGISTERS
1248ahd_reg_print_t ahd_cmcspltstat0_print;
1249#else
1250#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
1251 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1252#endif
1253
1254#if AIC_DEBUG_REGISTERS
1255ahd_reg_print_t ahd_dchspltstat0_print; 807ahd_reg_print_t ahd_dchspltstat0_print;
1256#else 808#else
1257#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 809#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
@@ -1259,27 +811,6 @@ ahd_reg_print_t ahd_dchspltstat0_print;
1259#endif 811#endif
1260 812
1261#if AIC_DEBUG_REGISTERS 813#if AIC_DEBUG_REGISTERS
1262ahd_reg_print_t ahd_ovlyspltstat0_print;
1263#else
1264#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
1265 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1266#endif
1267
1268#if AIC_DEBUG_REGISTERS
1269ahd_reg_print_t ahd_cmcspltstat1_print;
1270#else
1271#define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \
1272 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1273#endif
1274
1275#if AIC_DEBUG_REGISTERS
1276ahd_reg_print_t ahd_ovlyspltstat1_print;
1277#else
1278#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
1279 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1280#endif
1281
1282#if AIC_DEBUG_REGISTERS
1283ahd_reg_print_t ahd_dchspltstat1_print; 814ahd_reg_print_t ahd_dchspltstat1_print;
1284#else 815#else
1285#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 816#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
@@ -1287,90 +818,6 @@ ahd_reg_print_t ahd_dchspltstat1_print;
1287#endif 818#endif
1288 819
1289#if AIC_DEBUG_REGISTERS 820#if AIC_DEBUG_REGISTERS
1290ahd_reg_print_t ahd_sgrxmsg0_print;
1291#else
1292#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
1293 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap)
1294#endif
1295
1296#if AIC_DEBUG_REGISTERS
1297ahd_reg_print_t ahd_slvspltoutadr0_print;
1298#else
1299#define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \
1300 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap)
1301#endif
1302
1303#if AIC_DEBUG_REGISTERS
1304ahd_reg_print_t ahd_sgrxmsg1_print;
1305#else
1306#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
1307 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap)
1308#endif
1309
1310#if AIC_DEBUG_REGISTERS
1311ahd_reg_print_t ahd_slvspltoutadr1_print;
1312#else
1313#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
1314 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
1315#endif
1316
1317#if AIC_DEBUG_REGISTERS
1318ahd_reg_print_t ahd_sgrxmsg2_print;
1319#else
1320#define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \
1321 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap)
1322#endif
1323
1324#if AIC_DEBUG_REGISTERS
1325ahd_reg_print_t ahd_slvspltoutadr2_print;
1326#else
1327#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
1328 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
1329#endif
1330
1331#if AIC_DEBUG_REGISTERS
1332ahd_reg_print_t ahd_sgrxmsg3_print;
1333#else
1334#define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \
1335 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap)
1336#endif
1337
1338#if AIC_DEBUG_REGISTERS
1339ahd_reg_print_t ahd_slvspltoutadr3_print;
1340#else
1341#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
1342 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap)
1343#endif
1344
1345#if AIC_DEBUG_REGISTERS
1346ahd_reg_print_t ahd_sgseqbcnt_print;
1347#else
1348#define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \
1349 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap)
1350#endif
1351
1352#if AIC_DEBUG_REGISTERS
1353ahd_reg_print_t ahd_slvspltoutattr0_print;
1354#else
1355#define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \
1356 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap)
1357#endif
1358
1359#if AIC_DEBUG_REGISTERS
1360ahd_reg_print_t ahd_slvspltoutattr1_print;
1361#else
1362#define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \
1363 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap)
1364#endif
1365
1366#if AIC_DEBUG_REGISTERS
1367ahd_reg_print_t ahd_slvspltoutattr2_print;
1368#else
1369#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
1370 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
1371#endif
1372
1373#if AIC_DEBUG_REGISTERS
1374ahd_reg_print_t ahd_sgspltstat0_print; 821ahd_reg_print_t ahd_sgspltstat0_print;
1375#else 822#else
1376#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 823#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
@@ -1385,13 +832,6 @@ ahd_reg_print_t ahd_sgspltstat1_print;
1385#endif 832#endif
1386 833
1387#if AIC_DEBUG_REGISTERS 834#if AIC_DEBUG_REGISTERS
1388ahd_reg_print_t ahd_sfunct_print;
1389#else
1390#define ahd_sfunct_print(regvalue, cur_col, wrap) \
1391 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
1392#endif
1393
1394#if AIC_DEBUG_REGISTERS
1395ahd_reg_print_t ahd_df0pcistat_print; 835ahd_reg_print_t ahd_df0pcistat_print;
1396#else 836#else
1397#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 837#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
@@ -1406,41 +846,6 @@ ahd_reg_print_t ahd_reg0_print;
1406#endif 846#endif
1407 847
1408#if AIC_DEBUG_REGISTERS 848#if AIC_DEBUG_REGISTERS
1409ahd_reg_print_t ahd_df1pcistat_print;
1410#else
1411#define ahd_df1pcistat_print(regvalue, cur_col, wrap) \
1412 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap)
1413#endif
1414
1415#if AIC_DEBUG_REGISTERS
1416ahd_reg_print_t ahd_sgpcistat_print;
1417#else
1418#define ahd_sgpcistat_print(regvalue, cur_col, wrap) \
1419 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap)
1420#endif
1421
1422#if AIC_DEBUG_REGISTERS
1423ahd_reg_print_t ahd_reg1_print;
1424#else
1425#define ahd_reg1_print(regvalue, cur_col, wrap) \
1426 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap)
1427#endif
1428
1429#if AIC_DEBUG_REGISTERS
1430ahd_reg_print_t ahd_cmcpcistat_print;
1431#else
1432#define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \
1433 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap)
1434#endif
1435
1436#if AIC_DEBUG_REGISTERS
1437ahd_reg_print_t ahd_ovlypcistat_print;
1438#else
1439#define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \
1440 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap)
1441#endif
1442
1443#if AIC_DEBUG_REGISTERS
1444ahd_reg_print_t ahd_reg_isr_print; 849ahd_reg_print_t ahd_reg_isr_print;
1445#else 850#else
1446#define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 851#define ahd_reg_isr_print(regvalue, cur_col, wrap) \
@@ -1455,13 +860,6 @@ ahd_reg_print_t ahd_sg_state_print;
1455#endif 860#endif
1456 861
1457#if AIC_DEBUG_REGISTERS 862#if AIC_DEBUG_REGISTERS
1458ahd_reg_print_t ahd_msipcistat_print;
1459#else
1460#define ahd_msipcistat_print(regvalue, cur_col, wrap) \
1461 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap)
1462#endif
1463
1464#if AIC_DEBUG_REGISTERS
1465ahd_reg_print_t ahd_targpcistat_print; 863ahd_reg_print_t ahd_targpcistat_print;
1466#else 864#else
1467#define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 865#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
@@ -1469,13 +867,6 @@ ahd_reg_print_t ahd_targpcistat_print;
1469#endif 867#endif
1470 868
1471#if AIC_DEBUG_REGISTERS 869#if AIC_DEBUG_REGISTERS
1472ahd_reg_print_t ahd_data_count_odd_print;
1473#else
1474#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
1475 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
1476#endif
1477
1478#if AIC_DEBUG_REGISTERS
1479ahd_reg_print_t ahd_scbptr_print; 870ahd_reg_print_t ahd_scbptr_print;
1480#else 871#else
1481#define ahd_scbptr_print(regvalue, cur_col, wrap) \ 872#define ahd_scbptr_print(regvalue, cur_col, wrap) \
@@ -1483,13 +874,6 @@ ahd_reg_print_t ahd_scbptr_print;
1483#endif 874#endif
1484 875
1485#if AIC_DEBUG_REGISTERS 876#if AIC_DEBUG_REGISTERS
1486ahd_reg_print_t ahd_ccscbacnt_print;
1487#else
1488#define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \
1489 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap)
1490#endif
1491
1492#if AIC_DEBUG_REGISTERS
1493ahd_reg_print_t ahd_scbautoptr_print; 877ahd_reg_print_t ahd_scbautoptr_print;
1494#else 878#else
1495#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 879#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
@@ -1504,13 +888,6 @@ ahd_reg_print_t ahd_ccsgaddr_print;
1504#endif 888#endif
1505 889
1506#if AIC_DEBUG_REGISTERS 890#if AIC_DEBUG_REGISTERS
1507ahd_reg_print_t ahd_ccscbadr_bk_print;
1508#else
1509#define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \
1510 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap)
1511#endif
1512
1513#if AIC_DEBUG_REGISTERS
1514ahd_reg_print_t ahd_ccscbaddr_print; 891ahd_reg_print_t ahd_ccscbaddr_print;
1515#else 892#else
1516#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 893#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
@@ -1518,13 +895,6 @@ ahd_reg_print_t ahd_ccscbaddr_print;
1518#endif 895#endif
1519 896
1520#if AIC_DEBUG_REGISTERS 897#if AIC_DEBUG_REGISTERS
1521ahd_reg_print_t ahd_cmc_rambist_print;
1522#else
1523#define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \
1524 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap)
1525#endif
1526
1527#if AIC_DEBUG_REGISTERS
1528ahd_reg_print_t ahd_ccscbctl_print; 898ahd_reg_print_t ahd_ccscbctl_print;
1529#else 899#else
1530#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 900#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
@@ -1546,13 +916,6 @@ ahd_reg_print_t ahd_ccsgram_print;
1546#endif 916#endif
1547 917
1548#if AIC_DEBUG_REGISTERS 918#if AIC_DEBUG_REGISTERS
1549ahd_reg_print_t ahd_flexadr_print;
1550#else
1551#define ahd_flexadr_print(regvalue, cur_col, wrap) \
1552 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap)
1553#endif
1554
1555#if AIC_DEBUG_REGISTERS
1556ahd_reg_print_t ahd_ccscbram_print; 919ahd_reg_print_t ahd_ccscbram_print;
1557#else 920#else
1558#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 921#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
@@ -1560,27 +923,6 @@ ahd_reg_print_t ahd_ccscbram_print;
1560#endif 923#endif
1561 924
1562#if AIC_DEBUG_REGISTERS 925#if AIC_DEBUG_REGISTERS
1563ahd_reg_print_t ahd_flexcnt_print;
1564#else
1565#define ahd_flexcnt_print(regvalue, cur_col, wrap) \
1566 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap)
1567#endif
1568
1569#if AIC_DEBUG_REGISTERS
1570ahd_reg_print_t ahd_flexdmastat_print;
1571#else
1572#define ahd_flexdmastat_print(regvalue, cur_col, wrap) \
1573 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap)
1574#endif
1575
1576#if AIC_DEBUG_REGISTERS
1577ahd_reg_print_t ahd_flexdata_print;
1578#else
1579#define ahd_flexdata_print(regvalue, cur_col, wrap) \
1580 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap)
1581#endif
1582
1583#if AIC_DEBUG_REGISTERS
1584ahd_reg_print_t ahd_brddat_print; 926ahd_reg_print_t ahd_brddat_print;
1585#else 927#else
1586#define ahd_brddat_print(regvalue, cur_col, wrap) \ 928#define ahd_brddat_print(regvalue, cur_col, wrap) \
@@ -1623,27 +965,6 @@ ahd_reg_print_t ahd_seestat_print;
1623#endif 965#endif
1624 966
1625#if AIC_DEBUG_REGISTERS 967#if AIC_DEBUG_REGISTERS
1626ahd_reg_print_t ahd_scbcnt_print;
1627#else
1628#define ahd_scbcnt_print(regvalue, cur_col, wrap) \
1629 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap)
1630#endif
1631
1632#if AIC_DEBUG_REGISTERS
1633ahd_reg_print_t ahd_dfwaddr_print;
1634#else
1635#define ahd_dfwaddr_print(regvalue, cur_col, wrap) \
1636 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap)
1637#endif
1638
1639#if AIC_DEBUG_REGISTERS
1640ahd_reg_print_t ahd_dspfltrctl_print;
1641#else
1642#define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \
1643 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap)
1644#endif
1645
1646#if AIC_DEBUG_REGISTERS
1647ahd_reg_print_t ahd_dspdatactl_print; 968ahd_reg_print_t ahd_dspdatactl_print;
1648#else 969#else
1649#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 970#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
@@ -1651,27 +972,6 @@ ahd_reg_print_t ahd_dspdatactl_print;
1651#endif 972#endif
1652 973
1653#if AIC_DEBUG_REGISTERS 974#if AIC_DEBUG_REGISTERS
1654ahd_reg_print_t ahd_dfraddr_print;
1655#else
1656#define ahd_dfraddr_print(regvalue, cur_col, wrap) \
1657 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap)
1658#endif
1659
1660#if AIC_DEBUG_REGISTERS
1661ahd_reg_print_t ahd_dspreqctl_print;
1662#else
1663#define ahd_dspreqctl_print(regvalue, cur_col, wrap) \
1664 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap)
1665#endif
1666
1667#if AIC_DEBUG_REGISTERS
1668ahd_reg_print_t ahd_dspackctl_print;
1669#else
1670#define ahd_dspackctl_print(regvalue, cur_col, wrap) \
1671 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap)
1672#endif
1673
1674#if AIC_DEBUG_REGISTERS
1675ahd_reg_print_t ahd_dfdat_print; 975ahd_reg_print_t ahd_dfdat_print;
1676#else 976#else
1677#define ahd_dfdat_print(regvalue, cur_col, wrap) \ 977#define ahd_dfdat_print(regvalue, cur_col, wrap) \
@@ -1693,76 +993,6 @@ ahd_reg_print_t ahd_wrtbiasctl_print;
1693#endif 993#endif
1694 994
1695#if AIC_DEBUG_REGISTERS 995#if AIC_DEBUG_REGISTERS
1696ahd_reg_print_t ahd_rcvrbiosctl_print;
1697#else
1698#define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \
1699 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap)
1700#endif
1701
1702#if AIC_DEBUG_REGISTERS
1703ahd_reg_print_t ahd_wrtbiascalc_print;
1704#else
1705#define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \
1706 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap)
1707#endif
1708
1709#if AIC_DEBUG_REGISTERS
1710ahd_reg_print_t ahd_rcvrbiascalc_print;
1711#else
1712#define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \
1713 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap)
1714#endif
1715
1716#if AIC_DEBUG_REGISTERS
1717ahd_reg_print_t ahd_dfptrs_print;
1718#else
1719#define ahd_dfptrs_print(regvalue, cur_col, wrap) \
1720 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap)
1721#endif
1722
1723#if AIC_DEBUG_REGISTERS
1724ahd_reg_print_t ahd_skewcalc_print;
1725#else
1726#define ahd_skewcalc_print(regvalue, cur_col, wrap) \
1727 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap)
1728#endif
1729
1730#if AIC_DEBUG_REGISTERS
1731ahd_reg_print_t ahd_dfbkptr_print;
1732#else
1733#define ahd_dfbkptr_print(regvalue, cur_col, wrap) \
1734 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap)
1735#endif
1736
1737#if AIC_DEBUG_REGISTERS
1738ahd_reg_print_t ahd_dfdbctl_print;
1739#else
1740#define ahd_dfdbctl_print(regvalue, cur_col, wrap) \
1741 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap)
1742#endif
1743
1744#if AIC_DEBUG_REGISTERS
1745ahd_reg_print_t ahd_dfscnt_print;
1746#else
1747#define ahd_dfscnt_print(regvalue, cur_col, wrap) \
1748 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap)
1749#endif
1750
1751#if AIC_DEBUG_REGISTERS
1752ahd_reg_print_t ahd_dfbcnt_print;
1753#else
1754#define ahd_dfbcnt_print(regvalue, cur_col, wrap) \
1755 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap)
1756#endif
1757
1758#if AIC_DEBUG_REGISTERS
1759ahd_reg_print_t ahd_ovlyaddr_print;
1760#else
1761#define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \
1762 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap)
1763#endif
1764
1765#if AIC_DEBUG_REGISTERS
1766ahd_reg_print_t ahd_seqctl0_print; 996ahd_reg_print_t ahd_seqctl0_print;
1767#else 997#else
1768#define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 998#define ahd_seqctl0_print(regvalue, cur_col, wrap) \
@@ -1770,13 +1000,6 @@ ahd_reg_print_t ahd_seqctl0_print;
1770#endif 1000#endif
1771 1001
1772#if AIC_DEBUG_REGISTERS 1002#if AIC_DEBUG_REGISTERS
1773ahd_reg_print_t ahd_seqctl1_print;
1774#else
1775#define ahd_seqctl1_print(regvalue, cur_col, wrap) \
1776 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap)
1777#endif
1778
1779#if AIC_DEBUG_REGISTERS
1780ahd_reg_print_t ahd_flags_print; 1003ahd_reg_print_t ahd_flags_print;
1781#else 1004#else
1782#define ahd_flags_print(regvalue, cur_col, wrap) \ 1005#define ahd_flags_print(regvalue, cur_col, wrap) \
@@ -1826,20 +1049,6 @@ ahd_reg_print_t ahd_dindex_print;
1826#endif 1049#endif
1827 1050
1828#if AIC_DEBUG_REGISTERS 1051#if AIC_DEBUG_REGISTERS
1829ahd_reg_print_t ahd_brkaddr0_print;
1830#else
1831#define ahd_brkaddr0_print(regvalue, cur_col, wrap) \
1832 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap)
1833#endif
1834
1835#if AIC_DEBUG_REGISTERS
1836ahd_reg_print_t ahd_brkaddr1_print;
1837#else
1838#define ahd_brkaddr1_print(regvalue, cur_col, wrap) \
1839 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap)
1840#endif
1841
1842#if AIC_DEBUG_REGISTERS
1843ahd_reg_print_t ahd_allones_print; 1052ahd_reg_print_t ahd_allones_print;
1844#else 1053#else
1845#define ahd_allones_print(regvalue, cur_col, wrap) \ 1054#define ahd_allones_print(regvalue, cur_col, wrap) \
@@ -1875,13 +1084,6 @@ ahd_reg_print_t ahd_dindir_print;
1875#endif 1084#endif
1876 1085
1877#if AIC_DEBUG_REGISTERS 1086#if AIC_DEBUG_REGISTERS
1878ahd_reg_print_t ahd_function1_print;
1879#else
1880#define ahd_function1_print(regvalue, cur_col, wrap) \
1881 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap)
1882#endif
1883
1884#if AIC_DEBUG_REGISTERS
1885ahd_reg_print_t ahd_stack_print; 1087ahd_reg_print_t ahd_stack_print;
1886#else 1088#else
1887#define ahd_stack_print(regvalue, cur_col, wrap) \ 1089#define ahd_stack_print(regvalue, cur_col, wrap) \
@@ -1903,13 +1105,6 @@ ahd_reg_print_t ahd_curaddr_print;
1903#endif 1105#endif
1904 1106
1905#if AIC_DEBUG_REGISTERS 1107#if AIC_DEBUG_REGISTERS
1906ahd_reg_print_t ahd_lastaddr_print;
1907#else
1908#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
1909 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
1910#endif
1911
1912#if AIC_DEBUG_REGISTERS
1913ahd_reg_print_t ahd_intvec2_addr_print; 1108ahd_reg_print_t ahd_intvec2_addr_print;
1914#else 1109#else
1915#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1110#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
@@ -1931,24 +1126,17 @@ ahd_reg_print_t ahd_accum_save_print;
1931#endif 1126#endif
1932 1127
1933#if AIC_DEBUG_REGISTERS 1128#if AIC_DEBUG_REGISTERS
1934ahd_reg_print_t ahd_waiting_scb_tails_print; 1129ahd_reg_print_t ahd_sram_base_print;
1935#else
1936#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1937 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1938#endif
1939
1940#if AIC_DEBUG_REGISTERS
1941ahd_reg_print_t ahd_ahd_pci_config_base_print;
1942#else 1130#else
1943#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1131#define ahd_sram_base_print(regvalue, cur_col, wrap) \
1944 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1132 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1945#endif 1133#endif
1946 1134
1947#if AIC_DEBUG_REGISTERS 1135#if AIC_DEBUG_REGISTERS
1948ahd_reg_print_t ahd_sram_base_print; 1136ahd_reg_print_t ahd_waiting_scb_tails_print;
1949#else 1137#else
1950#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1138#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1951 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1139 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1952#endif 1140#endif
1953 1141
1954#if AIC_DEBUG_REGISTERS 1142#if AIC_DEBUG_REGISTERS
@@ -2218,17 +1406,17 @@ ahd_reg_print_t ahd_mk_message_scsiid_print;
2218#endif 1406#endif
2219 1407
2220#if AIC_DEBUG_REGISTERS 1408#if AIC_DEBUG_REGISTERS
2221ahd_reg_print_t ahd_scb_base_print; 1409ahd_reg_print_t ahd_scb_residual_datacnt_print;
2222#else 1410#else
2223#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 1411#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
2224 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 1412 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
2225#endif 1413#endif
2226 1414
2227#if AIC_DEBUG_REGISTERS 1415#if AIC_DEBUG_REGISTERS
2228ahd_reg_print_t ahd_scb_residual_datacnt_print; 1416ahd_reg_print_t ahd_scb_base_print;
2229#else 1417#else
2230#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 1418#define ahd_scb_base_print(regvalue, cur_col, wrap) \
2231 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 1419 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
2232#endif 1420#endif
2233 1421
2234#if AIC_DEBUG_REGISTERS 1422#if AIC_DEBUG_REGISTERS
@@ -2246,27 +1434,6 @@ ahd_reg_print_t ahd_scb_scsi_status_print;
2246#endif 1434#endif
2247 1435
2248#if AIC_DEBUG_REGISTERS 1436#if AIC_DEBUG_REGISTERS
2249ahd_reg_print_t ahd_scb_target_phases_print;
2250#else
2251#define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \
2252 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap)
2253#endif
2254
2255#if AIC_DEBUG_REGISTERS
2256ahd_reg_print_t ahd_scb_target_data_dir_print;
2257#else
2258#define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \
2259 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap)
2260#endif
2261
2262#if AIC_DEBUG_REGISTERS
2263ahd_reg_print_t ahd_scb_target_itag_print;
2264#else
2265#define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \
2266 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap)
2267#endif
2268
2269#if AIC_DEBUG_REGISTERS
2270ahd_reg_print_t ahd_scb_sense_busaddr_print; 1437ahd_reg_print_t ahd_scb_sense_busaddr_print;
2271#else 1438#else
2272#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 1439#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
@@ -2365,13 +1532,6 @@ ahd_reg_print_t ahd_scb_next2_print;
2365#endif 1532#endif
2366 1533
2367#if AIC_DEBUG_REGISTERS 1534#if AIC_DEBUG_REGISTERS
2368ahd_reg_print_t ahd_scb_spare_print;
2369#else
2370#define ahd_scb_spare_print(regvalue, cur_col, wrap) \
2371 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap)
2372#endif
2373
2374#if AIC_DEBUG_REGISTERS
2375ahd_reg_print_t ahd_scb_disconnected_lists_print; 1535ahd_reg_print_t ahd_scb_disconnected_lists_print;
2376#else 1536#else
2377#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 1537#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
@@ -2557,10 +1717,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2557 1717
2558#define SG_CACHE_PRE 0x1b 1718#define SG_CACHE_PRE 0x1b
2559 1719
2560#define LQIN 0x20
2561
2562#define TYPEPTR 0x20 1720#define TYPEPTR 0x20
2563 1721
1722#define LQIN 0x20
1723
2564#define TAGPTR 0x21 1724#define TAGPTR 0x21
2565 1725
2566#define LUNPTR 0x22 1726#define LUNPTR 0x22
@@ -2620,14 +1780,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2620#define SINGLECMD 0x02 1780#define SINGLECMD 0x02
2621#define ABORTPENDING 0x01 1781#define ABORTPENDING 0x01
2622 1782
2623#define SCSBIST0 0x39
2624#define GSBISTERR 0x40
2625#define GSBISTDONE 0x20
2626#define GSBISTRUN 0x10
2627#define OSBISTERR 0x04
2628#define OSBISTDONE 0x02
2629#define OSBISTRUN 0x01
2630
2631#define LQCTL2 0x39 1783#define LQCTL2 0x39
2632#define LQIRETRY 0x80 1784#define LQIRETRY 0x80
2633#define LQICONTINUE 0x40 1785#define LQICONTINUE 0x40
@@ -2638,10 +1790,13 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2638#define LQOTOIDLE 0x02 1790#define LQOTOIDLE 0x02
2639#define LQOPAUSE 0x01 1791#define LQOPAUSE 0x01
2640 1792
2641#define SCSBIST1 0x3a 1793#define SCSBIST0 0x39
2642#define NTBISTERR 0x04 1794#define GSBISTERR 0x40
2643#define NTBISTDONE 0x02 1795#define GSBISTDONE 0x20
2644#define NTBISTRUN 0x01 1796#define GSBISTRUN 0x10
1797#define OSBISTERR 0x04
1798#define OSBISTDONE 0x02
1799#define OSBISTRUN 0x01
2645 1800
2646#define SCSISEQ0 0x3a 1801#define SCSISEQ0 0x3a
2647#define TEMODEO 0x80 1802#define TEMODEO 0x80
@@ -2650,8 +1805,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2650#define FORCEBUSFREE 0x10 1805#define FORCEBUSFREE 0x10
2651#define SCSIRSTO 0x01 1806#define SCSIRSTO 0x01
2652 1807
1808#define SCSBIST1 0x3a
1809#define NTBISTERR 0x04
1810#define NTBISTDONE 0x02
1811#define NTBISTRUN 0x01
1812
2653#define SCSISEQ1 0x3b 1813#define SCSISEQ1 0x3b
2654 1814
1815#define BUSINITID 0x3c
1816
2655#define SXFRCTL0 0x3c 1817#define SXFRCTL0 0x3c
2656#define DFON 0x80 1818#define DFON 0x80
2657#define DFPEXP 0x40 1819#define DFPEXP 0x40
@@ -2660,8 +1822,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2660 1822
2661#define DLCOUNT 0x3c 1823#define DLCOUNT 0x3c
2662 1824
2663#define BUSINITID 0x3c
2664
2665#define SXFRCTL1 0x3d 1825#define SXFRCTL1 0x3d
2666#define BITBUCKET 0x80 1826#define BITBUCKET 0x80
2667#define ENSACHK 0x40 1827#define ENSACHK 0x40
@@ -2686,6 +1846,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2686#define CURRFIFO_1 0x01 1846#define CURRFIFO_1 0x01
2687#define CURRFIFO_0 0x00 1847#define CURRFIFO_0 0x00
2688 1848
1849#define MULTARGID 0x40
1850
2689#define SCSISIGO 0x40 1851#define SCSISIGO 0x40
2690#define CDO 0x80 1852#define CDO 0x80
2691#define IOO 0x40 1853#define IOO 0x40
@@ -2696,8 +1858,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2696#define REQO 0x02 1858#define REQO 0x02
2697#define ACKO 0x01 1859#define ACKO 0x01
2698 1860
2699#define MULTARGID 0x40
2700
2701#define SCSISIGI 0x41 1861#define SCSISIGI 0x41
2702#define ATNI 0x10 1862#define ATNI 0x10
2703#define SELI 0x08 1863#define SELI 0x08
@@ -2744,15 +1904,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2744#define ENAB20 0x04 1904#define ENAB20 0x04
2745#define SELWIDE 0x02 1905#define SELWIDE 0x02
2746 1906
2747#define CLRSINT0 0x4b
2748#define CLRSELDO 0x40
2749#define CLRSELDI 0x20
2750#define CLRSELINGO 0x10
2751#define CLRIOERR 0x08
2752#define CLROVERRUN 0x04
2753#define CLRSPIORDY 0x02
2754#define CLRARBDO 0x01
2755
2756#define SSTAT0 0x4b 1907#define SSTAT0 0x4b
2757#define TARGET 0x80 1908#define TARGET 0x80
2758#define SELDO 0x40 1909#define SELDO 0x40
@@ -2772,14 +1923,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2772#define ENSPIORDY 0x02 1923#define ENSPIORDY 0x02
2773#define ENARBDO 0x01 1924#define ENARBDO 0x01
2774 1925
2775#define CLRSINT1 0x4c 1926#define CLRSINT0 0x4b
2776#define CLRSELTIMEO 0x80 1927#define CLRSELDO 0x40
2777#define CLRATNO 0x40 1928#define CLRSELDI 0x20
2778#define CLRSCSIRSTI 0x20 1929#define CLRSELINGO 0x10
2779#define CLRBUSFREE 0x08 1930#define CLRIOERR 0x08
2780#define CLRSCSIPERR 0x04 1931#define CLROVERRUN 0x04
2781#define CLRSTRB2FAST 0x02 1932#define CLRSPIORDY 0x02
2782#define CLRREQINIT 0x01 1933#define CLRARBDO 0x01
2783 1934
2784#define SSTAT1 0x4c 1935#define SSTAT1 0x4c
2785#define SELTO 0x80 1936#define SELTO 0x80
@@ -2791,6 +1942,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2791#define STRB2FAST 0x02 1942#define STRB2FAST 0x02
2792#define REQINIT 0x01 1943#define REQINIT 0x01
2793 1944
1945#define CLRSINT1 0x4c
1946#define CLRSELTIMEO 0x80
1947#define CLRATNO 0x40
1948#define CLRSCSIRSTI 0x20
1949#define CLRBUSFREE 0x08
1950#define CLRSCSIPERR 0x04
1951#define CLRSTRB2FAST 0x02
1952#define CLRREQINIT 0x01
1953
2794#define SSTAT2 0x4d 1954#define SSTAT2 0x4d
2795#define BUSFREETIME 0xc0 1955#define BUSFREETIME 0xc0
2796#define NONPACKREQ 0x20 1956#define NONPACKREQ 0x20
@@ -2838,14 +1998,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2838#define LQIATNLQ 0x02 1998#define LQIATNLQ 0x02
2839#define LQIATNCMD 0x01 1999#define LQIATNCMD 0x01
2840 2000
2841#define CLRLQIINT0 0x50
2842#define CLRLQIATNQAS 0x20
2843#define CLRLQICRCT1 0x10
2844#define CLRLQICRCT2 0x08
2845#define CLRLQIBADLQT 0x04
2846#define CLRLQIATNLQ 0x02
2847#define CLRLQIATNCMD 0x01
2848
2849#define LQIMODE0 0x50 2001#define LQIMODE0 0x50
2850#define ENLQIATNQASK 0x20 2002#define ENLQIATNQASK 0x20
2851#define ENLQICRCT1 0x10 2003#define ENLQICRCT1 0x10
@@ -2854,6 +2006,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2854#define ENLQIATNLQ 0x02 2006#define ENLQIATNLQ 0x02
2855#define ENLQIATNCMD 0x01 2007#define ENLQIATNCMD 0x01
2856 2008
2009#define CLRLQIINT0 0x50
2010#define CLRLQIATNQAS 0x20
2011#define CLRLQICRCT1 0x10
2012#define CLRLQICRCT2 0x08
2013#define CLRLQIBADLQT 0x04
2014#define CLRLQIATNLQ 0x02
2015#define CLRLQIATNCMD 0x01
2016
2857#define LQIMODE1 0x51 2017#define LQIMODE1 0x51
2858#define ENLQIPHASE_LQ 0x80 2018#define ENLQIPHASE_LQ 0x80
2859#define ENLQIPHASE_NLQ 0x40 2019#define ENLQIPHASE_NLQ 0x40
@@ -2976,6 +2136,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2976 2136
2977#define LQOSCSCTL 0x5a 2137#define LQOSCSCTL 0x5a
2978#define LQOH2A_VERSION 0x80 2138#define LQOH2A_VERSION 0x80
2139#define LQOBUSETDLY 0x40
2140#define LQONOHOLDLACK 0x02
2979#define LQONOCHKOVER 0x01 2141#define LQONOCHKOVER 0x01
2980 2142
2981#define NEXTSCB 0x5a 2143#define NEXTSCB 0x5a
@@ -2998,8 +2160,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
2998#define CFG4ICMD 0x02 2160#define CFG4ICMD 0x02
2999#define CFG4TCMD 0x01 2161#define CFG4TCMD 0x01
3000 2162
3001#define CURRSCB 0x5c
3002
3003#define SEQIMODE 0x5c 2163#define SEQIMODE 0x5c
3004#define ENCTXTDONE 0x40 2164#define ENCTXTDONE 0x40
3005#define ENSAVEPTRS 0x20 2165#define ENSAVEPTRS 0x20
@@ -3009,6 +2169,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3009#define ENCFG4ICMD 0x02 2169#define ENCFG4ICMD 0x02
3010#define ENCFG4TCMD 0x01 2170#define ENCFG4TCMD 0x01
3011 2171
2172#define CURRSCB 0x5c
2173
3012#define MDFFSTAT 0x5d 2174#define MDFFSTAT 0x5d
3013#define SHCNTNEGATIVE 0x40 2175#define SHCNTNEGATIVE 0x40
3014#define SHCNTMINUS1 0x20 2176#define SHCNTMINUS1 0x20
@@ -3023,29 +2185,29 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3023 2185
3024#define DFFTAG 0x5e 2186#define DFFTAG 0x5e
3025 2187
3026#define LASTSCB 0x5e
3027
3028#define SCSITEST 0x5e 2188#define SCSITEST 0x5e
3029#define CNTRTEST 0x08 2189#define CNTRTEST 0x08
3030#define SEL_TXPLL_DEBUG 0x04 2190#define SEL_TXPLL_DEBUG 0x04
3031 2191
2192#define LASTSCB 0x5e
2193
3032#define IOPDNCTL 0x5f 2194#define IOPDNCTL 0x5f
3033#define DISABLE_OE 0x80 2195#define DISABLE_OE 0x80
3034#define PDN_IDIST 0x04 2196#define PDN_IDIST 0x04
3035#define PDN_DIFFSENSE 0x01 2197#define PDN_DIFFSENSE 0x01
3036 2198
2199#define DGRPCRCI 0x60
2200
3037#define SHADDR 0x60 2201#define SHADDR 0x60
3038 2202
3039#define NEGOADDR 0x60 2203#define NEGOADDR 0x60
3040 2204
3041#define DGRPCRCI 0x60
3042
3043#define NEGPERIOD 0x61 2205#define NEGPERIOD 0x61
3044 2206
3045#define PACKCRCI 0x62
3046
3047#define NEGOFFSET 0x62 2207#define NEGOFFSET 0x62
3048 2208
2209#define PACKCRCI 0x62
2210
3049#define NEGPPROPTS 0x63 2211#define NEGPPROPTS 0x63
3050#define PPROPT_PACE 0x08 2212#define PPROPT_PACE 0x08
3051#define PPROPT_QAS 0x04 2213#define PPROPT_QAS 0x04
@@ -3066,6 +2228,7 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3066#define ANNEXDAT 0x66 2228#define ANNEXDAT 0x66
3067 2229
3068#define SCSCHKN 0x66 2230#define SCSCHKN 0x66
2231#define BIDICHKDIS 0x80
3069#define STSELSKIDDIS 0x40 2232#define STSELSKIDDIS 0x40
3070#define CURRFIFODEF 0x20 2233#define CURRFIFODEF 0x20
3071#define WIDERESEN 0x10 2234#define WIDERESEN 0x10
@@ -3090,6 +2253,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3090 2253
3091#define SELOID 0x6b 2254#define SELOID 0x6b
3092 2255
2256#define FAIRNESS 0x6c
2257
3093#define PLL400CTL0 0x6c 2258#define PLL400CTL0 0x6c
3094#define PLL_VCOSEL 0x80 2259#define PLL_VCOSEL 0x80
3095#define PLL_PWDN 0x40 2260#define PLL_PWDN 0x40
@@ -3099,8 +2264,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3099#define PLL_DLPF 0x02 2264#define PLL_DLPF 0x02
3100#define PLL_ENFBM 0x01 2265#define PLL_ENFBM 0x01
3101 2266
3102#define FAIRNESS 0x6c
3103
3104#define PLL400CTL1 0x6d 2267#define PLL400CTL1 0x6d
3105#define PLL_CNTEN 0x80 2268#define PLL_CNTEN 0x80
3106#define PLL_CNTCLR 0x40 2269#define PLL_CNTCLR 0x40
@@ -3112,25 +2275,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3112 2275
3113#define HADDR 0x70 2276#define HADDR 0x70
3114 2277
2278#define HODMAADR 0x70
2279
3115#define PLLDELAY 0x70 2280#define PLLDELAY 0x70
3116#define SPLIT_DROP_REQ 0x80 2281#define SPLIT_DROP_REQ 0x80
3117 2282
3118#define HODMAADR 0x70 2283#define HCNT 0x78
3119 2284
3120#define HODMACNT 0x78 2285#define HODMACNT 0x78
3121 2286
3122#define HCNT 0x78
3123
3124#define HODMAEN 0x7a 2287#define HODMAEN 0x7a
3125 2288
3126#define SCBHADDR 0x7c
3127
3128#define SGHADDR 0x7c 2289#define SGHADDR 0x7c
3129 2290
3130#define SCBHCNT 0x84 2291#define SCBHADDR 0x7c
3131 2292
3132#define SGHCNT 0x84 2293#define SGHCNT 0x84
3133 2294
2295#define SCBHCNT 0x84
2296
3134#define DFF_THRSH 0x88 2297#define DFF_THRSH 0x88
3135#define WR_DFTHRSH 0x70 2298#define WR_DFTHRSH 0x70
3136#define RD_DFTHRSH 0x07 2299#define RD_DFTHRSH 0x07
@@ -3163,6 +2326,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3163 2326
3164#define CMCRXMSG0 0x90 2327#define CMCRXMSG0 0x90
3165 2328
2329#define OVLYRXMSG0 0x90
2330
2331#define DCHRXMSG0 0x90
2332
3166#define ROENABLE 0x90 2333#define ROENABLE 0x90
3167#define MSIROEN 0x20 2334#define MSIROEN 0x20
3168#define OVLYROEN 0x10 2335#define OVLYROEN 0x10
@@ -3171,11 +2338,11 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3171#define DCH1ROEN 0x02 2338#define DCH1ROEN 0x02
3172#define DCH0ROEN 0x01 2339#define DCH0ROEN 0x01
3173 2340
3174#define OVLYRXMSG0 0x90 2341#define OVLYRXMSG1 0x91
3175 2342
3176#define DCHRXMSG0 0x90 2343#define CMCRXMSG1 0x91
3177 2344
3178#define OVLYRXMSG1 0x91 2345#define DCHRXMSG1 0x91
3179 2346
3180#define NSENABLE 0x91 2347#define NSENABLE 0x91
3181#define MSINSEN 0x20 2348#define MSINSEN 0x20
@@ -3185,10 +2352,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3185#define DCH1NSEN 0x02 2352#define DCH1NSEN 0x02
3186#define DCH0NSEN 0x01 2353#define DCH0NSEN 0x01
3187 2354
3188#define CMCRXMSG1 0x91
3189
3190#define DCHRXMSG1 0x91
3191
3192#define DCHRXMSG2 0x92 2355#define DCHRXMSG2 0x92
3193 2356
3194#define CMCRXMSG2 0x92 2357#define CMCRXMSG2 0x92
@@ -3212,24 +2375,24 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3212#define TSCSERREN 0x02 2375#define TSCSERREN 0x02
3213#define CMPABCDIS 0x01 2376#define CMPABCDIS 0x01
3214 2377
2378#define CMCSEQBCNT 0x94
2379
3215#define OVLYSEQBCNT 0x94 2380#define OVLYSEQBCNT 0x94
3216 2381
3217#define DCHSEQBCNT 0x94 2382#define DCHSEQBCNT 0x94
3218 2383
3219#define CMCSEQBCNT 0x94
3220
3221#define CMCSPLTSTAT0 0x96
3222
3223#define DCHSPLTSTAT0 0x96 2384#define DCHSPLTSTAT0 0x96
3224 2385
3225#define OVLYSPLTSTAT0 0x96 2386#define OVLYSPLTSTAT0 0x96
3226 2387
3227#define CMCSPLTSTAT1 0x97 2388#define CMCSPLTSTAT0 0x96
3228 2389
3229#define OVLYSPLTSTAT1 0x97 2390#define OVLYSPLTSTAT1 0x97
3230 2391
3231#define DCHSPLTSTAT1 0x97 2392#define DCHSPLTSTAT1 0x97
3232 2393
2394#define CMCSPLTSTAT1 0x97
2395
3233#define SGRXMSG0 0x98 2396#define SGRXMSG0 0x98
3234#define CDNUM 0xf8 2397#define CDNUM 0xf8
3235#define CFNUM 0x07 2398#define CFNUM 0x07
@@ -3257,18 +2420,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3257#define TAG_NUM 0x1f 2420#define TAG_NUM 0x1f
3258#define RLXORD 0x10 2421#define RLXORD 0x10
3259 2422
3260#define SGSEQBCNT 0x9c
3261
3262#define SLVSPLTOUTATTR0 0x9c 2423#define SLVSPLTOUTATTR0 0x9c
3263#define LOWER_BCNT 0xff 2424#define LOWER_BCNT 0xff
3264 2425
2426#define SGSEQBCNT 0x9c
2427
3265#define SLVSPLTOUTATTR1 0x9d 2428#define SLVSPLTOUTATTR1 0x9d
3266#define CMPLT_DNUM 0xf8 2429#define CMPLT_DNUM 0xf8
3267#define CMPLT_FNUM 0x07 2430#define CMPLT_FNUM 0x07
3268 2431
3269#define SLVSPLTOUTATTR2 0x9e
3270#define CMPLT_BNUM 0xff
3271
3272#define SGSPLTSTAT0 0x9e 2432#define SGSPLTSTAT0 0x9e
3273#define STAETERM 0x80 2433#define STAETERM 0x80
3274#define SCBCERR 0x40 2434#define SCBCERR 0x40
@@ -3279,6 +2439,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3279#define RXSCEMSG 0x02 2439#define RXSCEMSG 0x02
3280#define RXSPLTRSP 0x01 2440#define RXSPLTRSP 0x01
3281 2441
2442#define SLVSPLTOUTATTR2 0x9e
2443#define CMPLT_BNUM 0xff
2444
3282#define SGSPLTSTAT1 0x9f 2445#define SGSPLTSTAT1 0x9f
3283#define RXDATABUCKET 0x01 2446#define RXDATABUCKET 0x01
3284 2447
@@ -3334,10 +2497,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3334 2497
3335#define CCSGADDR 0xac 2498#define CCSGADDR 0xac
3336 2499
3337#define CCSCBADR_BK 0xac
3338
3339#define CCSCBADDR 0xac 2500#define CCSCBADDR 0xac
3340 2501
2502#define CCSCBADR_BK 0xac
2503
3341#define CMC_RAMBIST 0xad 2504#define CMC_RAMBIST 0xad
3342#define SG_ELEMENT_SIZE 0x80 2505#define SG_ELEMENT_SIZE 0x80
3343#define SCBRAMBIST_FAIL 0x40 2506#define SCBRAMBIST_FAIL 0x40
@@ -3391,9 +2554,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3391#define SEEDAT 0xbc 2554#define SEEDAT 0xbc
3392 2555
3393#define SEECTL 0xbe 2556#define SEECTL 0xbe
2557#define SEEOP_EWDS 0x40
3394#define SEEOP_WALL 0x40 2558#define SEEOP_WALL 0x40
3395#define SEEOP_EWEN 0x40 2559#define SEEOP_EWEN 0x40
3396#define SEEOP_EWDS 0x40
3397#define SEEOPCODE 0x70 2560#define SEEOPCODE 0x70
3398#define SEERST 0x02 2561#define SEERST 0x02
3399#define SEESTART 0x01 2562#define SEESTART 0x01
@@ -3410,25 +2573,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3410 2573
3411#define SCBCNT 0xbf 2574#define SCBCNT 0xbf
3412 2575
3413#define DFWADDR 0xc0
3414
3415#define DSPFLTRCTL 0xc0 2576#define DSPFLTRCTL 0xc0
3416#define FLTRDISABLE 0x20 2577#define FLTRDISABLE 0x20
3417#define EDGESENSE 0x10 2578#define EDGESENSE 0x10
3418#define DSPFCNTSEL 0x0f 2579#define DSPFCNTSEL 0x0f
3419 2580
2581#define DFWADDR 0xc0
2582
3420#define DSPDATACTL 0xc1 2583#define DSPDATACTL 0xc1
3421#define BYPASSENAB 0x80 2584#define BYPASSENAB 0x80
3422#define DESQDIS 0x10 2585#define DESQDIS 0x10
3423#define RCVROFFSTDIS 0x04 2586#define RCVROFFSTDIS 0x04
3424#define XMITOFFSTDIS 0x02 2587#define XMITOFFSTDIS 0x02
3425 2588
3426#define DFRADDR 0xc2
3427
3428#define DSPREQCTL 0xc2 2589#define DSPREQCTL 0xc2
3429#define MANREQCTL 0xc0 2590#define MANREQCTL 0xc0
3430#define MANREQDLY 0x3f 2591#define MANREQDLY 0x3f
3431 2592
2593#define DFRADDR 0xc2
2594
3432#define DSPACKCTL 0xc3 2595#define DSPACKCTL 0xc3
3433#define MANACKCTL 0xc0 2596#define MANACKCTL 0xc0
3434#define MANACKDLY 0x3f 2597#define MANACKDLY 0x3f
@@ -3449,14 +2612,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3449 2612
3450#define WRTBIASCALC 0xc7 2613#define WRTBIASCALC 0xc7
3451 2614
3452#define RCVRBIASCALC 0xc8
3453
3454#define DFPTRS 0xc8 2615#define DFPTRS 0xc8
3455 2616
3456#define SKEWCALC 0xc9 2617#define RCVRBIASCALC 0xc8
3457 2618
3458#define DFBKPTR 0xc9 2619#define DFBKPTR 0xc9
3459 2620
2621#define SKEWCALC 0xc9
2622
3460#define DFDBCTL 0xcb 2623#define DFDBCTL 0xcb
3461#define DFF_CIO_WR_RDY 0x20 2624#define DFF_CIO_WR_RDY 0x20
3462#define DFF_CIO_RD_RDY 0x10 2625#define DFF_CIO_RD_RDY 0x10
@@ -3541,12 +2704,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3541 2704
3542#define ACCUM_SAVE 0xfa 2705#define ACCUM_SAVE 0xfa
3543 2706
3544#define WAITING_SCB_TAILS 0x100
3545
3546#define AHD_PCI_CONFIG_BASE 0x100 2707#define AHD_PCI_CONFIG_BASE 0x100
3547 2708
3548#define SRAM_BASE 0x100 2709#define SRAM_BASE 0x100
3549 2710
2711#define WAITING_SCB_TAILS 0x100
2712
3550#define WAITING_TID_HEAD 0x120 2713#define WAITING_TID_HEAD 0x120
3551 2714
3552#define WAITING_TID_TAIL 0x122 2715#define WAITING_TID_TAIL 0x122
@@ -3575,8 +2738,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3575#define PRELOADEN 0x80 2738#define PRELOADEN 0x80
3576#define WIDEODD 0x40 2739#define WIDEODD 0x40
3577#define SCSIEN 0x20 2740#define SCSIEN 0x20
3578#define SDMAEN 0x10
3579#define SDMAENACK 0x10 2741#define SDMAENACK 0x10
2742#define SDMAEN 0x10
3580#define HDMAEN 0x08 2743#define HDMAEN 0x08
3581#define HDMAENACK 0x08 2744#define HDMAENACK 0x08
3582#define DIRECTION 0x04 2745#define DIRECTION 0x04
@@ -3674,12 +2837,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3674 2837
3675#define MK_MESSAGE_SCSIID 0x162 2838#define MK_MESSAGE_SCSIID 0x162
3676 2839
3677#define SCB_BASE 0x180
3678
3679#define SCB_RESIDUAL_DATACNT 0x180 2840#define SCB_RESIDUAL_DATACNT 0x180
3680#define SCB_CDB_STORE 0x180 2841#define SCB_CDB_STORE 0x180
3681#define SCB_HOST_CDB_PTR 0x180 2842#define SCB_HOST_CDB_PTR 0x180
3682 2843
2844#define SCB_BASE 0x180
2845
3683#define SCB_RESIDUAL_SGPTR 0x184 2846#define SCB_RESIDUAL_SGPTR 0x184
3684#define SG_ADDR_MASK 0xf8 2847#define SG_ADDR_MASK 0xf8
3685#define SG_OVERRUN_RESID 0x02 2848#define SG_OVERRUN_RESID 0x02
@@ -3747,6 +2910,17 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3747#define SCB_DISCONNECTED_LISTS 0x1b8 2910#define SCB_DISCONNECTED_LISTS 0x1b8
3748 2911
3749 2912
2913#define CMD_GROUP_CODE_SHIFT 0x05
2914#define STIMESEL_MIN 0x18
2915#define STIMESEL_SHIFT 0x03
2916#define INVALID_ADDR 0x80
2917#define AHD_PRECOMP_MASK 0x07
2918#define TARGET_DATA_IN 0x01
2919#define CCSCBADDR_MAX 0x80
2920#define NUMDSPS 0x14
2921#define SEEOP_EWEN_ADDR 0xc0
2922#define AHD_ANNEXCOL_PER_DEV0 0x04
2923#define DST_MODE_SHIFT 0x04
3750#define AHD_TIMER_MAX_US 0x18ffe7 2924#define AHD_TIMER_MAX_US 0x18ffe7
3751#define AHD_TIMER_MAX_TICKS 0xffff 2925#define AHD_TIMER_MAX_TICKS 0xffff
3752#define AHD_SENSE_BUFSIZE 0x100 2926#define AHD_SENSE_BUFSIZE 0x100
@@ -3781,43 +2955,32 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print;
3781#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 2955#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
3782#define NVRAM_SCB_OFFSET 0x2c 2956#define NVRAM_SCB_OFFSET 0x2c
3783#define STATUS_PKT_SENSE 0xff 2957#define STATUS_PKT_SENSE 0xff
3784#define CMD_GROUP_CODE_SHIFT 0x05
3785#define MAX_OFFSET_PACED_BUG 0x7f 2958#define MAX_OFFSET_PACED_BUG 0x7f
3786#define STIMESEL_BUG_ADJ 0x08 2959#define STIMESEL_BUG_ADJ 0x08
3787#define STIMESEL_MIN 0x18
3788#define STIMESEL_SHIFT 0x03
3789#define CCSGRAM_MAXSEGS 0x10 2960#define CCSGRAM_MAXSEGS 0x10
3790#define INVALID_ADDR 0x80
3791#define SEEOP_ERAL_ADDR 0x80 2961#define SEEOP_ERAL_ADDR 0x80
3792#define AHD_SLEWRATE_DEF_REVB 0x08 2962#define AHD_SLEWRATE_DEF_REVB 0x08
3793#define AHD_PRECOMP_CUTBACK_17 0x04 2963#define AHD_PRECOMP_CUTBACK_17 0x04
3794#define AHD_PRECOMP_MASK 0x07
3795#define SRC_MODE_SHIFT 0x00 2964#define SRC_MODE_SHIFT 0x00
3796#define PKT_OVERRUN_BUFSIZE 0x200 2965#define PKT_OVERRUN_BUFSIZE 0x200
3797#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 2966#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
3798#define TARGET_DATA_IN 0x01
3799#define HOST_MSG 0xff 2967#define HOST_MSG 0xff
3800#define MAX_OFFSET 0xfe 2968#define MAX_OFFSET 0xfe
3801#define BUS_16_BIT 0x01 2969#define BUS_16_BIT 0x01
3802#define CCSCBADDR_MAX 0x80
3803#define NUMDSPS 0x14
3804#define SEEOP_EWEN_ADDR 0xc0
3805#define AHD_ANNEXCOL_PER_DEV0 0x04
3806#define DST_MODE_SHIFT 0x04
3807 2970
3808 2971
3809/* Downloaded Constant Definitions */ 2972/* Downloaded Constant Definitions */
2973#define SG_SIZEOF 0x04
2974#define SG_PREFETCH_ALIGN_MASK 0x02
2975#define SG_PREFETCH_CNT_LIMIT 0x01
3810#define CACHELINE_MASK 0x07 2976#define CACHELINE_MASK 0x07
3811#define SCB_TRANSFER_SIZE 0x06 2977#define SCB_TRANSFER_SIZE 0x06
3812#define PKT_OVERRUN_BUFOFFSET 0x05 2978#define PKT_OVERRUN_BUFOFFSET 0x05
3813#define SG_SIZEOF 0x04
3814#define SG_PREFETCH_ADDR_MASK 0x03 2979#define SG_PREFETCH_ADDR_MASK 0x03
3815#define SG_PREFETCH_ALIGN_MASK 0x02
3816#define SG_PREFETCH_CNT_LIMIT 0x01
3817#define SG_PREFETCH_CNT 0x00 2980#define SG_PREFETCH_CNT 0x00
3818#define DOWNLOAD_CONST_COUNT 0x08 2981#define DOWNLOAD_CONST_COUNT 0x08
3819 2982
3820 2983
3821/* Exported Labels */ 2984/* Exported Labels */
3822#define LABEL_seq_isr 0x28f
3823#define LABEL_timer_isr 0x28b 2985#define LABEL_timer_isr 0x28b
2986#define LABEL_seq_isr 0x28f
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 20:20:04 -0500