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1/*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#95 $
41 *
42 * $FreeBSD$
43 */
44
45#ifndef _AIC79XX_H_
46#define _AIC79XX_H_
47
48/* Register Definitions */
49#include "aic79xx_reg.h"
50
51/************************* Forward Declarations *******************************/
52struct ahd_platform_data;
53struct scb_platform_data;
54
55/****************************** Useful Macros *********************************/
56#ifndef MAX
57#define MAX(a,b) (((a) > (b)) ? (a) : (b))
58#endif
59
60#ifndef MIN
61#define MIN(a,b) (((a) < (b)) ? (a) : (b))
62#endif
63
64#ifndef TRUE
65#define TRUE 1
66#endif
67#ifndef FALSE
68#define FALSE 0
69#endif
70
71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
72
73#define ALL_CHANNELS '\0'
74#define ALL_TARGETS_MASK 0xFFFF
75#define INITIATOR_WILDCARD (~0)
76#define SCB_LIST_NULL 0xFF00
77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
78#define QOUTFIFO_ENTRY_VALID 0x8000
79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
81
82#define SCSIID_TARGET(ahd, scsiid) \
83 (((scsiid) & TID) >> TID_SHIFT)
84#define SCSIID_OUR_ID(scsiid) \
85 ((scsiid) & OID)
86#define SCSIID_CHANNEL(ahd, scsiid) ('A')
87#define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88#define SCB_GET_OUR_ID(scb) \
89 SCSIID_OUR_ID((scb)->hscb->scsiid)
90#define SCB_GET_TARGET(ahd, scb) \
91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
92#define SCB_GET_CHANNEL(ahd, scb) \
93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
94#define SCB_GET_LUN(scb) \
95 ((scb)->hscb->lun)
96#define SCB_GET_TARGET_OFFSET(ahd, scb) \
97 SCB_GET_TARGET(ahd, scb)
98#define SCB_GET_TARGET_MASK(ahd, scb) \
99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
100#ifdef AHD_DEBUG
101#define SCB_IS_SILENT(scb) \
102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
103 && (((scb)->flags & SCB_SILENT) != 0))
104#else
105#define SCB_IS_SILENT(scb) \
106 (((scb)->flags & SCB_SILENT) != 0)
107#endif
108/*
109 * TCLs have the following format: TTTTLLLLLLLL
110 */
111#define TCL_TARGET_OFFSET(tcl) \
112 ((((tcl) >> 4) & TID) >> 4)
113#define TCL_LUN(tcl) \
114 (tcl & (AHD_NUM_LUNS - 1))
115#define BUILD_TCL(scsiid, lun) \
116 ((lun) | (((scsiid) & TID) << 4))
117#define BUILD_TCL_RAW(target, channel, lun) \
118 ((lun) | ((target) << 8))
119
120#define SCB_GET_TAG(scb) \
121 ahd_le16toh(scb->hscb->tag)
122
123#ifndef AHD_TARGET_MODE
124#undef AHD_TMODE_ENABLE
125#define AHD_TMODE_ENABLE 0
126#endif
127
128#define AHD_BUILD_COL_IDX(target, lun) \
129 (((lun) << 4) | target)
130
131#define AHD_GET_SCB_COL_IDX(ahd, scb) \
132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
133
134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \
135do { \
136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
138} while (0)
139
140#define AHD_COPY_SCB_COL_IDX(dst, src) \
141do { \
142 dst->hscb->scsiid = src->hscb->scsiid; \
143 dst->hscb->lun = src->hscb->lun; \
144} while (0)
145
146#define AHD_NEVER_COL_IDX 0xFFFF
147
148/**************************** Driver Constants ********************************/
149/*
150 * The maximum number of supported targets.
151 */
152#define AHD_NUM_TARGETS 16
153
154/*
155 * The maximum number of supported luns.
156 * The identify message only supports 64 luns in non-packetized transfers.
157 * You can have 2^64 luns when information unit transfers are enabled,
158 * but until we see a need to support that many, we support 256.
159 */
160#define AHD_NUM_LUNS_NONPKT 64
161#define AHD_NUM_LUNS 256
162
163/*
164 * The maximum transfer per S/G segment.
165 */
166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
167
168/*
169 * The maximum amount of SCB storage in hardware on a controller.
170 * This value represents an upper bound. Due to software design,
171 * we may not be able to use this number.
172 */
173#define AHD_SCB_MAX 512
174
175/*
176 * The maximum number of concurrent transactions supported per driver instance.
177 * Sequencer Control Blocks (SCBs) store per-transaction information.
178 */
179#define AHD_MAX_QUEUE AHD_SCB_MAX
180
181/*
182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
183 * in size and accommodate as many transactions as can be queued concurrently.
184 */
185#define AHD_QIN_SIZE AHD_MAX_QUEUE
186#define AHD_QOUT_SIZE AHD_MAX_QUEUE
187
188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
189/*
190 * The maximum amount of SCB storage we allocate in host memory.
191 */
192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
193
194/*
195 * Ring Buffer of incoming target commands.
196 * We allocate 256 to simplify the logic in the sequencer
197 * by using the natural wrap point of an 8bit counter.
198 */
199#define AHD_TMODE_CMDS 256
200
201/* Reset line assertion time in us */
202#define AHD_BUSRESET_DELAY 25
203
204/******************* Chip Characteristics/Operating Settings *****************/
205/*
206 * Chip Type
207 * The chip order is from least sophisticated to most sophisticated.
208 */
209typedef enum {
210 AHD_NONE = 0x0000,
211 AHD_CHIPID_MASK = 0x00FF,
212 AHD_AIC7901 = 0x0001,
213 AHD_AIC7902 = 0x0002,
214 AHD_AIC7901A = 0x0003,
215 AHD_PCI = 0x0100, /* Bus type PCI */
216 AHD_PCIX = 0x0200, /* Bus type PCIX */
217 AHD_BUS_MASK = 0x0F00
218} ahd_chip;
219
220/*
221 * Features available in each chip type.
222 */
223typedef enum {
224 AHD_FENONE = 0x00000,
225 AHD_WIDE = 0x00001,/* Wide Channel */
226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
229 AHD_RTI = 0x04000,/* Retained Training Support */
230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
232 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
233 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
234 AHD_AIC7901_FE = AHD_FENONE,
235 AHD_AIC7901A_FE = AHD_FENONE,
236 AHD_AIC7902_FE = AHD_MULTI_FUNC
237} ahd_feature;
238
239/*
240 * Bugs in the silicon that we work around in software.
241 */
242typedef enum {
243 AHD_BUGNONE = 0x0000,
244 /*
245 * Rev A hardware fails to update LAST/CURR/NEXTSCB
246 * correctly in certain packetized selection cases.
247 */
248 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
249 /* The wrong SCB is accessed to check the abort pending bit. */
250 AHD_ABORT_LQI_BUG = 0x0002,
251 /* Packetized bitbucket crosses packet boundaries. */
252 AHD_PKT_BITBUCKET_BUG = 0x0004,
253 /* The selection timer runs twice as long as its setting. */
254 AHD_LONG_SETIMO_BUG = 0x0008,
255 /* The Non-LQ CRC error status is delayed until phase change. */
256 AHD_NLQICRC_DELAYED_BUG = 0x0010,
257 /* The chip must be reset for all outgoing bus resets. */
258 AHD_SCSIRST_BUG = 0x0020,
259 /* Some PCIX fields must be saved and restored across chip reset. */
260 AHD_PCIX_CHIPRST_BUG = 0x0040,
261 /* MMAPIO is not functional in PCI-X mode. */
262 AHD_PCIX_MMAPIO_BUG = 0x0080,
263 /* Reads to SCBRAM fail to reset the discard timer. */
264 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
265 /* Bug workarounds that can be disabled on non-PCIX busses. */
266 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
267 | AHD_PCIX_MMAPIO_BUG
268 | AHD_PCIX_SCBRAM_RD_BUG,
269 /*
270 * LQOSTOP0 status set even for forced selections with ATN
271 * to perform non-packetized message delivery.
272 */
273 AHD_LQO_ATNO_BUG = 0x0200,
274 /* FIFO auto-flush does not always trigger. */
275 AHD_AUTOFLUSH_BUG = 0x0400,
276 /* The CLRLQO registers are not self-clearing. */
277 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
278 /* The PACKETIZED status bit refers to the previous connection. */
279 AHD_PKTIZED_STATUS_BUG = 0x1000,
280 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
281 AHD_PKT_LUN_BUG = 0x2000,
282 /*
283 * Only the FIFO allocated to the non-packetized connection may
284 * be in use during a non-packetzied connection.
285 */
286 AHD_NONPACKFIFO_BUG = 0x4000,
287 /*
288 * Writing to a DFF SCBPTR register may fail if concurent with
289 * a hardware write to the other DFF SCBPTR register. This is
290 * not currently a concern in our sequencer since all chips with
291 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
292 * occur in non-packetized connections.
293 */
294 AHD_MDFF_WSCBPTR_BUG = 0x8000,
295 /* SGHADDR updates are slow. */
296 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
297 /*
298 * Changing the MODE_PTR coincident with an interrupt that
299 * switches to a different mode will cause the interrupt to
300 * be in the mode written outside of interrupt context.
301 */
302 AHD_SET_MODE_BUG = 0x20000,
303 /* Non-packetized busfree revision does not work. */
304 AHD_BUSFREEREV_BUG = 0x40000,
305 /*
306 * Paced transfers are indicated with a non-standard PPR
307 * option bit in the neg table, 160MHz is indicated by
308 * sync factor 0x7, and the offset if off by a factor of 2.
309 */
310 AHD_PACED_NEGTABLE_BUG = 0x80000,
311 /* LQOOVERRUN false positives. */
312 AHD_LQOOVERRUN_BUG = 0x100000,
313 /*
314 * Controller write to INTSTAT will lose to a host
315 * write to CLRINT.
316 */
317 AHD_INTCOLLISION_BUG = 0x200000,
318 /*
319 * The GEM318 violates the SCSI spec by not waiting
320 * the mandated bus settle delay between phase changes
321 * in some situations. Some aic79xx chip revs. are more
322 * strict in this regard and will treat REQ assertions
323 * that fall within the bus settle delay window as
324 * glitches. This flag tells the firmware to tolerate
325 * early REQ assertions.
326 */
327 AHD_EARLY_REQ_BUG = 0x400000,
328 /*
329 * The LED does not stay on long enough in packetized modes.
330 */
331 AHD_FAINT_LED_BUG = 0x800000
332} ahd_bug;
333
334/*
335 * Configuration specific settings.
336 * The driver determines these settings by probing the
337 * chip/controller's configuration.
338 */
339typedef enum {
340 AHD_FNONE = 0x00000,
341 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
342 AHD_USEDEFAULTS = 0x00004,/*
343 * For cards without an seeprom
344 * or a BIOS to initialize the chip's
345 * SRAM, we use the default target
346 * settings.
347 */
348 AHD_SEQUENCER_DEBUG = 0x00008,
349 AHD_RESET_BUS_A = 0x00010,
350 AHD_EXTENDED_TRANS_A = 0x00020,
351 AHD_TERM_ENB_A = 0x00040,
352 AHD_SPCHK_ENB_A = 0x00080,
353 AHD_STPWLEVEL_A = 0x00100,
354 AHD_INITIATORROLE = 0x00200,/*
355 * Allow initiator operations on
356 * this controller.
357 */
358 AHD_TARGETROLE = 0x00400,/*
359 * Allow target operations on this
360 * controller.
361 */
362 AHD_RESOURCE_SHORTAGE = 0x00800,
363 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
364 AHD_INT50_SPEEDFLEX = 0x02000,/*
365 * Internal 50pin connector
366 * sits behind an aic3860
367 */
368 AHD_BIOS_ENABLED = 0x04000,
369 AHD_ALL_INTERRUPTS = 0x08000,
370 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
371 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
372 AHD_CURRENT_SENSING = 0x40000,
373 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
374 AHD_HP_BOARD = 0x100000,
375 AHD_RESET_POLL_ACTIVE = 0x200000,
376 AHD_UPDATE_PEND_CMDS = 0x400000,
377 AHD_RUNNING_QOUTFIFO = 0x800000,
378 AHD_HAD_FIRST_SEL = 0x1000000
379} ahd_flag;
380
381/************************* Hardware SCB Definition ***************************/
382
383/*
384 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
385 * consists of a "hardware SCB" mirroring the fields available on the card
386 * and additional information the kernel stores for each transaction.
387 *
388 * To minimize space utilization, a portion of the hardware scb stores
389 * different data during different portions of a SCSI transaction.
390 * As initialized by the host driver for the initiator role, this area
391 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
392 * the cdb has been presented to the target, this area serves to store
393 * residual transfer information and the SCSI status byte.
394 * For the target role, the contents of this area do not change, but
395 * still serve a different purpose than for the initiator role. See
396 * struct target_data for details.
397 */
398
399/*
400 * Status information embedded in the shared poriton of
401 * an SCB after passing the cdb to the target. The kernel
402 * driver will only read this data for transactions that
403 * complete abnormally.
404 */
405struct initiator_status {
406 uint32_t residual_datacnt; /* Residual in the current S/G seg */
407 uint32_t residual_sgptr; /* The next S/G for this transfer */
408 uint8_t scsi_status; /* Standard SCSI status byte */
409};
410
411struct target_status {
412 uint32_t residual_datacnt; /* Residual in the current S/G seg */
413 uint32_t residual_sgptr; /* The next S/G for this transfer */
414 uint8_t scsi_status; /* SCSI status to give to initiator */
415 uint8_t target_phases; /* Bitmap of phases to execute */
416 uint8_t data_phase; /* Data-In or Data-Out */
417 uint8_t initiator_tag; /* Initiator's transaction tag */
418};
419
420/*
421 * Initiator mode SCB shared data area.
422 * If the embedded CDB is 12 bytes or less, we embed
423 * the sense buffer address in the SCB. This allows
424 * us to retrieve sense information without interrupting
425 * the host in packetized mode.
426 */
427typedef uint32_t sense_addr_t;
428#define MAX_CDB_LEN 16
429#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
430union initiator_data {
431 struct {
432 uint64_t cdbptr;
433 uint8_t cdblen;
434 } cdb_from_host;
435 uint8_t cdb[MAX_CDB_LEN];
436 struct {
437 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
438 sense_addr_t sense_addr;
439 } cdb_plus_saddr;
440};
441
442/*
443 * Target mode version of the shared data SCB segment.
444 */
445struct target_data {
446 uint32_t spare[2];
447 uint8_t scsi_status; /* SCSI status to give to initiator */
448 uint8_t target_phases; /* Bitmap of phases to execute */
449 uint8_t data_phase; /* Data-In or Data-Out */
450 uint8_t initiator_tag; /* Initiator's transaction tag */
451};
452
453struct hardware_scb {
454/*0*/ union {
455 union initiator_data idata;
456 struct target_data tdata;
457 struct initiator_status istatus;
458 struct target_status tstatus;
459 } shared_data;
460/*
461 * A word about residuals.
462 * The scb is presented to the sequencer with the dataptr and datacnt
463 * fields initialized to the contents of the first S/G element to
464 * transfer. The sgptr field is initialized to the bus address for
465 * the S/G element that follows the first in the in core S/G array
466 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
467 * S/G entry for this transfer (single S/G element transfer with the
468 * first elements address and length preloaded in the dataptr/datacnt
469 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
470 * The SG_FULL_RESID flag ensures that the residual will be correctly
471 * noted even if no data transfers occur. Once the data phase is entered,
472 * the residual sgptr and datacnt are loaded from the sgptr and the
473 * datacnt fields. After each S/G element's dataptr and length are
474 * loaded into the hardware, the residual sgptr is advanced. After
475 * each S/G element is expired, its datacnt field is checked to see
476 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
477 * residual sg ptr and the transfer is considered complete. If the
478 * sequencer determines that there is a residual in the tranfer, or
479 * there is non-zero status, it will set the SG_STATUS_VALID flag in
480 * sgptr and dma the scb back into host memory. To sumarize:
481 *
482 * Sequencer:
483 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
484 * or residual_sgptr does not have SG_LIST_NULL set.
485 *
486 * o We are transfering the last segment if residual_datacnt has
487 * the SG_LAST_SEG flag set.
488 *
489 * Host:
490 * o A residual can only have occurred if a completed scb has the
491 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
492 * the residual_datacnt, and the residual_sgptr field will tell
493 * for sure.
494 *
495 * o residual_sgptr and sgptr refer to the "next" sg entry
496 * and so may point beyond the last valid sg entry for the
497 * transfer.
498 */
499#define SG_PTR_MASK 0xFFFFFFF8
500/*16*/ uint16_t tag; /* Reused by Sequencer. */
501/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
502/*19*/ uint8_t scsiid; /*
503 * Selection out Id
504 * Our Id (bits 0-3) Their ID (bits 4-7)
505 */
506/*20*/ uint8_t lun;
507/*21*/ uint8_t task_attribute;
508/*22*/ uint8_t cdb_len;
509/*23*/ uint8_t task_management;
510/*24*/ uint64_t dataptr;
511/*32*/ uint32_t datacnt; /* Byte 3 is spare. */
512/*36*/ uint32_t sgptr;
513/*40*/ uint32_t hscb_busaddr;
514/*44*/ uint32_t next_hscb_busaddr;
515/********** Long lun field only downloaded for full 8 byte lun support ********/
516/*48*/ uint8_t pkt_long_lun[8];
517/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
518/*56*/ uint8_t spare[8];
519};
520
521/************************ Kernel SCB Definitions ******************************/
522/*
523 * Some fields of the SCB are OS dependent. Here we collect the
524 * definitions for elements that all OS platforms need to include
525 * in there SCB definition.
526 */
527
528/*
529 * Definition of a scatter/gather element as transfered to the controller.
530 * The aic7xxx chips only support a 24bit length. We use the top byte of
531 * the length to store additional address bits and a flag to indicate
532 * that a given segment terminates the transfer. This gives us an
533 * addressable range of 512GB on machines with 64bit PCI or with chips
534 * that can support dual address cycles on 32bit PCI busses.
535 */
536struct ahd_dma_seg {
537 uint32_t addr;
538 uint32_t len;
539#define AHD_DMA_LAST_SEG 0x80000000
540#define AHD_SG_HIGH_ADDR_MASK 0x7F000000
541#define AHD_SG_LEN_MASK 0x00FFFFFF
542};
543
544struct ahd_dma64_seg {
545 uint64_t addr;
546 uint32_t len;
547 uint32_t pad;
548};
549
550struct map_node {
551 bus_dmamap_t dmamap;
552 dma_addr_t physaddr;
553 uint8_t *vaddr;
554 SLIST_ENTRY(map_node) links;
555};
556
557/*
558 * The current state of this SCB.
559 */
560typedef enum {
561 SCB_FLAG_NONE = 0x00000,
562 SCB_TRANSMISSION_ERROR = 0x00001,/*
563 * We detected a parity or CRC
564 * error that has effected the
565 * payload of the command. This
566 * flag is checked when normal
567 * status is returned to catch
568 * the case of a target not
569 * responding to our attempt
570 * to report the error.
571 */
572 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
573 * Another device was active
574 * during the first timeout for
575 * this SCB so we gave ourselves
576 * an additional timeout period
577 * in case it was hogging the
578 * bus.
579 */
580 SCB_DEVICE_RESET = 0x00004,
581 SCB_SENSE = 0x00008,
582 SCB_CDB32_PTR = 0x00010,
583 SCB_RECOVERY_SCB = 0x00020,
584 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
585 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
586 SCB_ABORT = 0x00100,
587 SCB_ACTIVE = 0x00200,
588 SCB_TARGET_IMMEDIATE = 0x00400,
589 SCB_PACKETIZED = 0x00800,
590 SCB_EXPECT_PPR_BUSFREE = 0x01000,
591 SCB_PKT_SENSE = 0x02000,
592 SCB_CMDPHASE_ABORT = 0x04000,
593 SCB_ON_COL_LIST = 0x08000,
594 SCB_SILENT = 0x10000 /*
595 * Be quiet about transmission type
596 * errors. They are expected and we
597 * don't want to upset the user. This
598 * flag is typically used during DV.
599 */
600} scb_flag;
601
602struct scb {
603 struct hardware_scb *hscb;
604 union {
605 SLIST_ENTRY(scb) sle;
606 LIST_ENTRY(scb) le;
607 TAILQ_ENTRY(scb) tqe;
608 } links;
609 union {
610 SLIST_ENTRY(scb) sle;
611 LIST_ENTRY(scb) le;
612 TAILQ_ENTRY(scb) tqe;
613 } links2;
614#define pending_links links2.le
615#define collision_links links2.le
616 struct scb *col_scb;
617 ahd_io_ctx_t io_ctx;
618 struct ahd_softc *ahd_softc;
619 scb_flag flags;
620#ifndef __linux__
621 bus_dmamap_t dmamap;
622#endif
623 struct scb_platform_data *platform_data;
624 struct map_node *hscb_map;
625 struct map_node *sg_map;
626 struct map_node *sense_map;
627 void *sg_list;
628 uint8_t *sense_data;
629 dma_addr_t sg_list_busaddr;
630 dma_addr_t sense_busaddr;
631 u_int sg_count;/* How full ahd_dma_seg is */
632#define AHD_MAX_LQ_CRC_ERRORS 5
633 u_int crc_retry_count;
634};
635
636TAILQ_HEAD(scb_tailq, scb);
637LIST_HEAD(scb_list, scb);
638
639struct scb_data {
640 /*
641 * TAILQ of lists of free SCBs grouped by device
642 * collision domains.
643 */
644 struct scb_tailq free_scbs;
645
646 /*
647 * Per-device lists of SCBs whose tag ID would collide
648 * with an already active tag on the device.
649 */
650 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
651
652 /*
653 * SCBs that will not collide with any active device.
654 */
655 struct scb_list any_dev_free_scb_list;
656
657 /*
658 * Mapping from tag to SCB.
659 */
660 struct scb *scbindex[AHD_SCB_MAX];
661
662 /*
663 * "Bus" addresses of our data structures.
664 */
665 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
666 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
667 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
668 SLIST_HEAD(, map_node) hscb_maps;
669 SLIST_HEAD(, map_node) sg_maps;
670 SLIST_HEAD(, map_node) sense_maps;
671 int scbs_left; /* unallocated scbs in head map_node */
672 int sgs_left; /* unallocated sgs in head map_node */
673 int sense_left; /* unallocated sense in head map_node */
674 uint16_t numscbs;
675 uint16_t maxhscbs; /* Number of SCBs on the card */
676 uint8_t init_level; /*
677 * How far we've initialized
678 * this structure.
679 */
680};
681
682/************************ Target Mode Definitions *****************************/
683
684/*
685 * Connection desciptor for select-in requests in target mode.
686 */
687struct target_cmd {
688 uint8_t scsiid; /* Our ID and the initiator's ID */
689 uint8_t identify; /* Identify message */
690 uint8_t bytes[22]; /*
691 * Bytes contains any additional message
692 * bytes terminated by 0xFF. The remainder
693 * is the cdb to execute.
694 */
695 uint8_t cmd_valid; /*
696 * When a command is complete, the firmware
697 * will set cmd_valid to all bits set.
698 * After the host has seen the command,
699 * the bits are cleared. This allows us
700 * to just peek at host memory to determine
701 * if more work is complete. cmd_valid is on
702 * an 8 byte boundary to simplify setting
703 * it on aic7880 hardware which only has
704 * limited direct access to the DMA FIFO.
705 */
706 uint8_t pad[7];
707};
708
709/*
710 * Number of events we can buffer up if we run out
711 * of immediate notify ccbs.
712 */
713#define AHD_TMODE_EVENT_BUFFER_SIZE 8
714struct ahd_tmode_event {
715 uint8_t initiator_id;
716 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
717#define EVENT_TYPE_BUS_RESET 0xFF
718 uint8_t event_arg;
719};
720
721/*
722 * Per enabled lun target mode state.
723 * As this state is directly influenced by the host OS'es target mode
724 * environment, we let the OS module define it. Forward declare the
725 * structure here so we can store arrays of them, etc. in OS neutral
726 * data structures.
727 */
728#ifdef AHD_TARGET_MODE
729struct ahd_tmode_lstate {
730 struct cam_path *path;
731 struct ccb_hdr_slist accept_tios;
732 struct ccb_hdr_slist immed_notifies;
733 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
734 uint8_t event_r_idx;
735 uint8_t event_w_idx;
736};
737#else
738struct ahd_tmode_lstate;
739#endif
740
741/******************** Transfer Negotiation Datastructures *********************/
742#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
743#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
744#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
745#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
746#define AHD_PERIOD_10MHz 0x19
747
748#define AHD_WIDTH_UNKNOWN 0xFF
749#define AHD_PERIOD_UNKNOWN 0xFF
750#define AHD_OFFSET_UNKNOWN 0xFF
751#define AHD_PPR_OPTS_UNKNOWN 0xFF
752
753/*
754 * Transfer Negotiation Information.
755 */
756struct ahd_transinfo {
757 uint8_t protocol_version; /* SCSI Revision level */
758 uint8_t transport_version; /* SPI Revision level */
759 uint8_t width; /* Bus width */
760 uint8_t period; /* Sync rate factor */
761 uint8_t offset; /* Sync offset */
762 uint8_t ppr_options; /* Parallel Protocol Request options */
763};
764
765/*
766 * Per-initiator current, goal and user transfer negotiation information. */
767struct ahd_initiator_tinfo {
768 struct ahd_transinfo curr;
769 struct ahd_transinfo goal;
770 struct ahd_transinfo user;
771};
772
773/*
774 * Per enabled target ID state.
775 * Pointers to lun target state as well as sync/wide negotiation information
776 * for each initiator<->target mapping. For the initiator role we pretend
777 * that we are the target and the targets are the initiators since the
778 * negotiation is the same regardless of role.
779 */
780struct ahd_tmode_tstate {
781 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
782 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
783
784 /*
785 * Per initiator state bitmasks.
786 */
787 uint16_t auto_negotiate;/* Auto Negotiation Required */
788 uint16_t discenable; /* Disconnection allowed */
789 uint16_t tagenable; /* Tagged Queuing allowed */
790};
791
792/*
793 * Points of interest along the negotiated transfer scale.
794 */
795#define AHD_SYNCRATE_160 0x8
796#define AHD_SYNCRATE_PACED 0x8
797#define AHD_SYNCRATE_DT 0x9
798#define AHD_SYNCRATE_ULTRA2 0xa
799#define AHD_SYNCRATE_ULTRA 0xc
800#define AHD_SYNCRATE_FAST 0x19
801#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
802#define AHD_SYNCRATE_SYNC 0x32
803#define AHD_SYNCRATE_MIN 0x60
804#define AHD_SYNCRATE_ASYNC 0xFF
805#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
806
807/* Safe and valid period for async negotiations. */
808#define AHD_ASYNC_XFER_PERIOD 0x44
809
810/*
811 * In RevA, the synctable uses a 120MHz rate for the period
812 * factor 8 and 160MHz for the period factor 7. The 120MHz
813 * rate never made it into the official SCSI spec, so we must
814 * compensate when setting the negotiation table for Rev A
815 * parts.
816 */
817#define AHD_SYNCRATE_REVA_120 0x8
818#define AHD_SYNCRATE_REVA_160 0x7
819
820/***************************** Lookup Tables **********************************/
821/*
822 * Phase -> name and message out response
823 * to parity errors in each phase table.
824 */
825struct ahd_phase_table_entry {
826 uint8_t phase;
827 uint8_t mesg_out; /* Message response to parity errors */
828 char *phasemsg;
829};
830
831/************************** Serial EEPROM Format ******************************/
832
833struct seeprom_config {
834/*
835 * Per SCSI ID Configuration Flags
836 */
837 uint16_t device_flags[16]; /* words 0-15 */
838#define CFXFER 0x003F /* synchronous transfer rate */
839#define CFXFER_ASYNC 0x3F
840#define CFQAS 0x0040 /* Negotiate QAS */
841#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
842#define CFSTART 0x0100 /* send start unit SCSI command */
843#define CFINCBIOS 0x0200 /* include in BIOS scan */
844#define CFDISC 0x0400 /* enable disconnection */
845#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
846#define CFWIDEB 0x1000 /* wide bus device */
847#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
848
849/*
850 * BIOS Control Bits
851 */
852 uint16_t bios_control; /* word 16 */
853#define CFSUPREM 0x0001 /* support all removeable drives */
854#define CFSUPREMB 0x0002 /* support removeable boot drives */
855#define CFBIOSSTATE 0x000C /* BIOS Action State */
856#define CFBS_DISABLED 0x00
857#define CFBS_ENABLED 0x04
858#define CFBS_DISABLED_SCAN 0x08
859#define CFENABLEDV 0x0010 /* Perform Domain Validation */
860#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
861#define CFSPARITY 0x0040 /* SCSI parity */
862#define CFEXTEND 0x0080 /* extended translation enabled */
863#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
864#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
865#define CFMSG_VERBOSE 0x0000
866#define CFMSG_SILENT 0x0200
867#define CFMSG_DIAG 0x0400
868#define CFRESETB 0x0800 /* reset SCSI bus at boot */
869/* UNUSED 0xf000 */
870
871/*
872 * Host Adapter Control Bits
873 */
874 uint16_t adapter_control; /* word 17 */
875#define CFAUTOTERM 0x0001 /* Perform Auto termination */
876#define CFSTERM 0x0002 /* SCSI low byte termination */
877#define CFWSTERM 0x0004 /* SCSI high byte termination */
878#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
879#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
880#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
881#define CFSTPWLEVEL 0x0040 /* Termination level control */
882#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
883#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
884#define CFCLUSTERENB 0x8000 /* Cluster Enable */
885
886/*
887 * Bus Release Time, Host Adapter ID
888 */
889 uint16_t brtime_id; /* word 18 */
890#define CFSCSIID 0x000f /* host adapter SCSI ID */
891/* UNUSED 0x00f0 */
892#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
893
894/*
895 * Maximum targets
896 */
897 uint16_t max_targets; /* word 19 */
898#define CFMAXTARG 0x00ff /* maximum targets */
899#define CFBOOTLUN 0x0f00 /* Lun to boot from */
900#define CFBOOTID 0xf000 /* Target to boot from */
901 uint16_t res_1[10]; /* words 20-29 */
902 uint16_t signature; /* BIOS Signature */
903#define CFSIGNATURE 0x400
904 uint16_t checksum; /* word 31 */
905};
906
907/*
908 * Vital Product Data used during POST and by the BIOS.
909 */
910struct vpd_config {
911 uint8_t bios_flags;
912#define VPDMASTERBIOS 0x0001
913#define VPDBOOTHOST 0x0002
914 uint8_t reserved_1[21];
915 uint8_t resource_type;
916 uint8_t resource_len[2];
917 uint8_t resource_data[8];
918 uint8_t vpd_tag;
919 uint16_t vpd_len;
920 uint8_t vpd_keyword[2];
921 uint8_t length;
922 uint8_t revision;
923 uint8_t device_flags;
924 uint8_t termnation_menus[2];
925 uint8_t fifo_threshold;
926 uint8_t end_tag;
927 uint8_t vpd_checksum;
928 uint16_t default_target_flags;
929 uint16_t default_bios_flags;
930 uint16_t default_ctrl_flags;
931 uint8_t default_irq;
932 uint8_t pci_lattime;
933 uint8_t max_target;
934 uint8_t boot_lun;
935 uint16_t signature;
936 uint8_t reserved_2;
937 uint8_t checksum;
938 uint8_t reserved_3[4];
939};
940
941/****************************** Flexport Logic ********************************/
942#define FLXADDR_TERMCTL 0x0
943#define FLX_TERMCTL_ENSECHIGH 0x8
944#define FLX_TERMCTL_ENSECLOW 0x4
945#define FLX_TERMCTL_ENPRIHIGH 0x2
946#define FLX_TERMCTL_ENPRILOW 0x1
947#define FLXADDR_ROMSTAT_CURSENSECTL 0x1
948#define FLX_ROMSTAT_SEECFG 0xF0
949#define FLX_ROMSTAT_EECFG 0x0F
950#define FLX_ROMSTAT_SEE_93C66 0x00
951#define FLX_ROMSTAT_SEE_NONE 0xF0
952#define FLX_ROMSTAT_EE_512x8 0x0
953#define FLX_ROMSTAT_EE_1MBx8 0x1
954#define FLX_ROMSTAT_EE_2MBx8 0x2
955#define FLX_ROMSTAT_EE_4MBx8 0x3
956#define FLX_ROMSTAT_EE_16MBx8 0x4
957#define CURSENSE_ENB 0x1
958#define FLXADDR_FLEXSTAT 0x2
959#define FLX_FSTAT_BUSY 0x1
960#define FLXADDR_CURRENT_STAT 0x4
961#define FLX_CSTAT_SEC_HIGH 0xC0
962#define FLX_CSTAT_SEC_LOW 0x30
963#define FLX_CSTAT_PRI_HIGH 0x0C
964#define FLX_CSTAT_PRI_LOW 0x03
965#define FLX_CSTAT_MASK 0x03
966#define FLX_CSTAT_SHIFT 2
967#define FLX_CSTAT_OKAY 0x0
968#define FLX_CSTAT_OVER 0x1
969#define FLX_CSTAT_UNDER 0x2
970#define FLX_CSTAT_INVALID 0x3
971
972int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
973 u_int start_addr, u_int count, int bstream);
974
975int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
976 u_int start_addr, u_int count);
977int ahd_wait_seeprom(struct ahd_softc *ahd);
978int ahd_verify_vpd_cksum(struct vpd_config *vpd);
979int ahd_verify_cksum(struct seeprom_config *sc);
980int ahd_acquire_seeprom(struct ahd_softc *ahd);
981void ahd_release_seeprom(struct ahd_softc *ahd);
982
983/**************************** Message Buffer *********************************/
984typedef enum {
985 MSG_FLAG_NONE = 0x00,
986 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
987 MSG_FLAG_IU_REQ_CHANGED = 0x02,
988 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
989 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
990 MSG_FLAG_PACKETIZED = 0x10
991} ahd_msg_flags;
992
993typedef enum {
994 MSG_TYPE_NONE = 0x00,
995 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
996 MSG_TYPE_INITIATOR_MSGIN = 0x02,
997 MSG_TYPE_TARGET_MSGOUT = 0x03,
998 MSG_TYPE_TARGET_MSGIN = 0x04
999} ahd_msg_type;
1000
1001typedef enum {
1002 MSGLOOP_IN_PROG,
1003 MSGLOOP_MSGCOMPLETE,
1004 MSGLOOP_TERMINATED
1005} msg_loop_stat;
1006
1007/*********************** Software Configuration Structure *********************/
1008struct ahd_suspend_channel_state {
1009 uint8_t scsiseq;
1010 uint8_t sxfrctl0;
1011 uint8_t sxfrctl1;
1012 uint8_t simode0;
1013 uint8_t simode1;
1014 uint8_t seltimer;
1015 uint8_t seqctl;
1016};
1017
1018struct ahd_suspend_state {
1019 struct ahd_suspend_channel_state channel[2];
1020 uint8_t optionmode;
1021 uint8_t dscommand0;
1022 uint8_t dspcistatus;
1023 /* hsmailbox */
1024 uint8_t crccontrol1;
1025 uint8_t scbbaddr;
1026 /* Host and sequencer SCB counts */
1027 uint8_t dff_thrsh;
1028 uint8_t *scratch_ram;
1029 uint8_t *btt;
1030};
1031
1032typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1033
1034typedef enum {
1035 AHD_MODE_DFF0,
1036 AHD_MODE_DFF1,
1037 AHD_MODE_CCHAN,
1038 AHD_MODE_SCSI,
1039 AHD_MODE_CFG,
1040 AHD_MODE_UNKNOWN
1041} ahd_mode;
1042
1043#define AHD_MK_MSK(x) (0x01 << (x))
1044#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1045#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1046#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1047#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1048#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1049#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1050#define AHD_MODE_ANY_MSK (~0)
1051
1052typedef uint8_t ahd_mode_state;
1053
1054typedef void ahd_callback_t (void *);
1055
1056struct ahd_softc {
1057 bus_space_tag_t tags[2];
1058 bus_space_handle_t bshs[2];
1059#ifndef __linux__
1060 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1061#endif
1062 struct scb_data scb_data;
1063
1064 struct hardware_scb *next_queued_hscb;
1065
1066 /*
1067 * SCBs that have been sent to the controller
1068 */
1069 LIST_HEAD(, scb) pending_scbs;
1070
1071 /*
1072 * Current register window mode information.
1073 */
1074 ahd_mode dst_mode;
1075 ahd_mode src_mode;
1076
1077 /*
1078 * Saved register window mode information
1079 * used for restore on next unpause.
1080 */
1081 ahd_mode saved_dst_mode;
1082 ahd_mode saved_src_mode;
1083
1084 /*
1085 * Platform specific data.
1086 */
1087 struct ahd_platform_data *platform_data;
1088
1089 /*
1090 * Platform specific device information.
1091 */
1092 ahd_dev_softc_t dev_softc;
1093
1094 /*
1095 * Bus specific device information.
1096 */
1097 ahd_bus_intr_t bus_intr;
1098
1099 /*
1100 * Target mode related state kept on a per enabled lun basis.
1101 * Targets that are not enabled will have null entries.
1102 * As an initiator, we keep one target entry for our initiator
1103 * ID to store our sync/wide transfer settings.
1104 */
1105 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1106
1107 /*
1108 * The black hole device responsible for handling requests for
1109 * disabled luns on enabled targets.
1110 */
1111 struct ahd_tmode_lstate *black_hole;
1112
1113 /*
1114 * Device instance currently on the bus awaiting a continue TIO
1115 * for a command that was not given the disconnect priveledge.
1116 */
1117 struct ahd_tmode_lstate *pending_device;
1118
1119 /*
1120 * Timer handles for timer driven callbacks.
1121 */
1122 ahd_timer_t reset_timer;
1123 ahd_timer_t stat_timer;
1124
1125 /*
1126 * Statistics.
1127 */
1128#define AHD_STAT_UPDATE_US 250000 /* 250ms */
1129#define AHD_STAT_BUCKETS 4
1130 u_int cmdcmplt_bucket;
1131 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1132 uint32_t cmdcmplt_total;
1133
1134 /*
1135 * Card characteristics
1136 */
1137 ahd_chip chip;
1138 ahd_feature features;
1139 ahd_bug bugs;
1140 ahd_flag flags;
1141 struct seeprom_config *seep_config;
1142
1143 /* Values to store in the SEQCTL register for pause and unpause */
1144 uint8_t unpause;
1145 uint8_t pause;
1146
1147 /* Command Queues */
1148 uint16_t qoutfifonext;
1149 uint16_t qoutfifonext_valid_tag;
1150 uint16_t qinfifonext;
1151 uint16_t qinfifo[AHD_SCB_MAX];
1152 uint16_t *qoutfifo;
1153
1154 /* Critical Section Data */
1155 struct cs *critical_sections;
1156 u_int num_critical_sections;
1157
1158 /* Buffer for handling packetized bitbucket. */
1159 uint8_t *overrun_buf;
1160
1161 /* Links for chaining softcs */
1162 TAILQ_ENTRY(ahd_softc) links;
1163
1164 /* Channel Names ('A', 'B', etc.) */
1165 char channel;
1166
1167 /* Initiator Bus ID */
1168 uint8_t our_id;
1169
1170 /*
1171 * Target incoming command FIFO.
1172 */
1173 struct target_cmd *targetcmds;
1174 uint8_t tqinfifonext;
1175
1176 /*
1177 * Cached verson of the hs_mailbox so we can avoid
1178 * pausing the sequencer during mailbox updates.
1179 */
1180 uint8_t hs_mailbox;
1181
1182 /*
1183 * Incoming and outgoing message handling.
1184 */
1185 uint8_t send_msg_perror;
1186 ahd_msg_flags msg_flags;
1187 ahd_msg_type msg_type;
1188 uint8_t msgout_buf[12];/* Message we are sending */
1189 uint8_t msgin_buf[12];/* Message we are receiving */
1190 u_int msgout_len; /* Length of message to send */
1191 u_int msgout_index; /* Current index in msgout */
1192 u_int msgin_index; /* Current index in msgin */
1193
1194 /*
1195 * Mapping information for data structures shared
1196 * between the sequencer and kernel.
1197 */
1198 bus_dma_tag_t parent_dmat;
1199 bus_dma_tag_t shared_data_dmat;
1200 bus_dmamap_t shared_data_dmamap;
1201 dma_addr_t shared_data_busaddr;
1202
1203 /* Information saved through suspend/resume cycles */
1204 struct ahd_suspend_state suspend_state;
1205
1206 /* Number of enabled target mode device on this card */
1207 u_int enabled_luns;
1208
1209 /* Initialization level of this data structure */
1210 u_int init_level;
1211
1212 /* PCI cacheline size. */
1213 u_int pci_cachesize;
1214
1215 /* IO Cell Parameters */
1216 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1217
1218 u_int stack_size;
1219 uint16_t *saved_stack;
1220
1221 /* Per-Unit descriptive information */
1222 const char *description;
1223 const char *bus_description;
1224 char *name;
1225 int unit;
1226
1227 /* Selection Timer settings */
1228 int seltime;
1229
1230 /*
1231 * Interrupt coalescing settings.
1232 */
1233#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1234#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1235#define AHD_INT_COALESCING_MAXCMDS_MAX 127
1236#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1237#define AHD_INT_COALESCING_MINCMDS_MAX 127
1238#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1239#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1240 u_int int_coalescing_timer;
1241 u_int int_coalescing_maxcmds;
1242 u_int int_coalescing_mincmds;
1243 u_int int_coalescing_threshold;
1244 u_int int_coalescing_stop_threshold;
1245
1246 uint16_t user_discenable;/* Disconnection allowed */
1247 uint16_t user_tagenable;/* Tagged Queuing allowed */
1248};
1249
1250TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1251extern struct ahd_softc_tailq ahd_tailq;
1252
1253/*************************** IO Cell Configuration ****************************/
1254#define AHD_PRECOMP_SLEW_INDEX \
1255 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1256
1257#define AHD_AMPLITUDE_INDEX \
1258 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1259
1260#define AHD_SET_SLEWRATE(ahd, new_slew) \
1261do { \
1262 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1263 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1264 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1265} while (0)
1266
1267#define AHD_SET_PRECOMP(ahd, new_pcomp) \
1268do { \
1269 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1270 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1271 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1272} while (0)
1273
1274#define AHD_SET_AMPLITUDE(ahd, new_amp) \
1275do { \
1276 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1277 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1278 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1279} while (0)
1280
1281/************************ Active Device Information ***************************/
1282typedef enum {
1283 ROLE_UNKNOWN,
1284 ROLE_INITIATOR,
1285 ROLE_TARGET
1286} role_t;
1287
1288struct ahd_devinfo {
1289 int our_scsiid;
1290 int target_offset;
1291 uint16_t target_mask;
1292 u_int target;
1293 u_int lun;
1294 char channel;
1295 role_t role; /*
1296 * Only guaranteed to be correct if not
1297 * in the busfree state.
1298 */
1299};
1300
1301/****************************** PCI Structures ********************************/
1302#define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/
1303#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */
1304#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */
1305
1306typedef int (ahd_device_setup_t)(struct ahd_softc *);
1307
1308struct ahd_pci_identity {
1309 uint64_t full_id;
1310 uint64_t id_mask;
1311 char *name;
1312 ahd_device_setup_t *setup;
1313};
1314extern struct ahd_pci_identity ahd_pci_ident_table [];
1315extern const u_int ahd_num_pci_devs;
1316
1317/***************************** VL/EISA Declarations ***************************/
1318struct aic7770_identity {
1319 uint32_t full_id;
1320 uint32_t id_mask;
1321 char *name;
1322 ahd_device_setup_t *setup;
1323};
1324extern struct aic7770_identity aic7770_ident_table [];
1325extern const int ahd_num_aic7770_devs;
1326
1327#define AHD_EISA_SLOT_OFFSET 0xc00
1328#define AHD_EISA_IOSIZE 0x100
1329
1330/*************************** Function Declarations ****************************/
1331/******************************************************************************/
1332void ahd_reset_cmds_pending(struct ahd_softc *ahd);
1333u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1334void ahd_busy_tcl(struct ahd_softc *ahd,
1335 u_int tcl, u_int busyid);
1336static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1337static __inline void
1338ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1339{
1340 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1341}
1342
1343/***************************** PCI Front End *********************************/
1344struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1345int ahd_pci_config(struct ahd_softc *,
1346 struct ahd_pci_identity *);
1347int ahd_pci_test_register_access(struct ahd_softc *);
1348
1349/************************** SCB and SCB queue management **********************/
1350int ahd_probe_scbs(struct ahd_softc *);
1351void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1352 struct scb *scb);
1353int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1354 int target, char channel, int lun,
1355 u_int tag, role_t role);
1356
1357/****************************** Initialization ********************************/
1358struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1359int ahd_softc_init(struct ahd_softc *);
1360void ahd_controller_info(struct ahd_softc *ahd, char *buf);
1361int ahd_init(struct ahd_softc *ahd);
1362int ahd_default_config(struct ahd_softc *ahd);
1363int ahd_parse_vpddata(struct ahd_softc *ahd,
1364 struct vpd_config *vpd);
1365int ahd_parse_cfgdata(struct ahd_softc *ahd,
1366 struct seeprom_config *sc);
1367void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1368void ahd_update_coalescing_values(struct ahd_softc *ahd,
1369 u_int timer,
1370 u_int maxcmds,
1371 u_int mincmds);
1372void ahd_enable_coalescing(struct ahd_softc *ahd,
1373 int enable);
1374void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1375int ahd_suspend(struct ahd_softc *ahd);
1376int ahd_resume(struct ahd_softc *ahd);
1377void ahd_softc_insert(struct ahd_softc *);
1378struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd);
1379void ahd_set_unit(struct ahd_softc *, int);
1380void ahd_set_name(struct ahd_softc *, char *);
1381struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1382void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1383void ahd_alloc_scbs(struct ahd_softc *ahd);
1384void ahd_free(struct ahd_softc *ahd);
1385int ahd_reset(struct ahd_softc *ahd, int reinit);
1386void ahd_shutdown(void *arg);
1387int ahd_write_flexport(struct ahd_softc *ahd,
1388 u_int addr, u_int value);
1389int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1390 uint8_t *value);
1391int ahd_wait_flexport(struct ahd_softc *ahd);
1392
1393/*************************** Interrupt Services *******************************/
1394void ahd_pci_intr(struct ahd_softc *ahd);
1395void ahd_clear_intstat(struct ahd_softc *ahd);
1396void ahd_flush_qoutfifo(struct ahd_softc *ahd);
1397void ahd_run_qoutfifo(struct ahd_softc *ahd);
1398#ifdef AHD_TARGET_MODE
1399void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1400#endif
1401void ahd_handle_hwerrint(struct ahd_softc *ahd);
1402void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1403void ahd_handle_scsiint(struct ahd_softc *ahd,
1404 u_int intstat);
1405void ahd_clear_critical_section(struct ahd_softc *ahd);
1406
1407/***************************** Error Recovery *********************************/
1408typedef enum {
1409 SEARCH_COMPLETE,
1410 SEARCH_COUNT,
1411 SEARCH_REMOVE,
1412 SEARCH_PRINT
1413} ahd_search_action;
1414int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1415 char channel, int lun, u_int tag,
1416 role_t role, uint32_t status,
1417 ahd_search_action action);
1418int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1419 char channel, int lun, u_int tag,
1420 int stop_on_first, int remove,
1421 int save_state);
1422void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1423int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1424 int initiate_reset);
1425int ahd_abort_scbs(struct ahd_softc *ahd, int target,
1426 char channel, int lun, u_int tag,
1427 role_t role, uint32_t status);
1428void ahd_restart(struct ahd_softc *ahd);
1429void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1430void ahd_handle_scb_status(struct ahd_softc *ahd,
1431 struct scb *scb);
1432void ahd_handle_scsi_status(struct ahd_softc *ahd,
1433 struct scb *scb);
1434void ahd_calc_residual(struct ahd_softc *ahd,
1435 struct scb *scb);
1436/*************************** Utility Functions ********************************/
1437struct ahd_phase_table_entry*
1438 ahd_lookup_phase_entry(int phase);
1439void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1440 u_int our_id, u_int target,
1441 u_int lun, char channel,
1442 role_t role);
1443/************************** Transfer Negotiation ******************************/
1444void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1445 u_int *ppr_options, u_int maxsync);
1446void ahd_validate_offset(struct ahd_softc *ahd,
1447 struct ahd_initiator_tinfo *tinfo,
1448 u_int period, u_int *offset,
1449 int wide, role_t role);
1450void ahd_validate_width(struct ahd_softc *ahd,
1451 struct ahd_initiator_tinfo *tinfo,
1452 u_int *bus_width,
1453 role_t role);
1454/*
1455 * Negotiation types. These are used to qualify if we should renegotiate
1456 * even if our goal and current transport parameters are identical.
1457 */
1458typedef enum {
1459 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1460 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1461 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1462} ahd_neg_type;
1463int ahd_update_neg_request(struct ahd_softc*,
1464 struct ahd_devinfo*,
1465 struct ahd_tmode_tstate*,
1466 struct ahd_initiator_tinfo*,
1467 ahd_neg_type);
1468void ahd_set_width(struct ahd_softc *ahd,
1469 struct ahd_devinfo *devinfo,
1470 u_int width, u_int type, int paused);
1471void ahd_set_syncrate(struct ahd_softc *ahd,
1472 struct ahd_devinfo *devinfo,
1473 u_int period, u_int offset,
1474 u_int ppr_options,
1475 u_int type, int paused);
1476typedef enum {
1477 AHD_QUEUE_NONE,
1478 AHD_QUEUE_BASIC,
1479 AHD_QUEUE_TAGGED
1480} ahd_queue_alg;
1481
1482void ahd_set_tags(struct ahd_softc *ahd,
1483 struct ahd_devinfo *devinfo,
1484 ahd_queue_alg alg);
1485
1486/**************************** Target Mode *************************************/
1487#ifdef AHD_TARGET_MODE
1488void ahd_send_lstate_events(struct ahd_softc *,
1489 struct ahd_tmode_lstate *);
1490void ahd_handle_en_lun(struct ahd_softc *ahd,
1491 struct cam_sim *sim, union ccb *ccb);
1492cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1493 struct cam_sim *sim, union ccb *ccb,
1494 struct ahd_tmode_tstate **tstate,
1495 struct ahd_tmode_lstate **lstate,
1496 int notfound_failure);
1497#ifndef AHD_TMODE_ENABLE
1498#define AHD_TMODE_ENABLE 0
1499#endif
1500#endif
1501/******************************* Debug ***************************************/
1502#ifdef AHD_DEBUG
1503extern uint32_t ahd_debug;
1504#define AHD_SHOW_MISC 0x00001
1505#define AHD_SHOW_SENSE 0x00002
1506#define AHD_SHOW_RECOVERY 0x00004
1507#define AHD_DUMP_SEEPROM 0x00008
1508#define AHD_SHOW_TERMCTL 0x00010
1509#define AHD_SHOW_MEMORY 0x00020
1510#define AHD_SHOW_MESSAGES 0x00040
1511#define AHD_SHOW_MODEPTR 0x00080
1512#define AHD_SHOW_SELTO 0x00100
1513#define AHD_SHOW_FIFOS 0x00200
1514#define AHD_SHOW_QFULL 0x00400
1515#define AHD_SHOW_DV 0x00800
1516#define AHD_SHOW_MASKED_ERRORS 0x01000
1517#define AHD_SHOW_QUEUE 0x02000
1518#define AHD_SHOW_TQIN 0x04000
1519#define AHD_SHOW_SG 0x08000
1520#define AHD_SHOW_INT_COALESCING 0x10000
1521#define AHD_DEBUG_SEQUENCER 0x20000
1522#endif
1523void ahd_print_scb(struct scb *scb);
1524void ahd_print_devinfo(struct ahd_softc *ahd,
1525 struct ahd_devinfo *devinfo);
1526void ahd_dump_sglist(struct scb *scb);
1527void ahd_dump_all_cards_state(void);
1528void ahd_dump_card_state(struct ahd_softc *ahd);
1529int ahd_print_register(ahd_reg_parse_entry_t *table,
1530 u_int num_entries,
1531 const char *name,
1532 u_int address,
1533 u_int value,
1534 u_int *cur_column,
1535 u_int wrap_point);
1536void ahd_dump_scbs(struct ahd_softc *ahd);
1537#endif /* _AIC79XX_H_ */
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