diff options
Diffstat (limited to 'drivers/scsi/aacraid/rx.c')
-rw-r--r-- | drivers/scsi/aacraid/rx.c | 46 |
1 files changed, 26 insertions, 20 deletions
diff --git a/drivers/scsi/aacraid/rx.c b/drivers/scsi/aacraid/rx.c index 630b99e1fe83..1ff25f49fada 100644 --- a/drivers/scsi/aacraid/rx.c +++ b/drivers/scsi/aacraid/rx.c | |||
@@ -63,7 +63,7 @@ static irqreturn_t aac_rx_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
63 | { | 63 | { |
64 | bellbits = rx_readl(dev, OutboundDoorbellReg); | 64 | bellbits = rx_readl(dev, OutboundDoorbellReg); |
65 | if (bellbits & DoorBellPrintfReady) { | 65 | if (bellbits & DoorBellPrintfReady) { |
66 | aac_printf(dev, le32_to_cpu(rx_readl (dev, IndexRegs.Mailbox[5]))); | 66 | aac_printf(dev, rx_readl(dev, IndexRegs.Mailbox[5])); |
67 | rx_writel(dev, MUnit.ODR,DoorBellPrintfReady); | 67 | rx_writel(dev, MUnit.ODR,DoorBellPrintfReady); |
68 | rx_writel(dev, InboundDoorbellReg,DoorBellPrintfDone); | 68 | rx_writel(dev, InboundDoorbellReg,DoorBellPrintfDone); |
69 | } | 69 | } |
@@ -98,7 +98,9 @@ static irqreturn_t aac_rx_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
98 | * for its completion. | 98 | * for its completion. |
99 | */ | 99 | */ |
100 | 100 | ||
101 | static int rx_sync_cmd(struct aac_dev *dev, u32 command, u32 p1, u32 *status) | 101 | static int rx_sync_cmd(struct aac_dev *dev, u32 command, |
102 | u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, | ||
103 | u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4) | ||
102 | { | 104 | { |
103 | unsigned long start; | 105 | unsigned long start; |
104 | int ok; | 106 | int ok; |
@@ -107,12 +109,12 @@ static int rx_sync_cmd(struct aac_dev *dev, u32 command, u32 p1, u32 *status) | |||
107 | */ | 109 | */ |
108 | rx_writel(dev, InboundMailbox0, command); | 110 | rx_writel(dev, InboundMailbox0, command); |
109 | /* | 111 | /* |
110 | * Write the parameters into Mailboxes 1 - 4 | 112 | * Write the parameters into Mailboxes 1 - 6 |
111 | */ | 113 | */ |
112 | rx_writel(dev, InboundMailbox1, p1); | 114 | rx_writel(dev, InboundMailbox1, p1); |
113 | rx_writel(dev, InboundMailbox2, 0); | 115 | rx_writel(dev, InboundMailbox2, p2); |
114 | rx_writel(dev, InboundMailbox3, 0); | 116 | rx_writel(dev, InboundMailbox3, p3); |
115 | rx_writel(dev, InboundMailbox4, 0); | 117 | rx_writel(dev, InboundMailbox4, p4); |
116 | /* | 118 | /* |
117 | * Clear the synch command doorbell to start on a clean slate. | 119 | * Clear the synch command doorbell to start on a clean slate. |
118 | */ | 120 | */ |
@@ -120,7 +122,7 @@ static int rx_sync_cmd(struct aac_dev *dev, u32 command, u32 p1, u32 *status) | |||
120 | /* | 122 | /* |
121 | * Disable doorbell interrupts | 123 | * Disable doorbell interrupts |
122 | */ | 124 | */ |
123 | rx_writeb(dev, MUnit.OIMR, dev->OIMR |= 0x04); | 125 | rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff); |
124 | /* | 126 | /* |
125 | * Force the completion of the mask register write before issuing | 127 | * Force the completion of the mask register write before issuing |
126 | * the interrupt. | 128 | * the interrupt. |
@@ -169,6 +171,14 @@ static int rx_sync_cmd(struct aac_dev *dev, u32 command, u32 p1, u32 *status) | |||
169 | */ | 171 | */ |
170 | if (status) | 172 | if (status) |
171 | *status = rx_readl(dev, IndexRegs.Mailbox[0]); | 173 | *status = rx_readl(dev, IndexRegs.Mailbox[0]); |
174 | if (r1) | ||
175 | *r1 = rx_readl(dev, IndexRegs.Mailbox[1]); | ||
176 | if (r2) | ||
177 | *r2 = rx_readl(dev, IndexRegs.Mailbox[2]); | ||
178 | if (r3) | ||
179 | *r3 = rx_readl(dev, IndexRegs.Mailbox[3]); | ||
180 | if (r4) | ||
181 | *r4 = rx_readl(dev, IndexRegs.Mailbox[4]); | ||
172 | /* | 182 | /* |
173 | * Clear the synch command doorbell. | 183 | * Clear the synch command doorbell. |
174 | */ | 184 | */ |
@@ -190,8 +200,7 @@ static int rx_sync_cmd(struct aac_dev *dev, u32 command, u32 p1, u32 *status) | |||
190 | 200 | ||
191 | static void aac_rx_interrupt_adapter(struct aac_dev *dev) | 201 | static void aac_rx_interrupt_adapter(struct aac_dev *dev) |
192 | { | 202 | { |
193 | u32 ret; | 203 | rx_sync_cmd(dev, BREAKPOINT_REQUEST, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL); |
194 | rx_sync_cmd(dev, BREAKPOINT_REQUEST, 0, &ret); | ||
195 | } | 204 | } |
196 | 205 | ||
197 | /** | 206 | /** |
@@ -220,7 +229,8 @@ static void aac_rx_notify_adapter(struct aac_dev *dev, u32 event) | |||
220 | rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_3); | 229 | rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_3); |
221 | break; | 230 | break; |
222 | case HostShutdown: | 231 | case HostShutdown: |
223 | // rx_sync_cmd(dev, HOST_CRASHING, 0, 0, 0, 0, &ret); | 232 | // rx_sync_cmd(dev, HOST_CRASHING, 0, 0, 0, 0, 0, 0, |
233 | // NULL, NULL, NULL, NULL, NULL); | ||
224 | break; | 234 | break; |
225 | case FastIo: | 235 | case FastIo: |
226 | rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_6); | 236 | rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_6); |
@@ -243,17 +253,11 @@ static void aac_rx_notify_adapter(struct aac_dev *dev, u32 event) | |||
243 | 253 | ||
244 | static void aac_rx_start_adapter(struct aac_dev *dev) | 254 | static void aac_rx_start_adapter(struct aac_dev *dev) |
245 | { | 255 | { |
246 | u32 status; | ||
247 | struct aac_init *init; | 256 | struct aac_init *init; |
248 | 257 | ||
249 | init = dev->init; | 258 | init = dev->init; |
250 | init->HostElapsedSeconds = cpu_to_le32(get_seconds()); | 259 | init->HostElapsedSeconds = cpu_to_le32(get_seconds()); |
251 | /* | 260 | /* |
252 | * Tell the adapter we are back and up and running so it will scan | ||
253 | * its command queues and enable our interrupts | ||
254 | */ | ||
255 | dev->irq_mask = (DoorBellPrintfReady | OUTBOUNDDOORBELL_1 | OUTBOUNDDOORBELL_2 | OUTBOUNDDOORBELL_3 | OUTBOUNDDOORBELL_4); | ||
256 | /* | ||
257 | * First clear out all interrupts. Then enable the one's that we | 261 | * First clear out all interrupts. Then enable the one's that we |
258 | * can handle. | 262 | * can handle. |
259 | */ | 263 | */ |
@@ -263,7 +267,8 @@ static void aac_rx_start_adapter(struct aac_dev *dev) | |||
263 | rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xfb); | 267 | rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xfb); |
264 | 268 | ||
265 | // We can only use a 32 bit address here | 269 | // We can only use a 32 bit address here |
266 | rx_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa, &status); | 270 | rx_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa, |
271 | 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL); | ||
267 | } | 272 | } |
268 | 273 | ||
269 | /** | 274 | /** |
@@ -288,8 +293,8 @@ static int aac_rx_check_health(struct aac_dev *dev) | |||
288 | if (status & KERNEL_PANIC) { | 293 | if (status & KERNEL_PANIC) { |
289 | char * buffer; | 294 | char * buffer; |
290 | struct POSTSTATUS { | 295 | struct POSTSTATUS { |
291 | u32 Post_Command; | 296 | __le32 Post_Command; |
292 | u32 Post_Address; | 297 | __le32 Post_Address; |
293 | } * post; | 298 | } * post; |
294 | dma_addr_t paddr, baddr; | 299 | dma_addr_t paddr, baddr; |
295 | int ret; | 300 | int ret; |
@@ -310,7 +315,8 @@ static int aac_rx_check_health(struct aac_dev *dev) | |||
310 | post->Post_Command = cpu_to_le32(COMMAND_POST_RESULTS); | 315 | post->Post_Command = cpu_to_le32(COMMAND_POST_RESULTS); |
311 | post->Post_Address = cpu_to_le32(baddr); | 316 | post->Post_Address = cpu_to_le32(baddr); |
312 | rx_writel(dev, MUnit.IMRx[0], paddr); | 317 | rx_writel(dev, MUnit.IMRx[0], paddr); |
313 | rx_sync_cmd(dev, COMMAND_POST_RESULTS, baddr, &status); | 318 | rx_sync_cmd(dev, COMMAND_POST_RESULTS, baddr, 0, 0, 0, 0, 0, |
319 | NULL, NULL, NULL, NULL, NULL); | ||
314 | pci_free_consistent(dev->pdev, sizeof(struct POSTSTATUS), | 320 | pci_free_consistent(dev->pdev, sizeof(struct POSTSTATUS), |
315 | post, paddr); | 321 | post, paddr); |
316 | if ((buffer[0] == '0') && (buffer[1] == 'x')) { | 322 | if ((buffer[0] == '0') && (buffer[1] == 'x')) { |