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path: root/drivers/scsi/FlashPoint.c
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Diffstat (limited to 'drivers/scsi/FlashPoint.c')
-rw-r--r--drivers/scsi/FlashPoint.c82
1 files changed, 40 insertions, 42 deletions
diff --git a/drivers/scsi/FlashPoint.c b/drivers/scsi/FlashPoint.c
index cf549ffe4baa..1c9078191d9e 100644
--- a/drivers/scsi/FlashPoint.c
+++ b/drivers/scsi/FlashPoint.c
@@ -25,8 +25,6 @@
25 25
26#define FAILURE 0xFFFFFFFFL 26#define FAILURE 0xFFFFFFFFL
27 27
28#define BITW(x) ((unsigned short)(1<<(x))) /* single-bit mask in bit position x */
29
30struct sccb; 28struct sccb;
31typedef void (*CALL_BK_FN) (struct sccb *); 29typedef void (*CALL_BK_FN) (struct sccb *);
32 30
@@ -373,9 +371,9 @@ typedef struct SCCBscam_info {
373#define SCAM_ENABLED BIT(2) 371#define SCAM_ENABLED BIT(2)
374#define SCAM_LEVEL2 BIT(3) 372#define SCAM_LEVEL2 BIT(3)
375 373
376#define RENEGO_ENA BITW(10) 374#define RENEGO_ENA BIT(10)
377#define CONNIO_ENA BITW(11) 375#define CONNIO_ENA BIT(11)
378#define GREEN_PC_ENA BITW(12) 376#define GREEN_PC_ENA BIT(12)
379 377
380#define AUTO_RATE_00 00 378#define AUTO_RATE_00 00
381#define AUTO_RATE_05 01 379#define AUTO_RATE_05 01
@@ -510,23 +508,23 @@ typedef struct SCCBscam_info {
510 508
511#define hp_intena 0x40 509#define hp_intena 0x40
512 510
513#define RESET BITW(7) 511#define RESET BIT(7)
514#define PROG_HLT BITW(6) 512#define PROG_HLT BIT(6)
515#define PARITY BITW(5) 513#define PARITY BIT(5)
516#define FIFO BITW(4) 514#define FIFO BIT(4)
517#define SEL BITW(3) 515#define SEL BIT(3)
518#define SCAM_SEL BITW(2) 516#define SCAM_SEL BIT(2)
519#define RSEL BITW(1) 517#define RSEL BIT(1)
520#define TIMEOUT BITW(0) 518#define TIMEOUT BIT(0)
521#define BUS_FREE BITW(15) 519#define BUS_FREE BIT(15)
522#define XFER_CNT_0 BITW(14) 520#define XFER_CNT_0 BIT(14)
523#define PHASE BITW(13) 521#define PHASE BIT(13)
524#define IUNKWN BITW(12) 522#define IUNKWN BIT(12)
525#define ICMD_COMP BITW(11) 523#define ICMD_COMP BIT(11)
526#define ITICKLE BITW(10) 524#define ITICKLE BIT(10)
527#define IDO_STRT BITW(9) 525#define IDO_STRT BIT(9)
528#define ITAR_DISC BITW(8) 526#define ITAR_DISC BIT(8)
529#define AUTO_INT (BITW(12)+BITW(11)+BITW(10)+BITW(9)+BITW(8)) 527#define AUTO_INT (BIT(12)+BIT(11)+BIT(10)+BIT(9)+BIT(8))
530#define CLR_ALL_INT 0xFFFF 528#define CLR_ALL_INT 0xFFFF
531#define CLR_ALL_INT_1 0xFF00 529#define CLR_ALL_INT_1 0xFF00
532 530
@@ -673,37 +671,37 @@ typedef struct SCCBscam_info {
673#define BIOS_DATA_OFFSET 0x60 671#define BIOS_DATA_OFFSET 0x60
674#define BIOS_RELATIVE_CARD 0x64 672#define BIOS_RELATIVE_CARD 0x64
675 673
676#define AR3 (BITW(9) + BITW(8)) 674#define AR3 (BIT(9) + BIT(8))
677#define SDATA BITW(10) 675#define SDATA BIT(10)
678 676
679#define CRD_OP BITW(11) /* Cmp Reg. w/ Data */ 677#define CRD_OP BIT(11) /* Cmp Reg. w/ Data */
680 678
681#define CRR_OP BITW(12) /* Cmp Reg. w. Reg. */ 679#define CRR_OP BIT(12) /* Cmp Reg. w. Reg. */
682 680
683#define CPE_OP (BITW(14)+BITW(11)) /* Cmp SCSI phs & Branch EQ */ 681#define CPE_OP (BIT(14)+BIT(11)) /* Cmp SCSI phs & Branch EQ */
684 682
685#define CPN_OP (BITW(14)+BITW(12)) /* Cmp SCSI phs & Branch NOT EQ */ 683#define CPN_OP (BIT(14)+BIT(12)) /* Cmp SCSI phs & Branch NOT EQ */
686 684
687#define ADATA_OUT 0x00 685#define ADATA_OUT 0x00
688#define ADATA_IN BITW(8) 686#define ADATA_IN BIT(8)
689#define ACOMMAND BITW(10) 687#define ACOMMAND BIT(10)
690#define ASTATUS (BITW(10)+BITW(8)) 688#define ASTATUS (BIT(10)+BIT(8))
691#define AMSG_OUT (BITW(10)+BITW(9)) 689#define AMSG_OUT (BIT(10)+BIT(9))
692#define AMSG_IN (BITW(10)+BITW(9)+BITW(8)) 690#define AMSG_IN (BIT(10)+BIT(9)+BIT(8))
693 691
694#define BRH_OP BITW(13) /* Branch */ 692#define BRH_OP BIT(13) /* Branch */
695 693
696#define ALWAYS 0x00 694#define ALWAYS 0x00
697#define EQUAL BITW(8) 695#define EQUAL BIT(8)
698#define NOT_EQ BITW(9) 696#define NOT_EQ BIT(9)
699 697
700#define TCB_OP (BITW(13)+BITW(11)) /* Test condition & branch */ 698#define TCB_OP (BIT(13)+BIT(11)) /* Test condition & branch */
701 699
702#define FIFO_0 BITW(10) 700#define FIFO_0 BIT(10)
703 701
704#define MPM_OP BITW(15) /* Match phase and move data */ 702#define MPM_OP BIT(15) /* Match phase and move data */
705 703
706#define MRR_OP BITW(14) /* Move DReg. to Reg. */ 704#define MRR_OP BIT(14) /* Move DReg. to Reg. */
707 705
708#define S_IDREG (BIT(2)+BIT(1)+BIT(0)) 706#define S_IDREG (BIT(2)+BIT(1)+BIT(0))
709 707
@@ -711,9 +709,9 @@ typedef struct SCCBscam_info {
711#define D_AR1 BIT(0) 709#define D_AR1 BIT(0)
712#define D_BUCKET (BIT(2) + BIT(1) + BIT(0)) 710#define D_BUCKET (BIT(2) + BIT(1) + BIT(0))
713 711
714#define RAT_OP (BITW(14)+BITW(13)+BITW(11)) 712#define RAT_OP (BIT(14)+BIT(13)+BIT(11))
715 713
716#define SSI_OP (BITW(15)+BITW(11)) 714#define SSI_OP (BIT(15)+BIT(11))
717 715
718#define SSI_ITAR_DISC (ITAR_DISC >> 8) 716#define SSI_ITAR_DISC (ITAR_DISC >> 8)
719#define SSI_IDO_STRT (IDO_STRT >> 8) 717#define SSI_IDO_STRT (IDO_STRT >> 8)