diff options
Diffstat (limited to 'drivers/scsi/3w-9xxx.h')
-rw-r--r-- | drivers/scsi/3w-9xxx.h | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/scsi/3w-9xxx.h b/drivers/scsi/3w-9xxx.h index 8c8ecbed3b58..46f22cdc8298 100644 --- a/drivers/scsi/3w-9xxx.h +++ b/drivers/scsi/3w-9xxx.h | |||
@@ -267,7 +267,6 @@ static twa_message_type twa_error_table[] = { | |||
267 | #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 | 267 | #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 |
268 | #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 | 268 | #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 |
269 | #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 | 269 | #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 |
270 | #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008 | ||
271 | 270 | ||
272 | /* Status register bit definitions */ | 271 | /* Status register bit definitions */ |
273 | #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 | 272 | #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 |
@@ -285,9 +284,8 @@ static twa_message_type twa_error_table[] = { | |||
285 | #define TW_STATUS_MICROCONTROLLER_READY 0x00002000 | 284 | #define TW_STATUS_MICROCONTROLLER_READY 0x00002000 |
286 | #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 | 285 | #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 |
287 | #define TW_STATUS_EXPECTED_BITS 0x00002000 | 286 | #define TW_STATUS_EXPECTED_BITS 0x00002000 |
288 | #define TW_STATUS_UNEXPECTED_BITS 0x00F00008 | 287 | #define TW_STATUS_UNEXPECTED_BITS 0x00F00000 |
289 | #define TW_STATUS_SBUF_WRITE_ERROR 0x00000008 | 288 | #define TW_STATUS_VALID_INTERRUPT 0x00DF0000 |
290 | #define TW_STATUS_VALID_INTERRUPT 0x00DF0008 | ||
291 | 289 | ||
292 | /* RESPONSE QUEUE BIT DEFINITIONS */ | 290 | /* RESPONSE QUEUE BIT DEFINITIONS */ |
293 | #define TW_RESPONSE_ID_MASK 0x00000FF0 | 291 | #define TW_RESPONSE_ID_MASK 0x00000FF0 |
@@ -324,9 +322,9 @@ static twa_message_type twa_error_table[] = { | |||
324 | 322 | ||
325 | /* Compatibility defines */ | 323 | /* Compatibility defines */ |
326 | #define TW_9000_ARCH_ID 0x5 | 324 | #define TW_9000_ARCH_ID 0x5 |
327 | #define TW_CURRENT_DRIVER_SRL 28 | 325 | #define TW_CURRENT_DRIVER_SRL 30 |
328 | #define TW_CURRENT_DRIVER_BUILD 9 | 326 | #define TW_CURRENT_DRIVER_BUILD 80 |
329 | #define TW_CURRENT_DRIVER_BRANCH 4 | 327 | #define TW_CURRENT_DRIVER_BRANCH 0 |
330 | 328 | ||
331 | /* Phase defines */ | 329 | /* Phase defines */ |
332 | #define TW_PHASE_INITIAL 0 | 330 | #define TW_PHASE_INITIAL 0 |
@@ -334,6 +332,7 @@ static twa_message_type twa_error_table[] = { | |||
334 | #define TW_PHASE_SGLIST 2 | 332 | #define TW_PHASE_SGLIST 2 |
335 | 333 | ||
336 | /* Misc defines */ | 334 | /* Misc defines */ |
335 | #define TW_9550SX_DRAIN_COMPLETED 0xFFFF | ||
337 | #define TW_SECTOR_SIZE 512 | 336 | #define TW_SECTOR_SIZE 512 |
338 | #define TW_ALIGNMENT_9000 4 /* 4 bytes */ | 337 | #define TW_ALIGNMENT_9000 4 /* 4 bytes */ |
339 | #define TW_ALIGNMENT_9000_SGL 0x3 | 338 | #define TW_ALIGNMENT_9000_SGL 0x3 |
@@ -417,6 +416,9 @@ static twa_message_type twa_error_table[] = { | |||
417 | #ifndef PCI_DEVICE_ID_3WARE_9000 | 416 | #ifndef PCI_DEVICE_ID_3WARE_9000 |
418 | #define PCI_DEVICE_ID_3WARE_9000 0x1002 | 417 | #define PCI_DEVICE_ID_3WARE_9000 0x1002 |
419 | #endif | 418 | #endif |
419 | #ifndef PCI_DEVICE_ID_3WARE_9550SX | ||
420 | #define PCI_DEVICE_ID_3WARE_9550SX 0x1003 | ||
421 | #endif | ||
420 | 422 | ||
421 | /* Bitmask macros to eliminate bitfields */ | 423 | /* Bitmask macros to eliminate bitfields */ |
422 | 424 | ||
@@ -443,6 +445,7 @@ static twa_message_type twa_error_table[] = { | |||
443 | #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4) | 445 | #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4) |
444 | #define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) | 446 | #define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) |
445 | #define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC) | 447 | #define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC) |
448 | #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30) | ||
446 | #define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | 449 | #define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
447 | #define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | 450 | #define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
448 | #define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | 451 | #define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |