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-rw-r--r--drivers/sbus/char/vfc.h171
1 files changed, 0 insertions, 171 deletions
diff --git a/drivers/sbus/char/vfc.h b/drivers/sbus/char/vfc.h
deleted file mode 100644
index a5240c52aa0b..000000000000
--- a/drivers/sbus/char/vfc.h
+++ /dev/null
@@ -1,171 +0,0 @@
1#ifndef _LINUX_VFC_H_
2#define _LINUX_VFC_H_
3
4/*
5 * The control register for the vfc is at offset 0x4000
6 * The first field ram bank is located at offset 0x5000
7 * The second field ram bank is at offset 0x7000
8 * i2c_reg address the Phillips PCF8584(see notes in vfc_i2c.c)
9 * data and transmit register.
10 * i2c_s1 controls register s1 of the PCF8584
11 * i2c_write seems to be similar to i2c_write but I am not
12 * quite sure why sun uses it
13 *
14 * I am also not sure whether or not you can read the fram bank as a
15 * whole or whether you must read each word individually from offset
16 * 0x5000 as soon as I figure it out I will update this file */
17
18struct vfc_regs {
19 char pad1[0x4000];
20 unsigned int control; /* Offset 0x4000 */
21 char pad2[0xffb]; /* from offset 0x4004 to 0x5000 */
22 unsigned int fram_bank1; /* Offset 0x5000 */
23 char pad3[0xffb]; /* from offset 0x5004 to 0x6000 */
24 unsigned int i2c_reg; /* Offset 0x6000 */
25 unsigned int i2c_magic2; /* Offset 0x6004 */
26 unsigned int i2c_s1; /* Offset 0x6008 */
27 unsigned int i2c_write; /* Offset 0x600c */
28 char pad4[0xff0]; /* from offset 0x6010 to 0x7000 */
29 unsigned int fram_bank2; /* Offset 0x7000 */
30 char pad5[0x1000];
31};
32
33#define VFC_SAA9051_NR (13)
34#define VFC_SAA9051_ADDR (0x8a)
35 /* The saa9051 returns the following for its status
36 * bit 0 - 0
37 * bit 1 - SECAM color detected (1=found,0=not found)
38 * bit 2 - COLOR detected (1=found,0=not found)
39 * bit 3 - 0
40 * bit 4 - Field frequency bit (1=60Hz (NTSC), 0=50Hz (PAL))
41 * bit 5 - 1
42 * bit 6 - horizontal frequency lock (1=transmitter found,
43 * 0=no transmitter)
44 * bit 7 - Power on reset bit (1=reset,0=at least one successful
45 * read of the status byte)
46 */
47
48#define VFC_SAA9051_PONRES (0x80)
49#define VFC_SAA9051_HLOCK (0x40)
50#define VFC_SAA9051_FD (0x10)
51#define VFC_SAA9051_CD (0x04)
52#define VFC_SAA9051_CS (0x02)
53
54
55/* The various saa9051 sub addresses */
56
57#define VFC_SAA9051_IDEL (0)
58#define VFC_SAA9051_HSY_START (1)
59#define VFC_SAA9051_HSY_STOP (2)
60#define VFC_SAA9051_HC_START (3)
61#define VFC_SAA9051_HC_STOP (4)
62#define VFC_SAA9051_HS_START (5)
63#define VFC_SAA9051_HORIZ_PEAK (6)
64#define VFC_SAA9051_HUE (7)
65#define VFC_SAA9051_C1 (8)
66#define VFC_SAA9051_C2 (9)
67#define VFC_SAA9051_C3 (0xa)
68#define VFC_SAA9051_SECAM_DELAY (0xb)
69
70
71/* Bit settings for saa9051 sub address 0x06 */
72
73#define VFC_SAA9051_AP1 (0x01)
74#define VFC_SAA9051_AP2 (0x02)
75#define VFC_SAA9051_COR1 (0x04)
76#define VFC_SAA9051_COR2 (0x08)
77#define VFC_SAA9051_BP1 (0x10)
78#define VFC_SAA9051_BP2 (0x20)
79#define VFC_SAA9051_PF (0x40)
80#define VFC_SAA9051_BY (0x80)
81
82
83/* Bit settings for saa9051 sub address 0x08 */
84
85#define VFC_SAA9051_CCFR0 (0x01)
86#define VFC_SAA9051_CCFR1 (0x02)
87#define VFC_SAA9051_YPN (0x04)
88#define VFC_SAA9051_ALT (0x08)
89#define VFC_SAA9051_CO (0x10)
90#define VFC_SAA9051_VTR (0x20)
91#define VFC_SAA9051_FS (0x40)
92#define VFC_SAA9051_HPLL (0x80)
93
94
95/* Bit settings for saa9051 sub address 9 */
96
97#define VFC_SAA9051_SS0 (0x01)
98#define VFC_SAA9051_SS1 (0x02)
99#define VFC_SAA9051_AFCC (0x04)
100#define VFC_SAA9051_CI (0x08)
101#define VFC_SAA9051_SA9D4 (0x10) /* Don't care bit */
102#define VFC_SAA9051_OEC (0x20)
103#define VFC_SAA9051_OEY (0x40)
104#define VFC_SAA9051_VNL (0x80)
105
106
107/* Bit settings for saa9051 sub address 0x0A */
108
109#define VFC_SAA9051_YDL0 (0x01)
110#define VFC_SAA9051_YDL1 (0x02)
111#define VFC_SAA9051_YDL2 (0x04)
112#define VFC_SAA9051_SS2 (0x08)
113#define VFC_SAA9051_SS3 (0x10)
114#define VFC_SAA9051_YC (0x20)
115#define VFC_SAA9051_CT (0x40)
116#define VFC_SAA9051_SYC (0x80)
117
118
119#define VFC_SAA9051_SA(a,b) ((a)->saa9051_state_array[(b)+1])
120#define vfc_update_saa9051(a) (vfc_i2c_sendbuf((a),VFC_SAA9051_ADDR,\
121 (a)->saa9051_state_array,\
122 VFC_SAA9051_NR))
123
124
125struct vfc_dev {
126 volatile struct vfc_regs __iomem *regs;
127 struct vfc_regs *phys_regs;
128 unsigned int control_reg;
129 struct mutex device_lock_mtx;
130 int instance;
131 int busy;
132 unsigned long which_io;
133 unsigned char saa9051_state_array[VFC_SAA9051_NR];
134};
135
136void captstat_reset(struct vfc_dev *);
137void memptr_reset(struct vfc_dev *);
138
139int vfc_pcf8584_init(struct vfc_dev *);
140void vfc_i2c_delay_no_busy(struct vfc_dev *, unsigned long);
141void vfc_i2c_delay(struct vfc_dev *);
142int vfc_i2c_sendbuf(struct vfc_dev *, unsigned char, char *, int) ;
143int vfc_i2c_recvbuf(struct vfc_dev *, unsigned char, char *, int) ;
144int vfc_i2c_reset_bus(struct vfc_dev *);
145int vfc_init_i2c_bus(struct vfc_dev *);
146
147#define VFC_CONTROL_DIAGMODE 0x10000000
148#define VFC_CONTROL_MEMPTR 0x20000000
149#define VFC_CONTROL_CAPTURE 0x02000000
150#define VFC_CONTROL_CAPTRESET 0x04000000
151
152#define VFC_STATUS_CAPTURE 0x08000000
153
154#ifdef VFC_IOCTL_DEBUG
155#define VFC_IOCTL_DEBUG_PRINTK(a) printk a
156#else
157#define VFC_IOCTL_DEBUG_PRINTK(a)
158#endif
159
160#ifdef VFC_I2C_DEBUG
161#define VFC_I2C_DEBUG_PRINTK(a) printk a
162#else
163#define VFC_I2C_DEBUG_PRINTK(a)
164#endif
165
166#endif /* _LINUX_VFC_H_ */
167
168
169
170
171
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 09:32:17 -0500