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-rw-r--r--drivers/rtc/Kconfig73
-rw-r--r--drivers/rtc/Makefile5
-rw-r--r--drivers/rtc/class.c4
-rw-r--r--drivers/rtc/rtc-ab3100.c2
-rw-r--r--drivers/rtc/rtc-bfin.c58
-rw-r--r--drivers/rtc/rtc-cmos.c6
-rw-r--r--drivers/rtc/rtc-ds3232.c505
-rw-r--r--drivers/rtc/rtc-fm3130.c183
-rw-r--r--drivers/rtc/rtc-imxdi.c519
-rw-r--r--drivers/rtc/rtc-isl12022.c327
-rw-r--r--drivers/rtc/rtc-jz4740.c380
-rw-r--r--drivers/rtc/rtc-lpc32xx.c414
-rw-r--r--drivers/rtc/rtc-m41t80.c16
-rw-r--r--drivers/rtc/rtc-m48t59.c5
-rw-r--r--drivers/rtc/rtc-m48t86.c2
-rw-r--r--drivers/rtc/rtc-max6900.c2
-rw-r--r--drivers/rtc/rtc-mpc5121.c4
-rw-r--r--drivers/rtc/rtc-mxc.c6
-rw-r--r--drivers/rtc/rtc-nuc900.c66
-rw-r--r--drivers/rtc/rtc-omap.c12
-rw-r--r--drivers/rtc/rtc-pcf8563.c8
-rw-r--r--drivers/rtc/rtc-pl031.c5
-rw-r--r--drivers/rtc/rtc-pxa.c42
-rw-r--r--drivers/rtc/rtc-rp5c01.c89
-rw-r--r--drivers/rtc/rtc-rs5c313.c34
-rw-r--r--drivers/rtc/rtc-rx8025.c2
-rw-r--r--drivers/rtc/rtc-s3c.c139
27 files changed, 2675 insertions, 233 deletions
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 10ba12c8c5e0..6a77437d4f5a 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -166,6 +166,17 @@ config RTC_DRV_DS1672
166 This driver can also be built as a module. If so, the module 166 This driver can also be built as a module. If so, the module
167 will be called rtc-ds1672. 167 will be called rtc-ds1672.
168 168
169config RTC_DRV_DS3232
170 tristate "Dallas/Maxim DS3232"
171 depends on RTC_CLASS && I2C
172 help
173 If you say yes here you get support for Dallas Semiconductor
174 DS3232 real-time clock chips. If an interrupt is associated
175 with the device, the alarm functionality is supported.
176
177 This driver can also be built as a module. If so, the module
178 will be called rtc-ds3232.
179
169config RTC_DRV_MAX6900 180config RTC_DRV_MAX6900
170 tristate "Maxim MAX6900" 181 tristate "Maxim MAX6900"
171 help 182 help
@@ -203,6 +214,15 @@ config RTC_DRV_ISL1208
203 This driver can also be built as a module. If so, the module 214 This driver can also be built as a module. If so, the module
204 will be called rtc-isl1208. 215 will be called rtc-isl1208.
205 216
217config RTC_DRV_ISL12022
218 tristate "Intersil ISL12022"
219 help
220 If you say yes here you get support for the
221 Intersil ISL12022 RTC chip.
222
223 This driver can also be built as a module. If so, the module
224 will be called rtc-isl12022.
225
206config RTC_DRV_X1205 226config RTC_DRV_X1205
207 tristate "Xicor/Intersil X1205" 227 tristate "Xicor/Intersil X1205"
208 help 228 help
@@ -537,6 +557,16 @@ config RTC_DRV_MSM6242
537 This driver can also be built as a module. If so, the module 557 This driver can also be built as a module. If so, the module
538 will be called rtc-msm6242. 558 will be called rtc-msm6242.
539 559
560config RTC_DRV_IMXDI
561 tristate "Freescale IMX DryIce Real Time Clock"
562 depends on ARCH_MX25
563 depends on RTC_CLASS
564 help
565 Support for Freescale IMX DryIce RTC
566
567 This driver can also be built as a module, if so, the module
568 will be called "rtc-imxdi".
569
540config RTC_MXC 570config RTC_MXC
541 tristate "Freescale MXC Real Time Clock" 571 tristate "Freescale MXC Real Time Clock"
542 depends on ARCH_MXC 572 depends on ARCH_MXC
@@ -645,9 +675,16 @@ config RTC_DRV_OMAP
645 DA8xx/OMAP-L13x chips. This driver can also be built as a 675 DA8xx/OMAP-L13x chips. This driver can also be built as a
646 module called rtc-omap. 676 module called rtc-omap.
647 677
678config HAVE_S3C_RTC
679 bool
680 help
681 This will include RTC support for Samsung SoCs. If
682 you want to include RTC support for any machine, kindly
683 select this in the respective mach-XXXX/Kconfig file.
684
648config RTC_DRV_S3C 685config RTC_DRV_S3C
649 tristate "Samsung S3C series SoC RTC" 686 tristate "Samsung S3C series SoC RTC"
650 depends on ARCH_S3C2410 || ARCH_S3C64XX 687 depends on ARCH_S3C2410 || ARCH_S3C64XX || HAVE_S3C_RTC
651 help 688 help
652 RTC (Realtime Clock) driver for the clock inbuilt into the 689 RTC (Realtime Clock) driver for the clock inbuilt into the
653 Samsung S3C24XX series of SoCs. This can provide periodic 690 Samsung S3C24XX series of SoCs. This can provide periodic
@@ -729,15 +766,15 @@ config RTC_DRV_AT32AP700X
729 AT32AP700x family processors. 766 AT32AP700x family processors.
730 767
731config RTC_DRV_AT91RM9200 768config RTC_DRV_AT91RM9200
732 tristate "AT91RM9200 or AT91SAM9RL" 769 tristate "AT91RM9200 or some AT91SAM9 RTC"
733 depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL 770 depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
734 help 771 help
735 Driver for the internal RTC (Realtime Clock) module found on 772 Driver for the internal RTC (Realtime Clock) module found on
736 Atmel AT91RM9200's and AT91SAM9RL chips. On SAM9RL chips 773 Atmel AT91RM9200's and some AT91SAM9 chips. On AT91SAM9 chips
737 this is powered by the backup power supply. 774 this is powered by the backup power supply.
738 775
739config RTC_DRV_AT91SAM9 776config RTC_DRV_AT91SAM9
740 tristate "AT91SAM9x/AT91CAP9" 777 tristate "AT91SAM9x/AT91CAP9 RTT as RTC"
741 depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40) 778 depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40)
742 help 779 help
743 RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT 780 RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT
@@ -745,8 +782,8 @@ config RTC_DRV_AT91SAM9
745 supply (such as a small coin cell battery), but do not need to 782 supply (such as a small coin cell battery), but do not need to
746 be used as RTCs. 783 be used as RTCs.
747 784
748 (On AT91SAM9rl chips you probably want to use the dedicated RTC 785 (On AT91SAM9rl and AT91SAM9G45 chips you probably want to use the
749 module and leave the RTT available for other uses.) 786 dedicated RTC module and leave the RTT available for other uses.)
750 787
751config RTC_DRV_AT91SAM9_RTT 788config RTC_DRV_AT91SAM9_RTT
752 int 789 int
@@ -774,7 +811,7 @@ config RTC_DRV_AT91SAM9_GPBR
774 811
775config RTC_DRV_AU1XXX 812config RTC_DRV_AU1XXX
776 tristate "Au1xxx Counter0 RTC support" 813 tristate "Au1xxx Counter0 RTC support"
777 depends on SOC_AU1X00 814 depends on MIPS_ALCHEMY
778 help 815 help
779 This is a driver for the Au1xxx on-chip Counter0 (Time-Of-Year 816 This is a driver for the Au1xxx on-chip Counter0 (Time-Of-Year
780 counter) to be used as a RTC. 817 counter) to be used as a RTC.
@@ -905,4 +942,24 @@ config RTC_DRV_MPC5121
905 This driver can also be built as a module. If so, the module 942 This driver can also be built as a module. If so, the module
906 will be called rtc-mpc5121. 943 will be called rtc-mpc5121.
907 944
945config RTC_DRV_JZ4740
946 tristate "Ingenic JZ4740 SoC"
947 depends on RTC_CLASS
948 depends on MACH_JZ4740
949 help
950 If you say yes here you get support for the Ingenic JZ4740 SoC RTC
951 controller.
952
953 This driver can also be buillt as a module. If so, the module
954 will be called rtc-jz4740.
955
956config RTC_DRV_LPC32XX
957 depends on ARCH_LPC32XX
958 tristate "NXP LPC32XX RTC"
959 help
960 This enables support for the NXP RTC in the LPC32XX
961
962 This driver can also be buillt as a module. If so, the module
963 will be called rtc-lpc32xx.
964
908endif # RTC_CLASS 965endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 5adbba7cf89c..7a7cb3228a1d 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -41,12 +41,17 @@ obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
41obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o 41obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
42obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o 42obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
43obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o 43obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
44obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
44obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o 45obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o
45obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o 46obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o
46obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o 47obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
47obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o 48obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o
48obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o 49obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o
50obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o
49obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o 51obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
52obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o
53obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o
54obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o
50obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o 55obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o
51obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o 56obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o
52obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o 57obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o
diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c
index 565562ba6ac9..e6539cbabb35 100644
--- a/drivers/rtc/class.c
+++ b/drivers/rtc/class.c
@@ -158,8 +158,10 @@ struct rtc_device *rtc_device_register(const char *name, struct device *dev,
158 rtc_dev_prepare(rtc); 158 rtc_dev_prepare(rtc);
159 159
160 err = device_register(&rtc->dev); 160 err = device_register(&rtc->dev);
161 if (err) 161 if (err) {
162 put_device(&rtc->dev);
162 goto exit_kfree; 163 goto exit_kfree;
164 }
163 165
164 rtc_dev_add_device(rtc); 166 rtc_dev_add_device(rtc);
165 rtc_sysfs_add_device(rtc); 167 rtc_sysfs_add_device(rtc);
diff --git a/drivers/rtc/rtc-ab3100.c b/drivers/rtc/rtc-ab3100.c
index d26780ea254b..261a07e0fb24 100644
--- a/drivers/rtc/rtc-ab3100.c
+++ b/drivers/rtc/rtc-ab3100.c
@@ -235,6 +235,7 @@ static int __init ab3100_rtc_probe(struct platform_device *pdev)
235 err = PTR_ERR(rtc); 235 err = PTR_ERR(rtc);
236 return err; 236 return err;
237 } 237 }
238 platform_set_drvdata(pdev, rtc);
238 239
239 return 0; 240 return 0;
240} 241}
@@ -244,6 +245,7 @@ static int __exit ab3100_rtc_remove(struct platform_device *pdev)
244 struct rtc_device *rtc = platform_get_drvdata(pdev); 245 struct rtc_device *rtc = platform_get_drvdata(pdev);
245 246
246 rtc_device_unregister(rtc); 247 rtc_device_unregister(rtc);
248 platform_set_drvdata(pdev, NULL);
247 return 0; 249 return 0;
248} 250}
249 251
diff --git a/drivers/rtc/rtc-bfin.c b/drivers/rtc/rtc-bfin.c
index 72b2bcc2c224..b4b6087f2234 100644
--- a/drivers/rtc/rtc-bfin.c
+++ b/drivers/rtc/rtc-bfin.c
@@ -2,7 +2,7 @@
2 * Blackfin On-Chip Real Time Clock Driver 2 * Blackfin On-Chip Real Time Clock Driver
3 * Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x 3 * Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x
4 * 4 *
5 * Copyright 2004-2009 Analog Devices Inc. 5 * Copyright 2004-2010 Analog Devices Inc.
6 * 6 *
7 * Enter bugs at http://blackfin.uclinux.org/ 7 * Enter bugs at http://blackfin.uclinux.org/
8 * 8 *
@@ -183,29 +183,33 @@ static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
183 struct bfin_rtc *rtc = dev_get_drvdata(dev); 183 struct bfin_rtc *rtc = dev_get_drvdata(dev);
184 unsigned long events = 0; 184 unsigned long events = 0;
185 bool write_complete = false; 185 bool write_complete = false;
186 u16 rtc_istat, rtc_ictl; 186 u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits;
187 187
188 dev_dbg_stamp(dev); 188 dev_dbg_stamp(dev);
189 189
190 rtc_istat = bfin_read_RTC_ISTAT(); 190 rtc_istat = bfin_read_RTC_ISTAT();
191 rtc_ictl = bfin_read_RTC_ICTL(); 191 rtc_ictl = bfin_read_RTC_ICTL();
192 rtc_istat_clear = 0;
192 193
193 if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) { 194 bits = RTC_ISTAT_WRITE_COMPLETE;
194 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); 195 if (rtc_istat & bits) {
196 rtc_istat_clear |= bits;
195 write_complete = true; 197 write_complete = true;
196 complete(&bfin_write_complete); 198 complete(&bfin_write_complete);
197 } 199 }
198 200
199 if (rtc_ictl & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) { 201 bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
200 if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) { 202 if (rtc_ictl & bits) {
201 bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY); 203 if (rtc_istat & bits) {
204 rtc_istat_clear |= bits;
202 events |= RTC_AF | RTC_IRQF; 205 events |= RTC_AF | RTC_IRQF;
203 } 206 }
204 } 207 }
205 208
206 if (rtc_ictl & RTC_ISTAT_SEC) { 209 bits = RTC_ISTAT_SEC;
207 if (rtc_istat & RTC_ISTAT_SEC) { 210 if (rtc_ictl & bits) {
208 bfin_write_RTC_ISTAT(RTC_ISTAT_SEC); 211 if (rtc_istat & bits) {
212 rtc_istat_clear |= bits;
209 events |= RTC_UF | RTC_IRQF; 213 events |= RTC_UF | RTC_IRQF;
210 } 214 }
211 } 215 }
@@ -213,9 +217,10 @@ static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
213 if (events) 217 if (events)
214 rtc_update_irq(rtc->rtc_dev, 1, events); 218 rtc_update_irq(rtc->rtc_dev, 1, events);
215 219
216 if (write_complete || events) 220 if (write_complete || events) {
221 bfin_write_RTC_ISTAT(rtc_istat_clear);
217 return IRQ_HANDLED; 222 return IRQ_HANDLED;
218 else 223 } else
219 return IRQ_NONE; 224 return IRQ_NONE;
220} 225}
221 226
@@ -422,21 +427,38 @@ static int __devexit bfin_rtc_remove(struct platform_device *pdev)
422#ifdef CONFIG_PM 427#ifdef CONFIG_PM
423static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state) 428static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state)
424{ 429{
425 if (device_may_wakeup(&pdev->dev)) { 430 struct device *dev = &pdev->dev;
431
432 dev_dbg_stamp(dev);
433
434 if (device_may_wakeup(dev)) {
426 enable_irq_wake(IRQ_RTC); 435 enable_irq_wake(IRQ_RTC);
427 bfin_rtc_sync_pending(&pdev->dev); 436 bfin_rtc_sync_pending(dev);
428 } else 437 } else
429 bfin_rtc_int_clear(-1); 438 bfin_rtc_int_clear(0);
430 439
431 return 0; 440 return 0;
432} 441}
433 442
434static int bfin_rtc_resume(struct platform_device *pdev) 443static int bfin_rtc_resume(struct platform_device *pdev)
435{ 444{
436 if (device_may_wakeup(&pdev->dev)) 445 struct device *dev = &pdev->dev;
446
447 dev_dbg_stamp(dev);
448
449 if (device_may_wakeup(dev))
437 disable_irq_wake(IRQ_RTC); 450 disable_irq_wake(IRQ_RTC);
438 else 451
439 bfin_write_RTC_ISTAT(-1); 452 /*
453 * Since only some of the RTC bits are maintained externally in the
454 * Vbat domain, we need to wait for the RTC MMRs to be synced into
455 * the core after waking up. This happens every RTC 1HZ. Once that
456 * has happened, we can go ahead and re-enable the important write
457 * complete interrupt event.
458 */
459 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))
460 continue;
461 bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE);
440 462
441 return 0; 463 return 0;
442} 464}
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index 11b8ea29d2b7..5856167a0c90 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -970,7 +970,6 @@ static inline int cmos_poweroff(struct device *dev)
970 970
971#include <linux/acpi.h> 971#include <linux/acpi.h>
972 972
973#ifdef CONFIG_PM
974static u32 rtc_handler(void *context) 973static u32 rtc_handler(void *context)
975{ 974{
976 acpi_clear_event(ACPI_EVENT_RTC); 975 acpi_clear_event(ACPI_EVENT_RTC);
@@ -999,11 +998,6 @@ static void rtc_wake_off(struct device *dev)
999{ 998{
1000 acpi_disable_event(ACPI_EVENT_RTC, 0); 999 acpi_disable_event(ACPI_EVENT_RTC, 0);
1001} 1000}
1002#else
1003#define rtc_wake_setup() do{}while(0)
1004#define rtc_wake_on NULL
1005#define rtc_wake_off NULL
1006#endif
1007 1001
1008/* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find 1002/* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find
1009 * its device node and pass extra config data. This helps its driver use 1003 * its device node and pass extra config data. This helps its driver use
diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c
new file mode 100644
index 000000000000..57063552d3b7
--- /dev/null
+++ b/drivers/rtc/rtc-ds3232.c
@@ -0,0 +1,505 @@
1/*
2 * RTC client/driver for the Maxim/Dallas DS3232 Real-Time Clock over I2C
3 *
4 * Copyright (C) 2009-2010 Freescale Semiconductor.
5 * Author: Jack Lan <jack.lan@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12/*
13 * It would be more efficient to use i2c msgs/i2c_transfer directly but, as
14 * recommened in .../Documentation/i2c/writing-clients section
15 * "Sending and receiving", using SMBus level communication is preferred.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/i2c.h>
22#include <linux/rtc.h>
23#include <linux/bcd.h>
24#include <linux/workqueue.h>
25#include <linux/slab.h>
26
27#define DS3232_REG_SECONDS 0x00
28#define DS3232_REG_MINUTES 0x01
29#define DS3232_REG_HOURS 0x02
30#define DS3232_REG_AMPM 0x02
31#define DS3232_REG_DAY 0x03
32#define DS3232_REG_DATE 0x04
33#define DS3232_REG_MONTH 0x05
34#define DS3232_REG_CENTURY 0x05
35#define DS3232_REG_YEAR 0x06
36#define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
37#define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
38#define DS3232_REG_CR 0x0E /* Control register */
39# define DS3232_REG_CR_nEOSC 0x80
40# define DS3232_REG_CR_INTCN 0x04
41# define DS3232_REG_CR_A2IE 0x02
42# define DS3232_REG_CR_A1IE 0x01
43
44#define DS3232_REG_SR 0x0F /* control/status register */
45# define DS3232_REG_SR_OSF 0x80
46# define DS3232_REG_SR_BSY 0x04
47# define DS3232_REG_SR_A2F 0x02
48# define DS3232_REG_SR_A1F 0x01
49
50struct ds3232 {
51 struct i2c_client *client;
52 struct rtc_device *rtc;
53 struct work_struct work;
54
55 /* The mutex protects alarm operations, and prevents a race
56 * between the enable_irq() in the workqueue and the free_irq()
57 * in the remove function.
58 */
59 struct mutex mutex;
60 int exiting;
61};
62
63static struct i2c_driver ds3232_driver;
64
65static int ds3232_check_rtc_status(struct i2c_client *client)
66{
67 int ret = 0;
68 int control, stat;
69
70 stat = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
71 if (stat < 0)
72 return stat;
73
74 if (stat & DS3232_REG_SR_OSF)
75 dev_warn(&client->dev,
76 "oscillator discontinuity flagged, "
77 "time unreliable\n");
78
79 stat &= ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
80
81 ret = i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
82 if (ret < 0)
83 return ret;
84
85 /* If the alarm is pending, clear it before requesting
86 * the interrupt, so an interrupt event isn't reported
87 * before everything is initialized.
88 */
89
90 control = i2c_smbus_read_byte_data(client, DS3232_REG_CR);
91 if (control < 0)
92 return control;
93
94 control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
95 control |= DS3232_REG_CR_INTCN;
96
97 return i2c_smbus_write_byte_data(client, DS3232_REG_CR, control);
98}
99
100static int ds3232_read_time(struct device *dev, struct rtc_time *time)
101{
102 struct i2c_client *client = to_i2c_client(dev);
103 int ret;
104 u8 buf[7];
105 unsigned int year, month, day, hour, minute, second;
106 unsigned int week, twelve_hr, am_pm;
107 unsigned int century, add_century = 0;
108
109 ret = i2c_smbus_read_i2c_block_data(client, DS3232_REG_SECONDS, 7, buf);
110
111 if (ret < 0)
112 return ret;
113 if (ret < 7)
114 return -EIO;
115
116 second = buf[0];
117 minute = buf[1];
118 hour = buf[2];
119 week = buf[3];
120 day = buf[4];
121 month = buf[5];
122 year = buf[6];
123
124 /* Extract additional information for AM/PM and century */
125
126 twelve_hr = hour & 0x40;
127 am_pm = hour & 0x20;
128 century = month & 0x80;
129
130 /* Write to rtc_time structure */
131
132 time->tm_sec = bcd2bin(second);
133 time->tm_min = bcd2bin(minute);
134 if (twelve_hr) {
135 /* Convert to 24 hr */
136 if (am_pm)
137 time->tm_hour = bcd2bin(hour & 0x1F) + 12;
138 else
139 time->tm_hour = bcd2bin(hour & 0x1F);
140 } else {
141 time->tm_hour = bcd2bin(hour);
142 }
143
144 time->tm_wday = bcd2bin(week);
145 time->tm_mday = bcd2bin(day);
146 time->tm_mon = bcd2bin(month & 0x7F);
147 if (century)
148 add_century = 100;
149
150 time->tm_year = bcd2bin(year) + add_century;
151
152 return rtc_valid_tm(time);
153}
154
155static int ds3232_set_time(struct device *dev, struct rtc_time *time)
156{
157 struct i2c_client *client = to_i2c_client(dev);
158 u8 buf[7];
159
160 /* Extract time from rtc_time and load into ds3232*/
161
162 buf[0] = bin2bcd(time->tm_sec);
163 buf[1] = bin2bcd(time->tm_min);
164 buf[2] = bin2bcd(time->tm_hour);
165 buf[3] = bin2bcd(time->tm_wday); /* Day of the week */
166 buf[4] = bin2bcd(time->tm_mday); /* Date */
167 buf[5] = bin2bcd(time->tm_mon);
168 if (time->tm_year >= 100) {
169 buf[5] |= 0x80;
170 buf[6] = bin2bcd(time->tm_year - 100);
171 } else {
172 buf[6] = bin2bcd(time->tm_year);
173 }
174
175 return i2c_smbus_write_i2c_block_data(client,
176 DS3232_REG_SECONDS, 7, buf);
177}
178
179/*
180 * DS3232 has two alarm, we only use alarm1
181 * According to linux specification, only support one-shot alarm
182 * no periodic alarm mode
183 */
184static int ds3232_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
185{
186 struct i2c_client *client = to_i2c_client(dev);
187 struct ds3232 *ds3232 = i2c_get_clientdata(client);
188 int control, stat;
189 int ret;
190 u8 buf[4];
191
192 mutex_lock(&ds3232->mutex);
193
194 ret = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
195 if (ret < 0)
196 goto out;
197 stat = ret;
198 ret = i2c_smbus_read_byte_data(client, DS3232_REG_CR);
199 if (ret < 0)
200 goto out;
201 control = ret;
202 ret = i2c_smbus_read_i2c_block_data(client, DS3232_REG_ALARM1, 4, buf);
203 if (ret < 0)
204 goto out;
205
206 alarm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
207 alarm->time.tm_min = bcd2bin(buf[1] & 0x7F);
208 alarm->time.tm_hour = bcd2bin(buf[2] & 0x7F);
209 alarm->time.tm_mday = bcd2bin(buf[3] & 0x7F);
210
211 alarm->time.tm_mon = -1;
212 alarm->time.tm_year = -1;
213 alarm->time.tm_wday = -1;
214 alarm->time.tm_yday = -1;
215 alarm->time.tm_isdst = -1;
216
217 alarm->enabled = !!(control & DS3232_REG_CR_A1IE);
218 alarm->pending = !!(stat & DS3232_REG_SR_A1F);
219
220 ret = 0;
221out:
222 mutex_unlock(&ds3232->mutex);
223 return ret;
224}
225
226/*
227 * linux rtc-module does not support wday alarm
228 * and only 24h time mode supported indeed
229 */
230static int ds3232_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
231{
232 struct i2c_client *client = to_i2c_client(dev);
233 struct ds3232 *ds3232 = i2c_get_clientdata(client);
234 int control, stat;
235 int ret;
236 u8 buf[4];
237
238 if (client->irq <= 0)
239 return -EINVAL;
240
241 mutex_lock(&ds3232->mutex);
242
243 buf[0] = bin2bcd(alarm->time.tm_sec);
244 buf[1] = bin2bcd(alarm->time.tm_min);
245 buf[2] = bin2bcd(alarm->time.tm_hour);
246 buf[3] = bin2bcd(alarm->time.tm_mday);
247
248 /* clear alarm interrupt enable bit */
249 ret = i2c_smbus_read_byte_data(client, DS3232_REG_CR);
250 if (ret < 0)
251 goto out;
252 control = ret;
253 control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
254 ret = i2c_smbus_write_byte_data(client, DS3232_REG_CR, control);
255 if (ret < 0)
256 goto out;
257
258 /* clear any pending alarm flag */
259 ret = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
260 if (ret < 0)
261 goto out;
262 stat = ret;
263 stat &= ~(DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
264 ret = i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
265 if (ret < 0)
266 goto out;
267
268 ret = i2c_smbus_write_i2c_block_data(client, DS3232_REG_ALARM1, 4, buf);
269
270 if (alarm->enabled) {
271 control |= DS3232_REG_CR_A1IE;
272 ret = i2c_smbus_write_byte_data(client, DS3232_REG_CR, control);
273 }
274out:
275 mutex_unlock(&ds3232->mutex);
276 return ret;
277}
278
279static void ds3232_update_alarm(struct i2c_client *client)
280{
281 struct ds3232 *ds3232 = i2c_get_clientdata(client);
282 int control;
283 int ret;
284 u8 buf[4];
285
286 mutex_lock(&ds3232->mutex);
287
288 ret = i2c_smbus_read_i2c_block_data(client, DS3232_REG_ALARM1, 4, buf);
289 if (ret < 0)
290 goto unlock;
291
292 buf[0] = bcd2bin(buf[0]) < 0 || (ds3232->rtc->irq_data & RTC_UF) ?
293 0x80 : buf[0];
294 buf[1] = bcd2bin(buf[1]) < 0 || (ds3232->rtc->irq_data & RTC_UF) ?
295 0x80 : buf[1];
296 buf[2] = bcd2bin(buf[2]) < 0 || (ds3232->rtc->irq_data & RTC_UF) ?
297 0x80 : buf[2];
298 buf[3] = bcd2bin(buf[3]) < 0 || (ds3232->rtc->irq_data & RTC_UF) ?
299 0x80 : buf[3];
300
301 ret = i2c_smbus_write_i2c_block_data(client, DS3232_REG_ALARM1, 4, buf);
302 if (ret < 0)
303 goto unlock;
304
305 control = i2c_smbus_read_byte_data(client, DS3232_REG_CR);
306 if (control < 0)
307 goto unlock;
308
309 if (ds3232->rtc->irq_data & (RTC_AF | RTC_UF))
310 /* enable alarm1 interrupt */
311 control |= DS3232_REG_CR_A1IE;
312 else
313 /* disable alarm1 interrupt */
314 control &= ~(DS3232_REG_CR_A1IE);
315 i2c_smbus_write_byte_data(client, DS3232_REG_CR, control);
316
317unlock:
318 mutex_unlock(&ds3232->mutex);
319}
320
321static int ds3232_alarm_irq_enable(struct device *dev, unsigned int enabled)
322{
323 struct i2c_client *client = to_i2c_client(dev);
324 struct ds3232 *ds3232 = i2c_get_clientdata(client);
325
326 if (client->irq <= 0)
327 return -EINVAL;
328
329 if (enabled)
330 ds3232->rtc->irq_data |= RTC_AF;
331 else
332 ds3232->rtc->irq_data &= ~RTC_AF;
333
334 ds3232_update_alarm(client);
335 return 0;
336}
337
338static int ds3232_update_irq_enable(struct device *dev, unsigned int enabled)
339{
340 struct i2c_client *client = to_i2c_client(dev);
341 struct ds3232 *ds3232 = i2c_get_clientdata(client);
342
343 if (client->irq <= 0)
344 return -EINVAL;
345
346 if (enabled)
347 ds3232->rtc->irq_data |= RTC_UF;
348 else
349 ds3232->rtc->irq_data &= ~RTC_UF;
350
351 ds3232_update_alarm(client);
352 return 0;
353}
354
355static irqreturn_t ds3232_irq(int irq, void *dev_id)
356{
357 struct i2c_client *client = dev_id;
358 struct ds3232 *ds3232 = i2c_get_clientdata(client);
359
360 disable_irq_nosync(irq);
361 schedule_work(&ds3232->work);
362 return IRQ_HANDLED;
363}
364
365static void ds3232_work(struct work_struct *work)
366{
367 struct ds3232 *ds3232 = container_of(work, struct ds3232, work);
368 struct i2c_client *client = ds3232->client;
369 int stat, control;
370
371 mutex_lock(&ds3232->mutex);
372
373 stat = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
374 if (stat < 0)
375 goto unlock;
376
377 if (stat & DS3232_REG_SR_A1F) {
378 control = i2c_smbus_read_byte_data(client, DS3232_REG_CR);
379 if (control < 0)
380 goto out;
381 /* disable alarm1 interrupt */
382 control &= ~(DS3232_REG_CR_A1IE);
383 i2c_smbus_write_byte_data(client, DS3232_REG_CR, control);
384
385 /* clear the alarm pend flag */
386 stat &= ~DS3232_REG_SR_A1F;
387 i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
388
389 rtc_update_irq(ds3232->rtc, 1, RTC_AF | RTC_IRQF);
390 }
391
392out:
393 if (!ds3232->exiting)
394 enable_irq(client->irq);
395unlock:
396 mutex_unlock(&ds3232->mutex);
397}
398
399static const struct rtc_class_ops ds3232_rtc_ops = {
400 .read_time = ds3232_read_time,
401 .set_time = ds3232_set_time,
402 .read_alarm = ds3232_read_alarm,
403 .set_alarm = ds3232_set_alarm,
404 .alarm_irq_enable = ds3232_alarm_irq_enable,
405 .update_irq_enable = ds3232_update_irq_enable,
406};
407
408static int __devinit ds3232_probe(struct i2c_client *client,
409 const struct i2c_device_id *id)
410{
411 struct ds3232 *ds3232;
412 int ret;
413
414 ds3232 = kzalloc(sizeof(struct ds3232), GFP_KERNEL);
415 if (!ds3232)
416 return -ENOMEM;
417
418 ds3232->client = client;
419 i2c_set_clientdata(client, ds3232);
420
421 INIT_WORK(&ds3232->work, ds3232_work);
422 mutex_init(&ds3232->mutex);
423
424 ret = ds3232_check_rtc_status(client);
425 if (ret)
426 goto out_free;
427
428 ds3232->rtc = rtc_device_register(client->name, &client->dev,
429 &ds3232_rtc_ops, THIS_MODULE);
430 if (IS_ERR(ds3232->rtc)) {
431 ret = PTR_ERR(ds3232->rtc);
432 dev_err(&client->dev, "unable to register the class device\n");
433 goto out_irq;
434 }
435
436 if (client->irq >= 0) {
437 ret = request_irq(client->irq, ds3232_irq, 0,
438 "ds3232", client);
439 if (ret) {
440 dev_err(&client->dev, "unable to request IRQ\n");
441 goto out_free;
442 }
443 }
444
445 return 0;
446
447out_irq:
448 if (client->irq >= 0)
449 free_irq(client->irq, client);
450
451out_free:
452 kfree(ds3232);
453 return ret;
454}
455
456static int __devexit ds3232_remove(struct i2c_client *client)
457{
458 struct ds3232 *ds3232 = i2c_get_clientdata(client);
459
460 if (client->irq >= 0) {
461 mutex_lock(&ds3232->mutex);
462 ds3232->exiting = 1;
463 mutex_unlock(&ds3232->mutex);
464
465 free_irq(client->irq, client);
466 flush_scheduled_work();
467 }
468
469 rtc_device_unregister(ds3232->rtc);
470 kfree(ds3232);
471 return 0;
472}
473
474static const struct i2c_device_id ds3232_id[] = {
475 { "ds3232", 0 },
476 { }
477};
478MODULE_DEVICE_TABLE(i2c, ds3232_id);
479
480static struct i2c_driver ds3232_driver = {
481 .driver = {
482 .name = "rtc-ds3232",
483 .owner = THIS_MODULE,
484 },
485 .probe = ds3232_probe,
486 .remove = __devexit_p(ds3232_remove),
487 .id_table = ds3232_id,
488};
489
490static int __init ds3232_init(void)
491{
492 return i2c_add_driver(&ds3232_driver);
493}
494
495static void __exit ds3232_exit(void)
496{
497 i2c_del_driver(&ds3232_driver);
498}
499
500module_init(ds3232_init);
501module_exit(ds3232_exit);
502
503MODULE_AUTHOR("Srikanth Srinivasan <srikanth.srinivasan@freescale.com>");
504MODULE_DESCRIPTION("Maxim/Dallas DS3232 RTC Driver");
505MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-fm3130.c b/drivers/rtc/rtc-fm3130.c
index ff6fce61ea41..4cf2e70c5078 100644
--- a/drivers/rtc/rtc-fm3130.c
+++ b/drivers/rtc/rtc-fm3130.c
@@ -52,8 +52,8 @@ struct fm3130 {
52 struct i2c_msg msg[4]; 52 struct i2c_msg msg[4];
53 struct i2c_client *client; 53 struct i2c_client *client;
54 struct rtc_device *rtc; 54 struct rtc_device *rtc;
55 int alarm_valid;
55 int data_valid; 56 int data_valid;
56 int alarm;
57}; 57};
58static const struct i2c_device_id fm3130_id[] = { 58static const struct i2c_device_id fm3130_id[] = {
59 { "fm3130", 0 }, 59 { "fm3130", 0 },
@@ -87,11 +87,7 @@ static void fm3130_rtc_mode(struct device *dev, int mode)
87 dev_dbg(dev, "invalid mode %d\n", mode); 87 dev_dbg(dev, "invalid mode %d\n", mode);
88 break; 88 break;
89 } 89 }
90 /* Checking for alarm */ 90
91 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AF) {
92 fm3130->alarm = 1;
93 fm3130->regs[FM3130_RTC_CONTROL] &= ~FM3130_RTC_CONTROL_BIT_AF;
94 }
95 i2c_smbus_write_byte_data(fm3130->client, 91 i2c_smbus_write_byte_data(fm3130->client,
96 FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL]); 92 FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL]);
97} 93}
@@ -104,7 +100,7 @@ static int fm3130_get_time(struct device *dev, struct rtc_time *t)
104 if (!fm3130->data_valid) { 100 if (!fm3130->data_valid) {
105 /* We have invalid data in RTC, probably due 101 /* We have invalid data in RTC, probably due
106 to battery faults or other problems. Return EIO 102 to battery faults or other problems. Return EIO
107 for now, it will allow us to set data later insted 103 for now, it will allow us to set data later instead
108 of error during probing which disables device */ 104 of error during probing which disables device */
109 return -EIO; 105 return -EIO;
110 } 106 }
@@ -208,6 +204,17 @@ static int fm3130_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
208 struct fm3130 *fm3130 = dev_get_drvdata(dev); 204 struct fm3130 *fm3130 = dev_get_drvdata(dev);
209 int tmp; 205 int tmp;
210 struct rtc_time *tm = &alrm->time; 206 struct rtc_time *tm = &alrm->time;
207
208 if (!fm3130->alarm_valid) {
209 /*
210 * We have invalid alarm in RTC, probably due to battery faults
211 * or other problems. Return EIO for now, it will allow us to
212 * set alarm value later instead of error during probing which
213 * disables device
214 */
215 return -EIO;
216 }
217
211 /* read the RTC alarm registers all at once */ 218 /* read the RTC alarm registers all at once */
212 tmp = i2c_transfer(to_i2c_adapter(fm3130->client->dev.parent), 219 tmp = i2c_transfer(to_i2c_adapter(fm3130->client->dev.parent),
213 &fm3130->msg[2], 2); 220 &fm3130->msg[2], 2);
@@ -222,20 +229,31 @@ static int fm3130_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
222 fm3130->regs[FM3130_ALARM_DATE], 229 fm3130->regs[FM3130_ALARM_DATE],
223 fm3130->regs[FM3130_ALARM_MONTHS]); 230 fm3130->regs[FM3130_ALARM_MONTHS]);
224 231
225
226 tm->tm_sec = bcd2bin(fm3130->regs[FM3130_ALARM_SECONDS] & 0x7F); 232 tm->tm_sec = bcd2bin(fm3130->regs[FM3130_ALARM_SECONDS] & 0x7F);
227 tm->tm_min = bcd2bin(fm3130->regs[FM3130_ALARM_MINUTES] & 0x7F); 233 tm->tm_min = bcd2bin(fm3130->regs[FM3130_ALARM_MINUTES] & 0x7F);
228 tm->tm_hour = bcd2bin(fm3130->regs[FM3130_ALARM_HOURS] & 0x3F); 234 tm->tm_hour = bcd2bin(fm3130->regs[FM3130_ALARM_HOURS] & 0x3F);
229 tm->tm_mday = bcd2bin(fm3130->regs[FM3130_ALARM_DATE] & 0x3F); 235 tm->tm_mday = bcd2bin(fm3130->regs[FM3130_ALARM_DATE] & 0x3F);
230 tm->tm_mon = bcd2bin(fm3130->regs[FM3130_ALARM_MONTHS] & 0x1F); 236 tm->tm_mon = bcd2bin(fm3130->regs[FM3130_ALARM_MONTHS] & 0x1F);
237
231 if (tm->tm_mon > 0) 238 if (tm->tm_mon > 0)
232 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ 239 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
240
233 dev_dbg(dev, "%s secs=%d, mins=%d, " 241 dev_dbg(dev, "%s secs=%d, mins=%d, "
234 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 242 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
235 "read alarm", tm->tm_sec, tm->tm_min, 243 "read alarm", tm->tm_sec, tm->tm_min,
236 tm->tm_hour, tm->tm_mday, 244 tm->tm_hour, tm->tm_mday,
237 tm->tm_mon, tm->tm_year, tm->tm_wday); 245 tm->tm_mon, tm->tm_year, tm->tm_wday);
238 246
247 /* check if alarm enabled */
248 fm3130->regs[FM3130_RTC_CONTROL] =
249 i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
250
251 if ((fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AEN) &&
252 (~fm3130->regs[FM3130_RTC_CONTROL] &
253 FM3130_RTC_CONTROL_BIT_CAL)) {
254 alrm->enabled = 1;
255 }
256
239 return 0; 257 return 0;
240} 258}
241 259
@@ -251,25 +269,20 @@ static int fm3130_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
251 tm->tm_hour, tm->tm_mday, 269 tm->tm_hour, tm->tm_mday,
252 tm->tm_mon, tm->tm_year, tm->tm_wday); 270 tm->tm_mon, tm->tm_year, tm->tm_wday);
253 271
254 if (tm->tm_sec != -1) 272 fm3130->regs[FM3130_ALARM_SECONDS] =
255 fm3130->regs[FM3130_ALARM_SECONDS] = 273 (tm->tm_sec != -1) ? bin2bcd(tm->tm_sec) : 0x80;
256 bin2bcd(tm->tm_sec) | 0x80;
257 274
258 if (tm->tm_min != -1) 275 fm3130->regs[FM3130_ALARM_MINUTES] =
259 fm3130->regs[FM3130_ALARM_MINUTES] = 276 (tm->tm_min != -1) ? bin2bcd(tm->tm_min) : 0x80;
260 bin2bcd(tm->tm_min) | 0x80;
261 277
262 if (tm->tm_hour != -1) 278 fm3130->regs[FM3130_ALARM_HOURS] =
263 fm3130->regs[FM3130_ALARM_HOURS] = 279 (tm->tm_hour != -1) ? bin2bcd(tm->tm_hour) : 0x80;
264 bin2bcd(tm->tm_hour) | 0x80;
265 280
266 if (tm->tm_mday != -1) 281 fm3130->regs[FM3130_ALARM_DATE] =
267 fm3130->regs[FM3130_ALARM_DATE] = 282 (tm->tm_mday != -1) ? bin2bcd(tm->tm_mday) : 0x80;
268 bin2bcd(tm->tm_mday) | 0x80;
269 283
270 if (tm->tm_mon != -1) 284 fm3130->regs[FM3130_ALARM_MONTHS] =
271 fm3130->regs[FM3130_ALARM_MONTHS] = 285 (tm->tm_mon != -1) ? bin2bcd(tm->tm_mon + 1) : 0x80;
272 bin2bcd(tm->tm_mon + 1) | 0x80;
273 286
274 dev_dbg(dev, "alarm write %02x %02x %02x %02x %02x\n", 287 dev_dbg(dev, "alarm write %02x %02x %02x %02x %02x\n",
275 fm3130->regs[FM3130_ALARM_SECONDS], 288 fm3130->regs[FM3130_ALARM_SECONDS],
@@ -285,11 +298,8 @@ static int fm3130_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
285 } 298 }
286 fm3130->regs[FM3130_RTC_CONTROL] = 299 fm3130->regs[FM3130_RTC_CONTROL] =
287 i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL); 300 i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
288 /* Checking for alarm */ 301
289 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AF) { 302 /* enable or disable alarm */
290 fm3130->alarm = 1;
291 fm3130->regs[FM3130_RTC_CONTROL] &= ~FM3130_RTC_CONTROL_BIT_AF;
292 }
293 if (alrm->enabled) { 303 if (alrm->enabled) {
294 i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL, 304 i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
295 (fm3130->regs[FM3130_RTC_CONTROL] & 305 (fm3130->regs[FM3130_RTC_CONTROL] &
@@ -298,16 +308,55 @@ static int fm3130_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
298 } else { 308 } else {
299 i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL, 309 i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
300 fm3130->regs[FM3130_RTC_CONTROL] & 310 fm3130->regs[FM3130_RTC_CONTROL] &
301 ~(FM3130_RTC_CONTROL_BIT_AEN)); 311 ~(FM3130_RTC_CONTROL_BIT_CAL) &
312 ~(FM3130_RTC_CONTROL_BIT_AEN));
302 } 313 }
314
315 /* We assume here that data is valid once written */
316 if (!fm3130->alarm_valid)
317 fm3130->alarm_valid = 1;
318
303 return 0; 319 return 0;
304} 320}
305 321
322static int fm3130_alarm_irq_enable(struct device *dev, unsigned int enabled)
323{
324 struct fm3130 *fm3130 = dev_get_drvdata(dev);
325 int ret = 0;
326
327 fm3130->regs[FM3130_RTC_CONTROL] =
328 i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
329
330 dev_dbg(dev, "alarm_irq_enable: enable=%d, FM3130_RTC_CONTROL=%02x\n",
331 enabled, fm3130->regs[FM3130_RTC_CONTROL]);
332
333 switch (enabled) {
334 case 0: /* alarm off */
335 ret = i2c_smbus_write_byte_data(fm3130->client,
336 FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL] &
337 ~(FM3130_RTC_CONTROL_BIT_CAL) &
338 ~(FM3130_RTC_CONTROL_BIT_AEN));
339 break;
340 case 1: /* alarm on */
341 ret = i2c_smbus_write_byte_data(fm3130->client,
342 FM3130_RTC_CONTROL, (fm3130->regs[FM3130_RTC_CONTROL] &
343 ~(FM3130_RTC_CONTROL_BIT_CAL)) |
344 FM3130_RTC_CONTROL_BIT_AEN);
345 break;
346 default:
347 ret = -EINVAL;
348 break;
349 }
350
351 return ret;
352}
353
306static const struct rtc_class_ops fm3130_rtc_ops = { 354static const struct rtc_class_ops fm3130_rtc_ops = {
307 .read_time = fm3130_get_time, 355 .read_time = fm3130_get_time,
308 .set_time = fm3130_set_time, 356 .set_time = fm3130_set_time,
309 .read_alarm = fm3130_read_alarm, 357 .read_alarm = fm3130_read_alarm,
310 .set_alarm = fm3130_set_alarm, 358 .set_alarm = fm3130_set_alarm,
359 .alarm_irq_enable = fm3130_alarm_irq_enable,
311}; 360};
312 361
313static struct i2c_driver fm3130_driver; 362static struct i2c_driver fm3130_driver;
@@ -356,6 +405,7 @@ static int __devinit fm3130_probe(struct i2c_client *client,
356 fm3130->msg[3].len = FM3130_ALARM_REGS; 405 fm3130->msg[3].len = FM3130_ALARM_REGS;
357 fm3130->msg[3].buf = &fm3130->regs[FM3130_ALARM_SECONDS]; 406 fm3130->msg[3].buf = &fm3130->regs[FM3130_ALARM_SECONDS];
358 407
408 fm3130->alarm_valid = 0;
359 fm3130->data_valid = 0; 409 fm3130->data_valid = 0;
360 410
361 tmp = i2c_transfer(adapter, fm3130->msg, 4); 411 tmp = i2c_transfer(adapter, fm3130->msg, 4);
@@ -370,12 +420,6 @@ static int __devinit fm3130_probe(struct i2c_client *client,
370 fm3130->regs[FM3130_CAL_CONTROL] = 420 fm3130->regs[FM3130_CAL_CONTROL] =
371 i2c_smbus_read_byte_data(client, FM3130_CAL_CONTROL); 421 i2c_smbus_read_byte_data(client, FM3130_CAL_CONTROL);
372 422
373 /* Checking for alarm */
374 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AF) {
375 fm3130->alarm = 1;
376 fm3130->regs[FM3130_RTC_CONTROL] &= ~FM3130_RTC_CONTROL_BIT_AF;
377 }
378
379 /* Disabling calibration mode */ 423 /* Disabling calibration mode */
380 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) { 424 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) {
381 i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL, 425 i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
@@ -400,44 +444,79 @@ static int __devinit fm3130_probe(struct i2c_client *client,
400 fm3130->regs[FM3130_CAL_CONTROL] & 444 fm3130->regs[FM3130_CAL_CONTROL] &
401 ~(FM3130_CAL_CONTROL_BIT_nOSCEN)); 445 ~(FM3130_CAL_CONTROL_BIT_nOSCEN));
402 446
403 /* oscillator fault? clear flag, and warn */ 447 /* low battery? clear flag, and warn */
404 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_LB) 448 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_LB) {
449 i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
450 fm3130->regs[FM3130_RTC_CONTROL] &
451 ~(FM3130_RTC_CONTROL_BIT_LB));
405 dev_warn(&client->dev, "Low battery!\n"); 452 dev_warn(&client->dev, "Low battery!\n");
453 }
406 454
407 /* oscillator fault? clear flag, and warn */ 455 /* check if Power On Reset bit is set */
408 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_POR) { 456 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_POR) {
409 i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL, 457 i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
410 fm3130->regs[FM3130_RTC_CONTROL] & 458 fm3130->regs[FM3130_RTC_CONTROL] &
411 ~FM3130_RTC_CONTROL_BIT_POR); 459 ~FM3130_RTC_CONTROL_BIT_POR);
412 dev_warn(&client->dev, "SET TIME!\n"); 460 dev_dbg(&client->dev, "POR bit is set\n");
413 } 461 }
414 /* ACS is controlled by alarm */ 462 /* ACS is controlled by alarm */
415 i2c_smbus_write_byte_data(client, FM3130_ALARM_WP_CONTROL, 0x80); 463 i2c_smbus_write_byte_data(client, FM3130_ALARM_WP_CONTROL, 0x80);
416 464
417 /* TODO */ 465 /* alarm registers sanity check */
418 /* TODO need to sanity check alarm */ 466 tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
419 tmp = fm3130->regs[FM3130_RTC_SECONDS]; 467 if (tmp > 59)
420 tmp = bcd2bin(tmp & 0x7f); 468 goto bad_alarm;
421 if (tmp > 60) 469
422 goto exit_bad;
423 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f); 470 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
424 if (tmp > 60) 471 if (tmp > 59)
425 goto exit_bad; 472 goto bad_alarm;
473
474 tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
475 if (tmp > 23)
476 goto bad_alarm;
426 477
427 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f); 478 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
428 if (tmp == 0 || tmp > 31) 479 if (tmp == 0 || tmp > 31)
429 goto exit_bad; 480 goto bad_alarm;
430 481
431 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f); 482 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
432 if (tmp == 0 || tmp > 12) 483 if (tmp == 0 || tmp > 12)
433 goto exit_bad; 484 goto bad_alarm;
434 485
435 tmp = fm3130->regs[FM3130_RTC_HOURS]; 486 fm3130->alarm_valid = 1;
487
488bad_alarm:
489
490 /* clock registers sanity chek */
491 tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
492 if (tmp > 59)
493 goto bad_clock;
494
495 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
496 if (tmp > 59)
497 goto bad_clock;
498
499 tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
500 if (tmp > 23)
501 goto bad_clock;
502
503 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x7);
504 if (tmp == 0 || tmp > 7)
505 goto bad_clock;
506
507 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
508 if (tmp == 0 || tmp > 31)
509 goto bad_clock;
510
511 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
512 if (tmp == 0 || tmp > 12)
513 goto bad_clock;
436 514
437 fm3130->data_valid = 1; 515 fm3130->data_valid = 1;
438 516
439exit_bad: 517bad_clock:
440 if (!fm3130->data_valid) 518
519 if (!fm3130->data_valid || !fm3130->alarm_valid)
441 dev_dbg(&client->dev, 520 dev_dbg(&client->dev,
442 "%s: %02x %02x %02x %02x %02x %02x %02x %02x" 521 "%s: %02x %02x %02x %02x %02x %02x %02x %02x"
443 "%02x %02x %02x %02x %02x %02x %02x\n", 522 "%02x %02x %02x %02x %02x %02x %02x\n",
diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
new file mode 100644
index 000000000000..2dd3c0163272
--- /dev/null
+++ b/drivers/rtc/rtc-imxdi.c
@@ -0,0 +1,519 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2010 Orex Computed Radiography
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/* based on rtc-mc13892.c */
16
17/*
18 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
19 * to implement a Linux RTC. Times and alarms are truncated to seconds.
20 * Since the RTC framework performs API locking via rtc->ops_lock the
21 * only simultaneous accesses we need to deal with is updating DryIce
22 * registers while servicing an alarm.
23 *
24 * Note that reading the DSR (DryIce Status Register) automatically clears
25 * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
26 * LP (Low Power) domain and set the WCF upon completion. Writes to the
27 * DIER (DryIce Interrupt Enable Register) are the only exception. These
28 * occur at normal bus speeds and do not set WCF. Periodic interrupts are
29 * not supported by the hardware.
30 */
31
32#include <linux/io.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/module.h>
36#include <linux/platform_device.h>
37#include <linux/rtc.h>
38#include <linux/workqueue.h>
39
40/* DryIce Register Definitions */
41
42#define DTCMR 0x00 /* Time Counter MSB Reg */
43#define DTCLR 0x04 /* Time Counter LSB Reg */
44
45#define DCAMR 0x08 /* Clock Alarm MSB Reg */
46#define DCALR 0x0c /* Clock Alarm LSB Reg */
47#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
48
49#define DCR 0x10 /* Control Reg */
50#define DCR_TCE (1 << 3) /* Time Counter Enable */
51
52#define DSR 0x14 /* Status Reg */
53#define DSR_WBF (1 << 10) /* Write Busy Flag */
54#define DSR_WNF (1 << 9) /* Write Next Flag */
55#define DSR_WCF (1 << 8) /* Write Complete Flag */
56#define DSR_WEF (1 << 7) /* Write Error Flag */
57#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
58#define DSR_NVF (1 << 1) /* Non-Valid Flag */
59#define DSR_SVF (1 << 0) /* Security Violation Flag */
60
61#define DIER 0x18 /* Interrupt Enable Reg */
62#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
63#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
64#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
65#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
66
67/**
68 * struct imxdi_dev - private imxdi rtc data
69 * @pdev: pionter to platform dev
70 * @rtc: pointer to rtc struct
71 * @ioaddr: IO registers pointer
72 * @irq: dryice normal interrupt
73 * @clk: input reference clock
74 * @dsr: copy of the DSR register
75 * @irq_lock: interrupt enable register (DIER) lock
76 * @write_wait: registers write complete queue
77 * @write_mutex: serialize registers write
78 * @work: schedule alarm work
79 */
80struct imxdi_dev {
81 struct platform_device *pdev;
82 struct rtc_device *rtc;
83 void __iomem *ioaddr;
84 int irq;
85 struct clk *clk;
86 u32 dsr;
87 spinlock_t irq_lock;
88 wait_queue_head_t write_wait;
89 struct mutex write_mutex;
90 struct work_struct work;
91};
92
93/*
94 * enable a dryice interrupt
95 */
96static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&imxdi->irq_lock, flags);
101 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
102 imxdi->ioaddr + DIER);
103 spin_unlock_irqrestore(&imxdi->irq_lock, flags);
104}
105
106/*
107 * disable a dryice interrupt
108 */
109static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
110{
111 unsigned long flags;
112
113 spin_lock_irqsave(&imxdi->irq_lock, flags);
114 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
115 imxdi->ioaddr + DIER);
116 spin_unlock_irqrestore(&imxdi->irq_lock, flags);
117}
118
119/*
120 * This function attempts to clear the dryice write-error flag.
121 *
122 * A dryice write error is similar to a bus fault and should not occur in
123 * normal operation. Clearing the flag requires another write, so the root
124 * cause of the problem may need to be fixed before the flag can be cleared.
125 */
126static void clear_write_error(struct imxdi_dev *imxdi)
127{
128 int cnt;
129
130 dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
131
132 /* clear the write error flag */
133 __raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
134
135 /* wait for it to take effect */
136 for (cnt = 0; cnt < 1000; cnt++) {
137 if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
138 return;
139 udelay(10);
140 }
141 dev_err(&imxdi->pdev->dev,
142 "ERROR: Cannot clear write-error flag!\n");
143}
144
145/*
146 * Write a dryice register and wait until it completes.
147 *
148 * This function uses interrupts to determine when the
149 * write has completed.
150 */
151static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
152{
153 int ret;
154 int rc = 0;
155
156 /* serialize register writes */
157 mutex_lock(&imxdi->write_mutex);
158
159 /* enable the write-complete interrupt */
160 di_int_enable(imxdi, DIER_WCIE);
161
162 imxdi->dsr = 0;
163
164 /* do the register write */
165 __raw_writel(val, imxdi->ioaddr + reg);
166
167 /* wait for the write to finish */
168 ret = wait_event_interruptible_timeout(imxdi->write_wait,
169 imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
170 if (ret < 0) {
171 rc = ret;
172 goto out;
173 } else if (ret == 0) {
174 dev_warn(&imxdi->pdev->dev,
175 "Write-wait timeout "
176 "val = 0x%08x reg = 0x%08x\n", val, reg);
177 }
178
179 /* check for write error */
180 if (imxdi->dsr & DSR_WEF) {
181 clear_write_error(imxdi);
182 rc = -EIO;
183 }
184
185out:
186 mutex_unlock(&imxdi->write_mutex);
187
188 return rc;
189}
190
191/*
192 * read the seconds portion of the current time from the dryice time counter
193 */
194static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
195{
196 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
197 unsigned long now;
198
199 now = __raw_readl(imxdi->ioaddr + DTCMR);
200 rtc_time_to_tm(now, tm);
201
202 return 0;
203}
204
205/*
206 * set the seconds portion of dryice time counter and clear the
207 * fractional part.
208 */
209static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
210{
211 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
212 int rc;
213
214 /* zero the fractional part first */
215 rc = di_write_wait(imxdi, 0, DTCLR);
216 if (rc == 0)
217 rc = di_write_wait(imxdi, secs, DTCMR);
218
219 return rc;
220}
221
222static int dryice_rtc_alarm_irq_enable(struct device *dev,
223 unsigned int enabled)
224{
225 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
226
227 if (enabled)
228 di_int_enable(imxdi, DIER_CAIE);
229 else
230 di_int_disable(imxdi, DIER_CAIE);
231
232 return 0;
233}
234
235/*
236 * read the seconds portion of the alarm register.
237 * the fractional part of the alarm register is always zero.
238 */
239static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
240{
241 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
242 u32 dcamr;
243
244 dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
245 rtc_time_to_tm(dcamr, &alarm->time);
246
247 /* alarm is enabled if the interrupt is enabled */
248 alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
249
250 /* don't allow the DSR read to mess up DSR_WCF */
251 mutex_lock(&imxdi->write_mutex);
252
253 /* alarm is pending if the alarm flag is set */
254 alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
255
256 mutex_unlock(&imxdi->write_mutex);
257
258 return 0;
259}
260
261/*
262 * set the seconds portion of dryice alarm register
263 */
264static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
265{
266 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
267 unsigned long now;
268 unsigned long alarm_time;
269 int rc;
270
271 rc = rtc_tm_to_time(&alarm->time, &alarm_time);
272 if (rc)
273 return rc;
274
275 /* don't allow setting alarm in the past */
276 now = __raw_readl(imxdi->ioaddr + DTCMR);
277 if (alarm_time < now)
278 return -EINVAL;
279
280 /* write the new alarm time */
281 rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
282 if (rc)
283 return rc;
284
285 if (alarm->enabled)
286 di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
287 else
288 di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
289
290 return 0;
291}
292
293static struct rtc_class_ops dryice_rtc_ops = {
294 .read_time = dryice_rtc_read_time,
295 .set_mmss = dryice_rtc_set_mmss,
296 .alarm_irq_enable = dryice_rtc_alarm_irq_enable,
297 .read_alarm = dryice_rtc_read_alarm,
298 .set_alarm = dryice_rtc_set_alarm,
299};
300
301/*
302 * dryice "normal" interrupt handler
303 */
304static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
305{
306 struct imxdi_dev *imxdi = dev_id;
307 u32 dsr, dier;
308 irqreturn_t rc = IRQ_NONE;
309
310 dier = __raw_readl(imxdi->ioaddr + DIER);
311
312 /* handle write complete and write error cases */
313 if ((dier & DIER_WCIE)) {
314 /*If the write wait queue is empty then there is no pending
315 operations. It means the interrupt is for DryIce -Security.
316 IRQ must be returned as none.*/
317 if (list_empty_careful(&imxdi->write_wait.task_list))
318 return rc;
319
320 /* DSR_WCF clears itself on DSR read */
321 dsr = __raw_readl(imxdi->ioaddr + DSR);
322 if ((dsr & (DSR_WCF | DSR_WEF))) {
323 /* mask the interrupt */
324 di_int_disable(imxdi, DIER_WCIE);
325
326 /* save the dsr value for the wait queue */
327 imxdi->dsr |= dsr;
328
329 wake_up_interruptible(&imxdi->write_wait);
330 rc = IRQ_HANDLED;
331 }
332 }
333
334 /* handle the alarm case */
335 if ((dier & DIER_CAIE)) {
336 /* DSR_WCF clears itself on DSR read */
337 dsr = __raw_readl(imxdi->ioaddr + DSR);
338 if (dsr & DSR_CAF) {
339 /* mask the interrupt */
340 di_int_disable(imxdi, DIER_CAIE);
341
342 /* finish alarm in user context */
343 schedule_work(&imxdi->work);
344 rc = IRQ_HANDLED;
345 }
346 }
347 return rc;
348}
349
350/*
351 * post the alarm event from user context so it can sleep
352 * on the write completion.
353 */
354static void dryice_work(struct work_struct *work)
355{
356 struct imxdi_dev *imxdi = container_of(work,
357 struct imxdi_dev, work);
358
359 /* dismiss the interrupt (ignore error) */
360 di_write_wait(imxdi, DSR_CAF, DSR);
361
362 /* pass the alarm event to the rtc framework. */
363 rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
364}
365
366/*
367 * probe for dryice rtc device
368 */
369static int dryice_rtc_probe(struct platform_device *pdev)
370{
371 struct resource *res;
372 struct imxdi_dev *imxdi;
373 int rc;
374
375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
376 if (!res)
377 return -ENODEV;
378
379 imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
380 if (!imxdi)
381 return -ENOMEM;
382
383 imxdi->pdev = pdev;
384
385 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
386 pdev->name))
387 return -EBUSY;
388
389 imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
390 resource_size(res));
391 if (imxdi->ioaddr == NULL)
392 return -ENOMEM;
393
394 imxdi->irq = platform_get_irq(pdev, 0);
395 if (imxdi->irq < 0)
396 return imxdi->irq;
397
398 init_waitqueue_head(&imxdi->write_wait);
399
400 INIT_WORK(&imxdi->work, dryice_work);
401
402 mutex_init(&imxdi->write_mutex);
403
404 imxdi->clk = clk_get(&pdev->dev, NULL);
405 if (IS_ERR(imxdi->clk))
406 return PTR_ERR(imxdi->clk);
407 clk_enable(imxdi->clk);
408
409 /*
410 * Initialize dryice hardware
411 */
412
413 /* mask all interrupts */
414 __raw_writel(0, imxdi->ioaddr + DIER);
415
416 rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
417 IRQF_SHARED, pdev->name, imxdi);
418 if (rc) {
419 dev_warn(&pdev->dev, "interrupt not available.\n");
420 goto err;
421 }
422
423 /* put dryice into valid state */
424 if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
425 rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
426 if (rc)
427 goto err;
428 }
429
430 /* initialize alarm */
431 rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
432 if (rc)
433 goto err;
434 rc = di_write_wait(imxdi, 0, DCALR);
435 if (rc)
436 goto err;
437
438 /* clear alarm flag */
439 if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
440 rc = di_write_wait(imxdi, DSR_CAF, DSR);
441 if (rc)
442 goto err;
443 }
444
445 /* the timer won't count if it has never been written to */
446 if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
447 rc = di_write_wait(imxdi, 0, DTCMR);
448 if (rc)
449 goto err;
450 }
451
452 /* start keeping time */
453 if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
454 rc = di_write_wait(imxdi,
455 __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
456 DCR);
457 if (rc)
458 goto err;
459 }
460
461 platform_set_drvdata(pdev, imxdi);
462 imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
463 &dryice_rtc_ops, THIS_MODULE);
464 if (IS_ERR(imxdi->rtc)) {
465 rc = PTR_ERR(imxdi->rtc);
466 goto err;
467 }
468
469 return 0;
470
471err:
472 clk_disable(imxdi->clk);
473 clk_put(imxdi->clk);
474
475 return rc;
476}
477
478static int __devexit dryice_rtc_remove(struct platform_device *pdev)
479{
480 struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
481
482 flush_work(&imxdi->work);
483
484 /* mask all interrupts */
485 __raw_writel(0, imxdi->ioaddr + DIER);
486
487 rtc_device_unregister(imxdi->rtc);
488
489 clk_disable(imxdi->clk);
490 clk_put(imxdi->clk);
491
492 return 0;
493}
494
495static struct platform_driver dryice_rtc_driver = {
496 .driver = {
497 .name = "imxdi_rtc",
498 .owner = THIS_MODULE,
499 },
500 .remove = __devexit_p(dryice_rtc_remove),
501};
502
503static int __init dryice_rtc_init(void)
504{
505 return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
506}
507
508static void __exit dryice_rtc_exit(void)
509{
510 platform_driver_unregister(&dryice_rtc_driver);
511}
512
513module_init(dryice_rtc_init);
514module_exit(dryice_rtc_exit);
515
516MODULE_AUTHOR("Freescale Semiconductor, Inc.");
517MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
518MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
519MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c
new file mode 100644
index 000000000000..ddbc797ea6cd
--- /dev/null
+++ b/drivers/rtc/rtc-isl12022.c
@@ -0,0 +1,327 @@
1/*
2 * An I2C driver for the Intersil ISL 12022
3 *
4 * Author: Roman Fietze <roman.fietze@telemotive.de>
5 *
6 * Based on the Philips PCF8563 RTC
7 * by Alessandro Zummo <a.zummo@towertech.it>.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
12 */
13
14#include <linux/i2c.h>
15#include <linux/bcd.h>
16#include <linux/rtc.h>
17#include <linux/slab.h>
18
19#define DRV_VERSION "0.1"
20
21/* ISL register offsets */
22#define ISL12022_REG_SC 0x00
23#define ISL12022_REG_MN 0x01
24#define ISL12022_REG_HR 0x02
25#define ISL12022_REG_DT 0x03
26#define ISL12022_REG_MO 0x04
27#define ISL12022_REG_YR 0x05
28#define ISL12022_REG_DW 0x06
29
30#define ISL12022_REG_SR 0x07
31#define ISL12022_REG_INT 0x08
32
33/* ISL register bits */
34#define ISL12022_HR_MIL (1 << 7) /* military or 24 hour time */
35
36#define ISL12022_SR_LBAT85 (1 << 2)
37#define ISL12022_SR_LBAT75 (1 << 1)
38
39#define ISL12022_INT_WRTC (1 << 6)
40
41
42static struct i2c_driver isl12022_driver;
43
44struct isl12022 {
45 struct rtc_device *rtc;
46
47 bool write_enabled; /* true if write enable is set */
48};
49
50
51static int isl12022_read_regs(struct i2c_client *client, uint8_t reg,
52 uint8_t *data, size_t n)
53{
54 struct i2c_msg msgs[] = {
55 {
56 .addr = client->addr,
57 .flags = 0,
58 .len = 1,
59 .buf = data
60 }, /* setup read ptr */
61 {
62 .addr = client->addr,
63 .flags = I2C_M_RD,
64 .len = n,
65 .buf = data
66 }
67 };
68
69 int ret;
70
71 data[0] = reg;
72 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
73 if (ret != ARRAY_SIZE(msgs)) {
74 dev_err(&client->dev, "%s: read error, ret=%d\n",
75 __func__, ret);
76 return -EIO;
77 }
78
79 return 0;
80}
81
82
83static int isl12022_write_reg(struct i2c_client *client,
84 uint8_t reg, uint8_t val)
85{
86 uint8_t data[2] = { reg, val };
87 int err;
88
89 err = i2c_master_send(client, data, sizeof(data));
90 if (err != sizeof(data)) {
91 dev_err(&client->dev,
92 "%s: err=%d addr=%02x, data=%02x\n",
93 __func__, err, data[0], data[1]);
94 return -EIO;
95 }
96
97 return 0;
98}
99
100
101/*
102 * In the routines that deal directly with the isl12022 hardware, we use
103 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
104 */
105static int isl12022_get_datetime(struct i2c_client *client, struct rtc_time *tm)
106{
107 uint8_t buf[ISL12022_REG_INT + 1];
108 int ret;
109
110 ret = isl12022_read_regs(client, ISL12022_REG_SC, buf, sizeof(buf));
111 if (ret)
112 return ret;
113
114 if (buf[ISL12022_REG_SR] & (ISL12022_SR_LBAT85 | ISL12022_SR_LBAT75)) {
115 dev_warn(&client->dev,
116 "voltage dropped below %u%%, "
117 "date and time is not reliable.\n",
118 buf[ISL12022_REG_SR] & ISL12022_SR_LBAT85 ? 85 : 75);
119 }
120
121 dev_dbg(&client->dev,
122 "%s: raw data is sec=%02x, min=%02x, hr=%02x, "
123 "mday=%02x, mon=%02x, year=%02x, wday=%02x, "
124 "sr=%02x, int=%02x",
125 __func__,
126 buf[ISL12022_REG_SC],
127 buf[ISL12022_REG_MN],
128 buf[ISL12022_REG_HR],
129 buf[ISL12022_REG_DT],
130 buf[ISL12022_REG_MO],
131 buf[ISL12022_REG_YR],
132 buf[ISL12022_REG_DW],
133 buf[ISL12022_REG_SR],
134 buf[ISL12022_REG_INT]);
135
136 tm->tm_sec = bcd2bin(buf[ISL12022_REG_SC] & 0x7F);
137 tm->tm_min = bcd2bin(buf[ISL12022_REG_MN] & 0x7F);
138 tm->tm_hour = bcd2bin(buf[ISL12022_REG_HR] & 0x3F);
139 tm->tm_mday = bcd2bin(buf[ISL12022_REG_DT] & 0x3F);
140 tm->tm_wday = buf[ISL12022_REG_DW] & 0x07;
141 tm->tm_mon = bcd2bin(buf[ISL12022_REG_MO] & 0x1F) - 1;
142 tm->tm_year = bcd2bin(buf[ISL12022_REG_YR]) + 100;
143
144 dev_dbg(&client->dev, "%s: secs=%d, mins=%d, hours=%d, "
145 "mday=%d, mon=%d, year=%d, wday=%d\n",
146 __func__,
147 tm->tm_sec, tm->tm_min, tm->tm_hour,
148 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
149
150 /* The clock can give out invalid datetime, but we cannot return
151 * -EINVAL otherwise hwclock will refuse to set the time on bootup. */
152 if (rtc_valid_tm(tm) < 0)
153 dev_err(&client->dev, "retrieved date and time is invalid.\n");
154
155 return 0;
156}
157
158static int isl12022_set_datetime(struct i2c_client *client, struct rtc_time *tm)
159{
160 struct isl12022 *isl12022 = i2c_get_clientdata(client);
161 size_t i;
162 int ret;
163 uint8_t buf[ISL12022_REG_DW + 1];
164
165 dev_dbg(&client->dev, "%s: secs=%d, mins=%d, hours=%d, "
166 "mday=%d, mon=%d, year=%d, wday=%d\n",
167 __func__,
168 tm->tm_sec, tm->tm_min, tm->tm_hour,
169 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
170
171 if (!isl12022->write_enabled) {
172
173 ret = isl12022_read_regs(client, ISL12022_REG_INT, buf, 1);
174 if (ret)
175 return ret;
176
177 /* Check if WRTC (write rtc enable) is set factory default is
178 * 0 (not set) */
179 if (!(buf[0] & ISL12022_INT_WRTC)) {
180 dev_info(&client->dev,
181 "init write enable and 24 hour format\n");
182
183 /* Set the write enable bit. */
184 ret = isl12022_write_reg(client,
185 ISL12022_REG_INT,
186 buf[0] | ISL12022_INT_WRTC);
187 if (ret)
188 return ret;
189
190 /* Write to any RTC register to start RTC, we use the
191 * HR register, setting the MIL bit to use the 24 hour
192 * format. */
193 ret = isl12022_read_regs(client, ISL12022_REG_HR,
194 buf, 1);
195 if (ret)
196 return ret;
197
198 ret = isl12022_write_reg(client,
199 ISL12022_REG_HR,
200 buf[0] | ISL12022_HR_MIL);
201 if (ret)
202 return ret;
203 }
204
205 isl12022->write_enabled = 1;
206 }
207
208 /* hours, minutes and seconds */
209 buf[ISL12022_REG_SC] = bin2bcd(tm->tm_sec);
210 buf[ISL12022_REG_MN] = bin2bcd(tm->tm_min);
211 buf[ISL12022_REG_HR] = bin2bcd(tm->tm_hour) | ISL12022_HR_MIL;
212
213 buf[ISL12022_REG_DT] = bin2bcd(tm->tm_mday);
214
215 /* month, 1 - 12 */
216 buf[ISL12022_REG_MO] = bin2bcd(tm->tm_mon + 1);
217
218 /* year and century */
219 buf[ISL12022_REG_YR] = bin2bcd(tm->tm_year % 100);
220
221 buf[ISL12022_REG_DW] = tm->tm_wday & 0x07;
222
223 /* write register's data */
224 for (i = 0; i < ARRAY_SIZE(buf); i++) {
225 ret = isl12022_write_reg(client, ISL12022_REG_SC + i,
226 buf[ISL12022_REG_SC + i]);
227 if (ret)
228 return -EIO;
229 };
230
231 return 0;
232}
233
234static int isl12022_rtc_read_time(struct device *dev, struct rtc_time *tm)
235{
236 return isl12022_get_datetime(to_i2c_client(dev), tm);
237}
238
239static int isl12022_rtc_set_time(struct device *dev, struct rtc_time *tm)
240{
241 return isl12022_set_datetime(to_i2c_client(dev), tm);
242}
243
244static const struct rtc_class_ops isl12022_rtc_ops = {
245 .read_time = isl12022_rtc_read_time,
246 .set_time = isl12022_rtc_set_time,
247};
248
249static int isl12022_probe(struct i2c_client *client,
250 const struct i2c_device_id *id)
251{
252 struct isl12022 *isl12022;
253
254 int ret = 0;
255
256 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
257 return -ENODEV;
258
259 isl12022 = kzalloc(sizeof(struct isl12022), GFP_KERNEL);
260 if (!isl12022)
261 return -ENOMEM;
262
263 dev_dbg(&client->dev, "chip found, driver version " DRV_VERSION "\n");
264
265 i2c_set_clientdata(client, isl12022);
266
267 isl12022->rtc = rtc_device_register(isl12022_driver.driver.name,
268 &client->dev,
269 &isl12022_rtc_ops,
270 THIS_MODULE);
271
272 if (IS_ERR(isl12022->rtc)) {
273 ret = PTR_ERR(isl12022->rtc);
274 goto exit_kfree;
275 }
276
277 return 0;
278
279exit_kfree:
280 kfree(isl12022);
281
282 return ret;
283}
284
285static int isl12022_remove(struct i2c_client *client)
286{
287 struct isl12022 *isl12022 = i2c_get_clientdata(client);
288
289 rtc_device_unregister(isl12022->rtc);
290 kfree(isl12022);
291
292 return 0;
293}
294
295static const struct i2c_device_id isl12022_id[] = {
296 { "isl12022", 0 },
297 { "rtc8564", 0 },
298 { }
299};
300MODULE_DEVICE_TABLE(i2c, isl12022_id);
301
302static struct i2c_driver isl12022_driver = {
303 .driver = {
304 .name = "rtc-isl12022",
305 },
306 .probe = isl12022_probe,
307 .remove = isl12022_remove,
308 .id_table = isl12022_id,
309};
310
311static int __init isl12022_init(void)
312{
313 return i2c_add_driver(&isl12022_driver);
314}
315
316static void __exit isl12022_exit(void)
317{
318 i2c_del_driver(&isl12022_driver);
319}
320
321module_init(isl12022_init);
322module_exit(isl12022_exit);
323
324MODULE_AUTHOR("roman.fietze@telemotive.de");
325MODULE_DESCRIPTION("ISL 12022 RTC driver");
326MODULE_LICENSE("GPL");
327MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
new file mode 100644
index 000000000000..2e16f72c9056
--- /dev/null
+++ b/drivers/rtc/rtc-jz4740.c
@@ -0,0 +1,380 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
4 * JZ4740 SoC RTC driver
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 675 Mass Ave, Cambridge, MA 02139, USA.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/rtc.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23
24#define JZ_REG_RTC_CTRL 0x00
25#define JZ_REG_RTC_SEC 0x04
26#define JZ_REG_RTC_SEC_ALARM 0x08
27#define JZ_REG_RTC_REGULATOR 0x0C
28#define JZ_REG_RTC_HIBERNATE 0x20
29#define JZ_REG_RTC_SCRATCHPAD 0x34
30
31#define JZ_RTC_CTRL_WRDY BIT(7)
32#define JZ_RTC_CTRL_1HZ BIT(6)
33#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
34#define JZ_RTC_CTRL_AF BIT(4)
35#define JZ_RTC_CTRL_AF_IRQ BIT(3)
36#define JZ_RTC_CTRL_AE BIT(2)
37#define JZ_RTC_CTRL_ENABLE BIT(0)
38
39struct jz4740_rtc {
40 struct resource *mem;
41 void __iomem *base;
42
43 struct rtc_device *rtc;
44
45 unsigned int irq;
46
47 spinlock_t lock;
48};
49
50static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
51{
52 return readl(rtc->base + reg);
53}
54
55static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
56{
57 uint32_t ctrl;
58 int timeout = 1000;
59
60 do {
61 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
62 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
63
64 return timeout ? 0 : -EIO;
65}
66
67static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
68 uint32_t val)
69{
70 int ret;
71 ret = jz4740_rtc_wait_write_ready(rtc);
72 if (ret == 0)
73 writel(val, rtc->base + reg);
74
75 return ret;
76}
77
78static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
79 bool set)
80{
81 int ret;
82 unsigned long flags;
83 uint32_t ctrl;
84
85 spin_lock_irqsave(&rtc->lock, flags);
86
87 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
88
89 /* Don't clear interrupt flags by accident */
90 ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
91
92 if (set)
93 ctrl |= mask;
94 else
95 ctrl &= ~mask;
96
97 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
98
99 spin_unlock_irqrestore(&rtc->lock, flags);
100
101 return ret;
102}
103
104static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
105{
106 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
107 uint32_t secs, secs2;
108 int timeout = 5;
109
110 /* If the seconds register is read while it is updated, it can contain a
111 * bogus value. This can be avoided by making sure that two consecutive
112 * reads have the same value.
113 */
114 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
115 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
116
117 while (secs != secs2 && --timeout) {
118 secs = secs2;
119 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
120 }
121
122 if (timeout == 0)
123 return -EIO;
124
125 rtc_time_to_tm(secs, time);
126
127 return rtc_valid_tm(time);
128}
129
130static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
131{
132 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
133
134 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
135}
136
137static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
138{
139 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
140 uint32_t secs;
141 uint32_t ctrl;
142
143 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
144
145 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
146
147 alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
148 alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
149
150 rtc_time_to_tm(secs, &alrm->time);
151
152 return rtc_valid_tm(&alrm->time);
153}
154
155static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
156{
157 int ret;
158 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
159 unsigned long secs;
160
161 rtc_tm_to_time(&alrm->time, &secs);
162
163 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
164 if (!ret)
165 ret = jz4740_rtc_ctrl_set_bits(rtc,
166 JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
167
168 return ret;
169}
170
171static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
172{
173 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
174 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
175}
176
177static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
178{
179 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
180 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
181}
182
183static struct rtc_class_ops jz4740_rtc_ops = {
184 .read_time = jz4740_rtc_read_time,
185 .set_mmss = jz4740_rtc_set_mmss,
186 .read_alarm = jz4740_rtc_read_alarm,
187 .set_alarm = jz4740_rtc_set_alarm,
188 .update_irq_enable = jz4740_rtc_update_irq_enable,
189 .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
190};
191
192static irqreturn_t jz4740_rtc_irq(int irq, void *data)
193{
194 struct jz4740_rtc *rtc = data;
195 uint32_t ctrl;
196 unsigned long events = 0;
197
198 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
199
200 if (ctrl & JZ_RTC_CTRL_1HZ)
201 events |= (RTC_UF | RTC_IRQF);
202
203 if (ctrl & JZ_RTC_CTRL_AF)
204 events |= (RTC_AF | RTC_IRQF);
205
206 rtc_update_irq(rtc->rtc, 1, events);
207
208 jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
209
210 return IRQ_HANDLED;
211}
212
213void jz4740_rtc_poweroff(struct device *dev)
214{
215 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
216 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
217}
218EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
219
220static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
221{
222 int ret;
223 struct jz4740_rtc *rtc;
224 uint32_t scratchpad;
225
226 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
227 if (!rtc)
228 return -ENOMEM;
229
230 rtc->irq = platform_get_irq(pdev, 0);
231 if (rtc->irq < 0) {
232 ret = -ENOENT;
233 dev_err(&pdev->dev, "Failed to get platform irq\n");
234 goto err_free;
235 }
236
237 rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
238 if (!rtc->mem) {
239 ret = -ENOENT;
240 dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
241 goto err_free;
242 }
243
244 rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
245 pdev->name);
246 if (!rtc->mem) {
247 ret = -EBUSY;
248 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
249 goto err_free;
250 }
251
252 rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
253 if (!rtc->base) {
254 ret = -EBUSY;
255 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
256 goto err_release_mem_region;
257 }
258
259 spin_lock_init(&rtc->lock);
260
261 platform_set_drvdata(pdev, rtc);
262
263 device_init_wakeup(&pdev->dev, 1);
264
265 rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
266 THIS_MODULE);
267 if (IS_ERR(rtc->rtc)) {
268 ret = PTR_ERR(rtc->rtc);
269 dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
270 goto err_iounmap;
271 }
272
273 ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
274 pdev->name, rtc);
275 if (ret) {
276 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
277 goto err_unregister_rtc;
278 }
279
280 scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
281 if (scratchpad != 0x12345678) {
282 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
283 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
284 if (ret) {
285 dev_err(&pdev->dev, "Could not write write to RTC registers\n");
286 goto err_free_irq;
287 }
288 }
289
290 return 0;
291
292err_free_irq:
293 free_irq(rtc->irq, rtc);
294err_unregister_rtc:
295 rtc_device_unregister(rtc->rtc);
296err_iounmap:
297 platform_set_drvdata(pdev, NULL);
298 iounmap(rtc->base);
299err_release_mem_region:
300 release_mem_region(rtc->mem->start, resource_size(rtc->mem));
301err_free:
302 kfree(rtc);
303
304 return ret;
305}
306
307static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
308{
309 struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
310
311 free_irq(rtc->irq, rtc);
312
313 rtc_device_unregister(rtc->rtc);
314
315 iounmap(rtc->base);
316 release_mem_region(rtc->mem->start, resource_size(rtc->mem));
317
318 kfree(rtc);
319
320 platform_set_drvdata(pdev, NULL);
321
322 return 0;
323}
324
325
326#ifdef CONFIG_PM
327static int jz4740_rtc_suspend(struct device *dev)
328{
329 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
330
331 if (device_may_wakeup(dev))
332 enable_irq_wake(rtc->irq);
333 return 0;
334}
335
336static int jz4740_rtc_resume(struct device *dev)
337{
338 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
339
340 if (device_may_wakeup(dev))
341 disable_irq_wake(rtc->irq);
342 return 0;
343}
344
345static const struct dev_pm_ops jz4740_pm_ops = {
346 .suspend = jz4740_rtc_suspend,
347 .resume = jz4740_rtc_resume,
348};
349#define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
350
351#else
352#define JZ4740_RTC_PM_OPS NULL
353#endif /* CONFIG_PM */
354
355struct platform_driver jz4740_rtc_driver = {
356 .probe = jz4740_rtc_probe,
357 .remove = __devexit_p(jz4740_rtc_remove),
358 .driver = {
359 .name = "jz4740-rtc",
360 .owner = THIS_MODULE,
361 .pm = JZ4740_RTC_PM_OPS,
362 },
363};
364
365static int __init jz4740_rtc_init(void)
366{
367 return platform_driver_register(&jz4740_rtc_driver);
368}
369module_init(jz4740_rtc_init);
370
371static void __exit jz4740_rtc_exit(void)
372{
373 platform_driver_unregister(&jz4740_rtc_driver);
374}
375module_exit(jz4740_rtc_exit);
376
377MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
378MODULE_LICENSE("GPL");
379MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
380MODULE_ALIAS("platform:jz4740-rtc");
diff --git a/drivers/rtc/rtc-lpc32xx.c b/drivers/rtc/rtc-lpc32xx.c
new file mode 100644
index 000000000000..ec8701ce99f9
--- /dev/null
+++ b/drivers/rtc/rtc-lpc32xx.c
@@ -0,0 +1,414 @@
1/*
2 * Copyright (C) 2010 NXP Semiconductors
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/spinlock.h>
19#include <linux/rtc.h>
20#include <linux/slab.h>
21#include <linux/io.h>
22
23/*
24 * Clock and Power control register offsets
25 */
26#define LPC32XX_RTC_UCOUNT 0x00
27#define LPC32XX_RTC_DCOUNT 0x04
28#define LPC32XX_RTC_MATCH0 0x08
29#define LPC32XX_RTC_MATCH1 0x0C
30#define LPC32XX_RTC_CTRL 0x10
31#define LPC32XX_RTC_INTSTAT 0x14
32#define LPC32XX_RTC_KEY 0x18
33#define LPC32XX_RTC_SRAM 0x80
34
35#define LPC32XX_RTC_CTRL_MATCH0 (1 << 0)
36#define LPC32XX_RTC_CTRL_MATCH1 (1 << 1)
37#define LPC32XX_RTC_CTRL_ONSW_MATCH0 (1 << 2)
38#define LPC32XX_RTC_CTRL_ONSW_MATCH1 (1 << 3)
39#define LPC32XX_RTC_CTRL_SW_RESET (1 << 4)
40#define LPC32XX_RTC_CTRL_CNTR_DIS (1 << 6)
41#define LPC32XX_RTC_CTRL_ONSW_FORCE_HI (1 << 7)
42
43#define LPC32XX_RTC_INTSTAT_MATCH0 (1 << 0)
44#define LPC32XX_RTC_INTSTAT_MATCH1 (1 << 1)
45#define LPC32XX_RTC_INTSTAT_ONSW (1 << 2)
46
47#define LPC32XX_RTC_KEY_ONSW_LOADVAL 0xB5C13F27
48
49#define RTC_NAME "rtc-lpc32xx"
50
51#define rtc_readl(dev, reg) \
52 __raw_readl((dev)->rtc_base + (reg))
53#define rtc_writel(dev, reg, val) \
54 __raw_writel((val), (dev)->rtc_base + (reg))
55
56struct lpc32xx_rtc {
57 void __iomem *rtc_base;
58 int irq;
59 unsigned char alarm_enabled;
60 struct rtc_device *rtc;
61 spinlock_t lock;
62};
63
64static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
65{
66 unsigned long elapsed_sec;
67 struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
68
69 elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
70 rtc_time_to_tm(elapsed_sec, time);
71
72 return rtc_valid_tm(time);
73}
74
75static int lpc32xx_rtc_set_mmss(struct device *dev, unsigned long secs)
76{
77 struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
78 u32 tmp;
79
80 spin_lock_irq(&rtc->lock);
81
82 /* RTC must be disabled during count update */
83 tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
84 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
85 rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
86 rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
87 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
88
89 spin_unlock_irq(&rtc->lock);
90
91 return 0;
92}
93
94static int lpc32xx_rtc_read_alarm(struct device *dev,
95 struct rtc_wkalrm *wkalrm)
96{
97 struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
98
99 rtc_time_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
100 wkalrm->enabled = rtc->alarm_enabled;
101 wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
102 LPC32XX_RTC_INTSTAT_MATCH0);
103
104 return rtc_valid_tm(&wkalrm->time);
105}
106
107static int lpc32xx_rtc_set_alarm(struct device *dev,
108 struct rtc_wkalrm *wkalrm)
109{
110 struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
111 unsigned long alarmsecs;
112 u32 tmp;
113 int ret;
114
115 ret = rtc_tm_to_time(&wkalrm->time, &alarmsecs);
116 if (ret < 0) {
117 dev_warn(dev, "Failed to convert time: %d\n", ret);
118 return ret;
119 }
120
121 spin_lock_irq(&rtc->lock);
122
123 /* Disable alarm during update */
124 tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
125 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
126
127 rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
128
129 rtc->alarm_enabled = wkalrm->enabled;
130 if (wkalrm->enabled) {
131 rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
132 LPC32XX_RTC_INTSTAT_MATCH0);
133 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
134 LPC32XX_RTC_CTRL_MATCH0);
135 }
136
137 spin_unlock_irq(&rtc->lock);
138
139 return 0;
140}
141
142static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
143 unsigned int enabled)
144{
145 struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
146 u32 tmp;
147
148 spin_lock_irq(&rtc->lock);
149 tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
150
151 if (enabled) {
152 rtc->alarm_enabled = 1;
153 tmp |= LPC32XX_RTC_CTRL_MATCH0;
154 } else {
155 rtc->alarm_enabled = 0;
156 tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
157 }
158
159 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
160 spin_unlock_irq(&rtc->lock);
161
162 return 0;
163}
164
165static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
166{
167 struct lpc32xx_rtc *rtc = dev;
168
169 spin_lock(&rtc->lock);
170
171 /* Disable alarm interrupt */
172 rtc_writel(rtc, LPC32XX_RTC_CTRL,
173 rtc_readl(rtc, LPC32XX_RTC_CTRL) &
174 ~LPC32XX_RTC_CTRL_MATCH0);
175 rtc->alarm_enabled = 0;
176
177 /*
178 * Write a large value to the match value so the RTC won't
179 * keep firing the match status
180 */
181 rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
182 rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
183
184 spin_unlock(&rtc->lock);
185
186 rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
187
188 return IRQ_HANDLED;
189}
190
191static const struct rtc_class_ops lpc32xx_rtc_ops = {
192 .read_time = lpc32xx_rtc_read_time,
193 .set_mmss = lpc32xx_rtc_set_mmss,
194 .read_alarm = lpc32xx_rtc_read_alarm,
195 .set_alarm = lpc32xx_rtc_set_alarm,
196 .alarm_irq_enable = lpc32xx_rtc_alarm_irq_enable,
197};
198
199static int __devinit lpc32xx_rtc_probe(struct platform_device *pdev)
200{
201 struct resource *res;
202 struct lpc32xx_rtc *rtc;
203 resource_size_t size;
204 int rtcirq;
205 u32 tmp;
206
207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 if (!res) {
209 dev_err(&pdev->dev, "Can't get memory resource\n");
210 return -ENOENT;
211 }
212
213 rtcirq = platform_get_irq(pdev, 0);
214 if (rtcirq < 0 || rtcirq >= NR_IRQS) {
215 dev_warn(&pdev->dev, "Can't get interrupt resource\n");
216 rtcirq = -1;
217 }
218
219 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
220 if (unlikely(!rtc)) {
221 dev_err(&pdev->dev, "Can't allocate memory\n");
222 return -ENOMEM;
223 }
224 rtc->irq = rtcirq;
225
226 size = resource_size(res);
227
228 if (!devm_request_mem_region(&pdev->dev, res->start, size,
229 pdev->name)) {
230 dev_err(&pdev->dev, "RTC registers are not free\n");
231 return -EBUSY;
232 }
233
234 rtc->rtc_base = devm_ioremap(&pdev->dev, res->start, size);
235 if (!rtc->rtc_base) {
236 dev_err(&pdev->dev, "Can't map memory\n");
237 return -ENOMEM;
238 }
239
240 spin_lock_init(&rtc->lock);
241
242 /*
243 * The RTC is on a seperate power domain and can keep it's state
244 * across a chip power cycle. If the RTC has never been previously
245 * setup, then set it up now for the first time.
246 */
247 tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
248 if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
249 tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
250 LPC32XX_RTC_CTRL_CNTR_DIS |
251 LPC32XX_RTC_CTRL_MATCH0 |
252 LPC32XX_RTC_CTRL_MATCH1 |
253 LPC32XX_RTC_CTRL_ONSW_MATCH0 |
254 LPC32XX_RTC_CTRL_ONSW_MATCH1 |
255 LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
256 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
257
258 /* Clear latched interrupt states */
259 rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
260 rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
261 LPC32XX_RTC_INTSTAT_MATCH0 |
262 LPC32XX_RTC_INTSTAT_MATCH1 |
263 LPC32XX_RTC_INTSTAT_ONSW);
264
265 /* Write key value to RTC so it won't reload on reset */
266 rtc_writel(rtc, LPC32XX_RTC_KEY,
267 LPC32XX_RTC_KEY_ONSW_LOADVAL);
268 } else {
269 rtc_writel(rtc, LPC32XX_RTC_CTRL,
270 tmp & ~LPC32XX_RTC_CTRL_MATCH0);
271 }
272
273 platform_set_drvdata(pdev, rtc);
274
275 rtc->rtc = rtc_device_register(RTC_NAME, &pdev->dev, &lpc32xx_rtc_ops,
276 THIS_MODULE);
277 if (IS_ERR(rtc->rtc)) {
278 dev_err(&pdev->dev, "Can't get RTC\n");
279 platform_set_drvdata(pdev, NULL);
280 return PTR_ERR(rtc->rtc);
281 }
282
283 /*
284 * IRQ is enabled after device registration in case alarm IRQ
285 * is pending upon suspend exit.
286 */
287 if (rtc->irq >= 0) {
288 if (devm_request_irq(&pdev->dev, rtc->irq,
289 lpc32xx_rtc_alarm_interrupt,
290 IRQF_DISABLED, pdev->name, rtc) < 0) {
291 dev_warn(&pdev->dev, "Can't request interrupt.\n");
292 rtc->irq = -1;
293 } else {
294 device_init_wakeup(&pdev->dev, 1);
295 }
296 }
297
298 return 0;
299}
300
301static int __devexit lpc32xx_rtc_remove(struct platform_device *pdev)
302{
303 struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
304
305 if (rtc->irq >= 0)
306 device_init_wakeup(&pdev->dev, 0);
307
308 platform_set_drvdata(pdev, NULL);
309 rtc_device_unregister(rtc->rtc);
310
311 return 0;
312}
313
314#ifdef CONFIG_PM
315static int lpc32xx_rtc_suspend(struct device *dev)
316{
317 struct platform_device *pdev = to_platform_device(dev);
318 struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
319
320 if (rtc->irq >= 0) {
321 if (device_may_wakeup(&pdev->dev))
322 enable_irq_wake(rtc->irq);
323 else
324 disable_irq_wake(rtc->irq);
325 }
326
327 return 0;
328}
329
330static int lpc32xx_rtc_resume(struct device *dev)
331{
332 struct platform_device *pdev = to_platform_device(dev);
333 struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
334
335 if (rtc->irq >= 0 && device_may_wakeup(&pdev->dev))
336 disable_irq_wake(rtc->irq);
337
338 return 0;
339}
340
341/* Unconditionally disable the alarm */
342static int lpc32xx_rtc_freeze(struct device *dev)
343{
344 struct platform_device *pdev = to_platform_device(dev);
345 struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
346
347 spin_lock_irq(&rtc->lock);
348
349 rtc_writel(rtc, LPC32XX_RTC_CTRL,
350 rtc_readl(rtc, LPC32XX_RTC_CTRL) &
351 ~LPC32XX_RTC_CTRL_MATCH0);
352
353 spin_unlock_irq(&rtc->lock);
354
355 return 0;
356}
357
358static int lpc32xx_rtc_thaw(struct device *dev)
359{
360 struct platform_device *pdev = to_platform_device(dev);
361 struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
362
363 if (rtc->alarm_enabled) {
364 spin_lock_irq(&rtc->lock);
365
366 rtc_writel(rtc, LPC32XX_RTC_CTRL,
367 rtc_readl(rtc, LPC32XX_RTC_CTRL) |
368 LPC32XX_RTC_CTRL_MATCH0);
369
370 spin_unlock_irq(&rtc->lock);
371 }
372
373 return 0;
374}
375
376static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
377 .suspend = lpc32xx_rtc_suspend,
378 .resume = lpc32xx_rtc_resume,
379 .freeze = lpc32xx_rtc_freeze,
380 .thaw = lpc32xx_rtc_thaw,
381 .restore = lpc32xx_rtc_resume
382};
383
384#define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
385#else
386#define LPC32XX_RTC_PM_OPS NULL
387#endif
388
389static struct platform_driver lpc32xx_rtc_driver = {
390 .probe = lpc32xx_rtc_probe,
391 .remove = __devexit_p(lpc32xx_rtc_remove),
392 .driver = {
393 .name = RTC_NAME,
394 .owner = THIS_MODULE,
395 .pm = LPC32XX_RTC_PM_OPS
396 },
397};
398
399static int __init lpc32xx_rtc_init(void)
400{
401 return platform_driver_register(&lpc32xx_rtc_driver);
402}
403module_init(lpc32xx_rtc_init);
404
405static void __exit lpc32xx_rtc_exit(void)
406{
407 platform_driver_unregister(&lpc32xx_rtc_driver);
408}
409module_exit(lpc32xx_rtc_exit);
410
411MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
412MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
413MODULE_LICENSE("GPL");
414MODULE_ALIAS("platform:rtc-lpc32xx");
diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c
index 6dc4e6241418..5a8daa358066 100644
--- a/drivers/rtc/rtc-m41t80.c
+++ b/drivers/rtc/rtc-m41t80.c
@@ -20,7 +20,7 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/rtc.h> 21#include <linux/rtc.h>
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/smp_lock.h> 23#include <linux/mutex.h>
24#include <linux/string.h> 24#include <linux/string.h>
25#ifdef CONFIG_RTC_DRV_M41T80_WDT 25#ifdef CONFIG_RTC_DRV_M41T80_WDT
26#include <linux/fs.h> 26#include <linux/fs.h>
@@ -68,6 +68,7 @@
68 68
69#define DRV_VERSION "0.05" 69#define DRV_VERSION "0.05"
70 70
71static DEFINE_MUTEX(m41t80_rtc_mutex);
71static const struct i2c_device_id m41t80_id[] = { 72static const struct i2c_device_id m41t80_id[] = {
72 { "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT }, 73 { "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT },
73 { "m41t65", M41T80_FEATURE_HT | M41T80_FEATURE_WD }, 74 { "m41t65", M41T80_FEATURE_HT | M41T80_FEATURE_WD },
@@ -121,7 +122,7 @@ static int m41t80_get_datetime(struct i2c_client *client,
121 122
122 /* assume 20YY not 19YY, and ignore the Century Bit */ 123 /* assume 20YY not 19YY, and ignore the Century Bit */
123 tm->tm_year = bcd2bin(buf[M41T80_REG_YEAR]) + 100; 124 tm->tm_year = bcd2bin(buf[M41T80_REG_YEAR]) + 100;
124 return 0; 125 return rtc_valid_tm(tm);
125} 126}
126 127
127/* Sets the given date and time to the real time clock. */ 128/* Sets the given date and time to the real time clock. */
@@ -677,9 +678,9 @@ static long wdt_unlocked_ioctl(struct file *file, unsigned int cmd,
677{ 678{
678 int ret; 679 int ret;
679 680
680 lock_kernel(); 681 mutex_lock(&m41t80_rtc_mutex);
681 ret = wdt_ioctl(file, cmd, arg); 682 ret = wdt_ioctl(file, cmd, arg);
682 unlock_kernel(); 683 mutex_unlock(&m41t80_rtc_mutex);
683 684
684 return ret; 685 return ret;
685} 686}
@@ -693,16 +694,16 @@ static long wdt_unlocked_ioctl(struct file *file, unsigned int cmd,
693static int wdt_open(struct inode *inode, struct file *file) 694static int wdt_open(struct inode *inode, struct file *file)
694{ 695{
695 if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) { 696 if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) {
696 lock_kernel(); 697 mutex_lock(&m41t80_rtc_mutex);
697 if (test_and_set_bit(0, &wdt_is_open)) { 698 if (test_and_set_bit(0, &wdt_is_open)) {
698 unlock_kernel(); 699 mutex_unlock(&m41t80_rtc_mutex);
699 return -EBUSY; 700 return -EBUSY;
700 } 701 }
701 /* 702 /*
702 * Activate 703 * Activate
703 */ 704 */
704 wdt_is_open = 1; 705 wdt_is_open = 1;
705 unlock_kernel(); 706 mutex_unlock(&m41t80_rtc_mutex);
706 return nonseekable_open(inode, file); 707 return nonseekable_open(inode, file);
707 } 708 }
708 return -ENODEV; 709 return -ENODEV;
@@ -748,6 +749,7 @@ static const struct file_operations wdt_fops = {
748 .write = wdt_write, 749 .write = wdt_write,
749 .open = wdt_open, 750 .open = wdt_open,
750 .release = wdt_release, 751 .release = wdt_release,
752 .llseek = no_llseek,
751}; 753};
752 754
753static struct miscdevice wdt_dev = { 755static struct miscdevice wdt_dev = {
diff --git a/drivers/rtc/rtc-m48t59.c b/drivers/rtc/rtc-m48t59.c
index be8359fdb65a..a99a0b554eb8 100644
--- a/drivers/rtc/rtc-m48t59.c
+++ b/drivers/rtc/rtc-m48t59.c
@@ -105,7 +105,7 @@ static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
105 dev_dbg(dev, "RTC read time %04d-%02d-%02d %02d/%02d/%02d\n", 105 dev_dbg(dev, "RTC read time %04d-%02d-%02d %02d/%02d/%02d\n",
106 tm->tm_year + 1900, tm->tm_mon, tm->tm_mday, 106 tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
107 tm->tm_hour, tm->tm_min, tm->tm_sec); 107 tm->tm_hour, tm->tm_min, tm->tm_sec);
108 return 0; 108 return rtc_valid_tm(tm);
109} 109}
110 110
111static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm) 111static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
@@ -196,7 +196,7 @@ static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
196 dev_dbg(dev, "RTC read alarm time %04d-%02d-%02d %02d/%02d/%02d\n", 196 dev_dbg(dev, "RTC read alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
197 tm->tm_year + 1900, tm->tm_mon, tm->tm_mday, 197 tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
198 tm->tm_hour, tm->tm_min, tm->tm_sec); 198 tm->tm_hour, tm->tm_min, tm->tm_sec);
199 return 0; 199 return rtc_valid_tm(tm);
200} 200}
201 201
202/* 202/*
@@ -506,7 +506,6 @@ out:
506 free_irq(m48t59->irq, &pdev->dev); 506 free_irq(m48t59->irq, &pdev->dev);
507 if (m48t59->ioaddr) 507 if (m48t59->ioaddr)
508 iounmap(m48t59->ioaddr); 508 iounmap(m48t59->ioaddr);
509 if (m48t59)
510 kfree(m48t59); 509 kfree(m48t59);
511 return ret; 510 return ret;
512} 511}
diff --git a/drivers/rtc/rtc-m48t86.c b/drivers/rtc/rtc-m48t86.c
index 7c045cffa9ff..f981287d582b 100644
--- a/drivers/rtc/rtc-m48t86.c
+++ b/drivers/rtc/rtc-m48t86.c
@@ -77,7 +77,7 @@ static int m48t86_rtc_read_time(struct device *dev, struct rtc_time *tm)
77 if (ops->readbyte(M48T86_REG_HOUR) & 0x80) 77 if (ops->readbyte(M48T86_REG_HOUR) & 0x80)
78 tm->tm_hour += 12; 78 tm->tm_hour += 12;
79 79
80 return 0; 80 return rtc_valid_tm(tm);
81} 81}
82 82
83static int m48t86_rtc_set_time(struct device *dev, struct rtc_time *tm) 83static int m48t86_rtc_set_time(struct device *dev, struct rtc_time *tm)
diff --git a/drivers/rtc/rtc-max6900.c b/drivers/rtc/rtc-max6900.c
index a4f6665ab3c5..486142c2637a 100644
--- a/drivers/rtc/rtc-max6900.c
+++ b/drivers/rtc/rtc-max6900.c
@@ -159,7 +159,7 @@ static int max6900_i2c_read_time(struct i2c_client *client, struct rtc_time *tm)
159 bcd2bin(regs[MAX6900_REG_CENTURY]) * 100 - 1900; 159 bcd2bin(regs[MAX6900_REG_CENTURY]) * 100 - 1900;
160 tm->tm_wday = bcd2bin(regs[MAX6900_REG_DW]); 160 tm->tm_wday = bcd2bin(regs[MAX6900_REG_DW]);
161 161
162 return 0; 162 return rtc_valid_tm(tm);
163} 163}
164 164
165static int max6900_i2c_clear_write_protect(struct i2c_client *client) 165static int max6900_i2c_clear_write_protect(struct i2c_client *client)
diff --git a/drivers/rtc/rtc-mpc5121.c b/drivers/rtc/rtc-mpc5121.c
index db5d8c416d26..dfcdf0901d21 100644
--- a/drivers/rtc/rtc-mpc5121.c
+++ b/drivers/rtc/rtc-mpc5121.c
@@ -268,7 +268,7 @@ static const struct rtc_class_ops mpc5121_rtc_ops = {
268 .update_irq_enable = mpc5121_rtc_update_irq_enable, 268 .update_irq_enable = mpc5121_rtc_update_irq_enable,
269}; 269};
270 270
271static int __devinit mpc5121_rtc_probe(struct of_device *op, 271static int __devinit mpc5121_rtc_probe(struct platform_device *op,
272 const struct of_device_id *match) 272 const struct of_device_id *match)
273{ 273{
274 struct mpc5121_rtc_data *rtc; 274 struct mpc5121_rtc_data *rtc;
@@ -338,7 +338,7 @@ out_free:
338 return err; 338 return err;
339} 339}
340 340
341static int __devexit mpc5121_rtc_remove(struct of_device *op) 341static int __devexit mpc5121_rtc_remove(struct platform_device *op)
342{ 342{
343 struct mpc5121_rtc_data *rtc = dev_get_drvdata(&op->dev); 343 struct mpc5121_rtc_data *rtc = dev_get_drvdata(&op->dev);
344 struct mpc5121_rtc_regs __iomem *regs = rtc->regs; 344 struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
index 25ec921db07c..0b06c1e03fd5 100644
--- a/drivers/rtc/rtc-mxc.c
+++ b/drivers/rtc/rtc-mxc.c
@@ -83,12 +83,6 @@ struct rtc_plat_data {
83 void __iomem *ioaddr; 83 void __iomem *ioaddr;
84 int irq; 84 int irq;
85 struct clk *clk; 85 struct clk *clk;
86 unsigned int irqen;
87 int alrm_sec;
88 int alrm_min;
89 int alrm_hour;
90 int alrm_mday;
91 struct timespec mxc_rtc_delta;
92 struct rtc_time g_rtc_alarm; 86 struct rtc_time g_rtc_alarm;
93}; 87};
94 88
diff --git a/drivers/rtc/rtc-nuc900.c b/drivers/rtc/rtc-nuc900.c
index a351bd5d8176..ddb0857e15a4 100644
--- a/drivers/rtc/rtc-nuc900.c
+++ b/drivers/rtc/rtc-nuc900.c
@@ -85,25 +85,24 @@ static irqreturn_t nuc900_rtc_interrupt(int irq, void *_rtc)
85 85
86static int *check_rtc_access_enable(struct nuc900_rtc *nuc900_rtc) 86static int *check_rtc_access_enable(struct nuc900_rtc *nuc900_rtc)
87{ 87{
88 unsigned int i; 88 unsigned int timeout = 0x1000;
89 __raw_writel(INIRRESET, nuc900_rtc->rtc_reg + REG_RTC_INIR); 89 __raw_writel(INIRRESET, nuc900_rtc->rtc_reg + REG_RTC_INIR);
90 90
91 mdelay(10); 91 mdelay(10);
92 92
93 __raw_writel(AERPOWERON, nuc900_rtc->rtc_reg + REG_RTC_AER); 93 __raw_writel(AERPOWERON, nuc900_rtc->rtc_reg + REG_RTC_AER);
94 94
95 for (i = 0; i < 1000; i++) { 95 while (!(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
96 if (__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB) 96 && timeout--)
97 return 0; 97 mdelay(1);
98 }
99 98
100 if ((__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB) == 0x0) 99 if (!timeout)
101 return ERR_PTR(-ENODEV); 100 return ERR_PTR(-EPERM);
102 101
103 return ERR_PTR(-EPERM); 102 return 0;
104} 103}
105 104
106static void nuc900_rtc_bcd2bin(unsigned int timereg, 105static int nuc900_rtc_bcd2bin(unsigned int timereg,
107 unsigned int calreg, struct rtc_time *tm) 106 unsigned int calreg, struct rtc_time *tm)
108{ 107{
109 tm->tm_mday = bcd2bin(calreg >> 0); 108 tm->tm_mday = bcd2bin(calreg >> 0);
@@ -114,15 +113,21 @@ static void nuc900_rtc_bcd2bin(unsigned int timereg,
114 tm->tm_min = bcd2bin(timereg >> 8); 113 tm->tm_min = bcd2bin(timereg >> 8);
115 tm->tm_hour = bcd2bin(timereg >> 16); 114 tm->tm_hour = bcd2bin(timereg >> 16);
116 115
117 rtc_valid_tm(tm); 116 return rtc_valid_tm(tm);
118} 117}
119 118
120static void nuc900_rtc_bin2bcd(struct rtc_time *settm, 119static void nuc900_rtc_bin2bcd(struct device *dev, struct rtc_time *settm,
121 struct nuc900_bcd_time *gettm) 120 struct nuc900_bcd_time *gettm)
122{ 121{
123 gettm->bcd_mday = bin2bcd(settm->tm_mday) << 0; 122 gettm->bcd_mday = bin2bcd(settm->tm_mday) << 0;
124 gettm->bcd_mon = bin2bcd(settm->tm_mon) << 8; 123 gettm->bcd_mon = bin2bcd(settm->tm_mon) << 8;
125 gettm->bcd_year = bin2bcd(settm->tm_year - 100) << 16; 124
125 if (settm->tm_year < 100) {
126 dev_warn(dev, "The year will be between 1970-1999, right?\n");
127 gettm->bcd_year = bin2bcd(settm->tm_year) << 16;
128 } else {
129 gettm->bcd_year = bin2bcd(settm->tm_year - 100) << 16;
130 }
126 131
127 gettm->bcd_sec = bin2bcd(settm->tm_sec) << 0; 132 gettm->bcd_sec = bin2bcd(settm->tm_sec) << 0;
128 gettm->bcd_min = bin2bcd(settm->tm_min) << 8; 133 gettm->bcd_min = bin2bcd(settm->tm_min) << 8;
@@ -165,9 +170,7 @@ static int nuc900_rtc_read_time(struct device *dev, struct rtc_time *tm)
165 timeval = __raw_readl(rtc->rtc_reg + REG_RTC_TLR); 170 timeval = __raw_readl(rtc->rtc_reg + REG_RTC_TLR);
166 clrval = __raw_readl(rtc->rtc_reg + REG_RTC_CLR); 171 clrval = __raw_readl(rtc->rtc_reg + REG_RTC_CLR);
167 172
168 nuc900_rtc_bcd2bin(timeval, clrval, tm); 173 return nuc900_rtc_bcd2bin(timeval, clrval, tm);
169
170 return 0;
171} 174}
172 175
173static int nuc900_rtc_set_time(struct device *dev, struct rtc_time *tm) 176static int nuc900_rtc_set_time(struct device *dev, struct rtc_time *tm)
@@ -177,7 +180,7 @@ static int nuc900_rtc_set_time(struct device *dev, struct rtc_time *tm)
177 unsigned long val; 180 unsigned long val;
178 int *err; 181 int *err;
179 182
180 nuc900_rtc_bin2bcd(tm, &gettm); 183 nuc900_rtc_bin2bcd(dev, tm, &gettm);
181 184
182 err = check_rtc_access_enable(rtc); 185 err = check_rtc_access_enable(rtc);
183 if (IS_ERR(err)) 186 if (IS_ERR(err))
@@ -200,9 +203,7 @@ static int nuc900_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
200 timeval = __raw_readl(rtc->rtc_reg + REG_RTC_TAR); 203 timeval = __raw_readl(rtc->rtc_reg + REG_RTC_TAR);
201 carval = __raw_readl(rtc->rtc_reg + REG_RTC_CAR); 204 carval = __raw_readl(rtc->rtc_reg + REG_RTC_CAR);
202 205
203 nuc900_rtc_bcd2bin(timeval, carval, &alrm->time); 206 return nuc900_rtc_bcd2bin(timeval, carval, &alrm->time);
204
205 return 0;
206} 207}
207 208
208static int nuc900_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 209static int nuc900_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
@@ -212,7 +213,7 @@ static int nuc900_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
212 unsigned long val; 213 unsigned long val;
213 int *err; 214 int *err;
214 215
215 nuc900_rtc_bin2bcd(&alrm->time, &tm); 216 nuc900_rtc_bin2bcd(dev, &alrm->time, &tm);
216 217
217 err = check_rtc_access_enable(rtc); 218 err = check_rtc_access_enable(rtc);
218 if (IS_ERR(err)) 219 if (IS_ERR(err))
@@ -268,29 +269,30 @@ static int __devinit nuc900_rtc_probe(struct platform_device *pdev)
268 goto fail2; 269 goto fail2;
269 } 270 }
270 271
271 nuc900_rtc->irq_num = platform_get_irq(pdev, 0); 272 platform_set_drvdata(pdev, nuc900_rtc);
272 if (request_irq(nuc900_rtc->irq_num, nuc900_rtc_interrupt,
273 IRQF_DISABLED, "nuc900rtc", nuc900_rtc)) {
274 dev_err(&pdev->dev, "NUC900 RTC request irq failed\n");
275 err = -EBUSY;
276 goto fail3;
277 }
278 273
279 nuc900_rtc->rtcdev = rtc_device_register(pdev->name, &pdev->dev, 274 nuc900_rtc->rtcdev = rtc_device_register(pdev->name, &pdev->dev,
280 &nuc900_rtc_ops, THIS_MODULE); 275 &nuc900_rtc_ops, THIS_MODULE);
281 if (IS_ERR(nuc900_rtc->rtcdev)) { 276 if (IS_ERR(nuc900_rtc->rtcdev)) {
282 dev_err(&pdev->dev, "rtc device register faild\n"); 277 dev_err(&pdev->dev, "rtc device register failed\n");
283 err = PTR_ERR(nuc900_rtc->rtcdev); 278 err = PTR_ERR(nuc900_rtc->rtcdev);
284 goto fail4; 279 goto fail3;
285 } 280 }
286 281
287 platform_set_drvdata(pdev, nuc900_rtc);
288 __raw_writel(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_TSSR) | MODE24, 282 __raw_writel(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_TSSR) | MODE24,
289 nuc900_rtc->rtc_reg + REG_RTC_TSSR); 283 nuc900_rtc->rtc_reg + REG_RTC_TSSR);
290 284
285 nuc900_rtc->irq_num = platform_get_irq(pdev, 0);
286 if (request_irq(nuc900_rtc->irq_num, nuc900_rtc_interrupt,
287 IRQF_DISABLED, "nuc900rtc", nuc900_rtc)) {
288 dev_err(&pdev->dev, "NUC900 RTC request irq failed\n");
289 err = -EBUSY;
290 goto fail4;
291 }
292
291 return 0; 293 return 0;
292 294
293fail4: free_irq(nuc900_rtc->irq_num, nuc900_rtc); 295fail4: rtc_device_unregister(nuc900_rtc->rtcdev);
294fail3: iounmap(nuc900_rtc->rtc_reg); 296fail3: iounmap(nuc900_rtc->rtc_reg);
295fail2: release_mem_region(res->start, resource_size(res)); 297fail2: release_mem_region(res->start, resource_size(res));
296fail1: kfree(nuc900_rtc); 298fail1: kfree(nuc900_rtc);
@@ -302,8 +304,8 @@ static int __devexit nuc900_rtc_remove(struct platform_device *pdev)
302 struct nuc900_rtc *nuc900_rtc = platform_get_drvdata(pdev); 304 struct nuc900_rtc *nuc900_rtc = platform_get_drvdata(pdev);
303 struct resource *res; 305 struct resource *res;
304 306
305 rtc_device_unregister(nuc900_rtc->rtcdev);
306 free_irq(nuc900_rtc->irq_num, nuc900_rtc); 307 free_irq(nuc900_rtc->irq_num, nuc900_rtc);
308 rtc_device_unregister(nuc900_rtc->rtcdev);
307 iounmap(nuc900_rtc->rtc_reg); 309 iounmap(nuc900_rtc->rtc_reg);
308 310
309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 311 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 64d9727b7229..73377b0d65da 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -34,7 +34,8 @@
34 * Board-specific wiring options include using split power mode with 34 * Board-specific wiring options include using split power mode with
35 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), 35 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
36 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from 36 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
37 * low power modes). See the BOARD-SPECIFIC CUSTOMIZATION comment. 37 * low power modes) for OMAP1 boards (OMAP-L138 has this built into
38 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
38 */ 39 */
39 40
40#define OMAP_RTC_BASE 0xfffb4800 41#define OMAP_RTC_BASE 0xfffb4800
@@ -401,16 +402,17 @@ static int __init omap_rtc_probe(struct platform_device *pdev)
401 402
402 /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: 403 /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
403 * 404 *
404 * - Boards wired so that RTC_WAKE_INT does something, and muxed 405 * - Device wake-up capability setting should come through chip
405 * right (W13_1610_RTC_WAKE_INT is the default after chip reset), 406 * init logic. OMAP1 boards should initialize the "wakeup capable"
406 * should initialize the device wakeup flag appropriately. 407 * flag in the platform device if the board is wired right for
408 * being woken up by RTC alarm. For OMAP-L138, this capability
409 * is built into the SoC by the "Deep Sleep" capability.
407 * 410 *
408 * - Boards wired so RTC_ON_nOFF is used as the reset signal, 411 * - Boards wired so RTC_ON_nOFF is used as the reset signal,
409 * rather than nPWRON_RESET, should forcibly enable split 412 * rather than nPWRON_RESET, should forcibly enable split
410 * power mode. (Some chip errata report that RTC_CTRL_SPLIT 413 * power mode. (Some chip errata report that RTC_CTRL_SPLIT
411 * is write-only, and always reads as zero...) 414 * is write-only, and always reads as zero...)
412 */ 415 */
413 device_init_wakeup(&pdev->dev, 0);
414 416
415 if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT) 417 if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
416 pr_info("%s: split power mode\n", pdev->name); 418 pr_info("%s: split power mode\n", pdev->name);
diff --git a/drivers/rtc/rtc-pcf8563.c b/drivers/rtc/rtc-pcf8563.c
index 1af42b4a6f59..b42c0c679266 100644
--- a/drivers/rtc/rtc-pcf8563.c
+++ b/drivers/rtc/rtc-pcf8563.c
@@ -172,14 +172,6 @@ static int pcf8563_set_datetime(struct i2c_client *client, struct rtc_time *tm)
172 return 0; 172 return 0;
173} 173}
174 174
175struct pcf8563_limit
176{
177 unsigned char reg;
178 unsigned char mask;
179 unsigned char min;
180 unsigned char max;
181};
182
183static int pcf8563_rtc_read_time(struct device *dev, struct rtc_time *tm) 175static int pcf8563_rtc_read_time(struct device *dev, struct rtc_time *tm)
184{ 176{
185 return pcf8563_get_datetime(to_i2c_client(dev), tm); 177 return pcf8563_get_datetime(to_i2c_client(dev), tm);
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c
index 3587d9922f28..b7a6690e5b35 100644
--- a/drivers/rtc/rtc-pl031.c
+++ b/drivers/rtc/rtc-pl031.c
@@ -23,7 +23,6 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/bcd.h> 24#include <linux/bcd.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/version.h>
27#include <linux/slab.h> 26#include <linux/slab.h>
28 27
29/* 28/*
@@ -404,7 +403,7 @@ static int pl031_probe(struct amba_device *adev, struct amba_id *id)
404 } 403 }
405 404
406 if (request_irq(adev->irq[0], pl031_interrupt, 405 if (request_irq(adev->irq[0], pl031_interrupt,
407 IRQF_DISABLED | IRQF_SHARED, "rtc-pl031", ldata)) { 406 IRQF_DISABLED, "rtc-pl031", ldata)) {
408 ret = -EIO; 407 ret = -EIO;
409 goto out_no_irq; 408 goto out_no_irq;
410 } 409 }
@@ -456,7 +455,7 @@ static struct rtc_class_ops stv2_pl031_ops = {
456 .irq_set_freq = pl031_irq_set_freq, 455 .irq_set_freq = pl031_irq_set_freq,
457}; 456};
458 457
459static struct amba_id pl031_ids[] __initdata = { 458static struct amba_id pl031_ids[] = {
460 { 459 {
461 .id = 0x00041031, 460 .id = 0x00041031,
462 .mask = 0x000fffff, 461 .mask = 0x000fffff,
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index e9c6fa035989..29e867a1aaa8 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -87,7 +87,6 @@ struct pxa_rtc {
87 int irq_Alrm; 87 int irq_Alrm;
88 struct rtc_device *rtc; 88 struct rtc_device *rtc;
89 spinlock_t lock; /* Protects this structure */ 89 spinlock_t lock; /* Protects this structure */
90 struct rtc_time rtc_alarm;
91}; 90};
92 91
93static u32 ryxr_calc(struct rtc_time *tm) 92static u32 ryxr_calc(struct rtc_time *tm)
@@ -236,32 +235,34 @@ static int pxa_periodic_irq_set_state(struct device *dev, int enabled)
236 return 0; 235 return 0;
237} 236}
238 237
239static int pxa_rtc_ioctl(struct device *dev, unsigned int cmd, 238static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
240 unsigned long arg)
241{ 239{
242 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 240 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
243 int ret = 0;
244 241
245 spin_lock_irq(&pxa_rtc->lock); 242 spin_lock_irq(&pxa_rtc->lock);
246 switch (cmd) { 243
247 case RTC_AIE_OFF: 244 if (enabled)
248 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
249 break;
250 case RTC_AIE_ON:
251 rtsr_set_bits(pxa_rtc, RTSR_RDALE1); 245 rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
252 break; 246 else
253 case RTC_UIE_OFF: 247 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
254 rtsr_clear_bits(pxa_rtc, RTSR_HZE); 248
255 break; 249 spin_unlock_irq(&pxa_rtc->lock);
256 case RTC_UIE_ON: 250 return 0;
251}
252
253static int pxa_update_irq_enable(struct device *dev, unsigned int enabled)
254{
255 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
256
257 spin_lock_irq(&pxa_rtc->lock);
258
259 if (enabled)
257 rtsr_set_bits(pxa_rtc, RTSR_HZE); 260 rtsr_set_bits(pxa_rtc, RTSR_HZE);
258 break; 261 else
259 default: 262 rtsr_clear_bits(pxa_rtc, RTSR_HZE);
260 ret = -ENOIOCTLCMD;
261 }
262 263
263 spin_unlock_irq(&pxa_rtc->lock); 264 spin_unlock_irq(&pxa_rtc->lock);
264 return ret; 265 return 0;
265} 266}
266 267
267static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm) 268static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
@@ -340,11 +341,12 @@ static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
340static const struct rtc_class_ops pxa_rtc_ops = { 341static const struct rtc_class_ops pxa_rtc_ops = {
341 .open = pxa_rtc_open, 342 .open = pxa_rtc_open,
342 .release = pxa_rtc_release, 343 .release = pxa_rtc_release,
343 .ioctl = pxa_rtc_ioctl,
344 .read_time = pxa_rtc_read_time, 344 .read_time = pxa_rtc_read_time,
345 .set_time = pxa_rtc_set_time, 345 .set_time = pxa_rtc_set_time,
346 .read_alarm = pxa_rtc_read_alarm, 346 .read_alarm = pxa_rtc_read_alarm,
347 .set_alarm = pxa_rtc_set_alarm, 347 .set_alarm = pxa_rtc_set_alarm,
348 .alarm_irq_enable = pxa_alarm_irq_enable,
349 .update_irq_enable = pxa_update_irq_enable,
348 .proc = pxa_rtc_proc, 350 .proc = pxa_rtc_proc,
349 .irq_set_state = pxa_periodic_irq_set_state, 351 .irq_set_state = pxa_periodic_irq_set_state,
350 .irq_set_freq = pxa_periodic_irq_set_freq, 352 .irq_set_freq = pxa_periodic_irq_set_freq,
diff --git a/drivers/rtc/rtc-rp5c01.c b/drivers/rtc/rtc-rp5c01.c
index a95f733bb15a..36eb66184461 100644
--- a/drivers/rtc/rtc-rp5c01.c
+++ b/drivers/rtc/rtc-rp5c01.c
@@ -63,6 +63,8 @@ enum {
63struct rp5c01_priv { 63struct rp5c01_priv {
64 u32 __iomem *regs; 64 u32 __iomem *regs;
65 struct rtc_device *rtc; 65 struct rtc_device *rtc;
66 spinlock_t lock; /* against concurrent RTC/NVRAM access */
67 struct bin_attribute nvram_attr;
66}; 68};
67 69
68static inline unsigned int rp5c01_read(struct rp5c01_priv *priv, 70static inline unsigned int rp5c01_read(struct rp5c01_priv *priv,
@@ -92,6 +94,7 @@ static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
92{ 94{
93 struct rp5c01_priv *priv = dev_get_drvdata(dev); 95 struct rp5c01_priv *priv = dev_get_drvdata(dev);
94 96
97 spin_lock_irq(&priv->lock);
95 rp5c01_lock(priv); 98 rp5c01_lock(priv);
96 99
97 tm->tm_sec = rp5c01_read(priv, RP5C01_10_SECOND) * 10 + 100 tm->tm_sec = rp5c01_read(priv, RP5C01_10_SECOND) * 10 +
@@ -111,6 +114,7 @@ static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
111 tm->tm_year += 100; 114 tm->tm_year += 100;
112 115
113 rp5c01_unlock(priv); 116 rp5c01_unlock(priv);
117 spin_unlock_irq(&priv->lock);
114 118
115 return rtc_valid_tm(tm); 119 return rtc_valid_tm(tm);
116} 120}
@@ -119,6 +123,7 @@ static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
119{ 123{
120 struct rp5c01_priv *priv = dev_get_drvdata(dev); 124 struct rp5c01_priv *priv = dev_get_drvdata(dev);
121 125
126 spin_lock_irq(&priv->lock);
122 rp5c01_lock(priv); 127 rp5c01_lock(priv);
123 128
124 rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND); 129 rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND);
@@ -139,6 +144,7 @@ static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
139 rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR); 144 rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR);
140 145
141 rp5c01_unlock(priv); 146 rp5c01_unlock(priv);
147 spin_unlock_irq(&priv->lock);
142 return 0; 148 return 0;
143} 149}
144 150
@@ -147,6 +153,72 @@ static const struct rtc_class_ops rp5c01_rtc_ops = {
147 .set_time = rp5c01_set_time, 153 .set_time = rp5c01_set_time,
148}; 154};
149 155
156
157/*
158 * The NVRAM is organized as 2 blocks of 13 nibbles of 4 bits.
159 * We provide access to them like AmigaOS does: the high nibble of each 8-bit
160 * byte is stored in BLOCK10, the low nibble in BLOCK11.
161 */
162
163static ssize_t rp5c01_nvram_read(struct file *filp, struct kobject *kobj,
164 struct bin_attribute *bin_attr,
165 char *buf, loff_t pos, size_t size)
166{
167 struct device *dev = container_of(kobj, struct device, kobj);
168 struct rp5c01_priv *priv = dev_get_drvdata(dev);
169 ssize_t count;
170
171 spin_lock_irq(&priv->lock);
172
173 for (count = 0; size > 0 && pos < RP5C01_MODE; count++, size--) {
174 u8 data;
175
176 rp5c01_write(priv,
177 RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
178 RP5C01_MODE);
179 data = rp5c01_read(priv, pos) << 4;
180 rp5c01_write(priv,
181 RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
182 RP5C01_MODE);
183 data |= rp5c01_read(priv, pos++);
184 rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
185 RP5C01_MODE);
186 *buf++ = data;
187 }
188
189 spin_unlock_irq(&priv->lock);
190 return count;
191}
192
193static ssize_t rp5c01_nvram_write(struct file *filp, struct kobject *kobj,
194 struct bin_attribute *bin_attr,
195 char *buf, loff_t pos, size_t size)
196{
197 struct device *dev = container_of(kobj, struct device, kobj);
198 struct rp5c01_priv *priv = dev_get_drvdata(dev);
199 ssize_t count;
200
201 spin_lock_irq(&priv->lock);
202
203 for (count = 0; size > 0 && pos < RP5C01_MODE; count++, size--) {
204 u8 data = *buf++;
205
206 rp5c01_write(priv,
207 RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
208 RP5C01_MODE);
209 rp5c01_write(priv, data >> 4, pos);
210 rp5c01_write(priv,
211 RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
212 RP5C01_MODE);
213 rp5c01_write(priv, data & 0xf, pos++);
214 rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
215 RP5C01_MODE);
216 }
217
218 spin_unlock_irq(&priv->lock);
219 return count;
220}
221
150static int __init rp5c01_rtc_probe(struct platform_device *dev) 222static int __init rp5c01_rtc_probe(struct platform_device *dev)
151{ 223{
152 struct resource *res; 224 struct resource *res;
@@ -168,6 +240,15 @@ static int __init rp5c01_rtc_probe(struct platform_device *dev)
168 goto out_free_priv; 240 goto out_free_priv;
169 } 241 }
170 242
243 sysfs_bin_attr_init(&priv->nvram_attr);
244 priv->nvram_attr.attr.name = "nvram";
245 priv->nvram_attr.attr.mode = S_IRUGO | S_IWUSR;
246 priv->nvram_attr.read = rp5c01_nvram_read;
247 priv->nvram_attr.write = rp5c01_nvram_write;
248 priv->nvram_attr.size = RP5C01_MODE;
249
250 spin_lock_init(&priv->lock);
251
171 rtc = rtc_device_register("rtc-rp5c01", &dev->dev, &rp5c01_rtc_ops, 252 rtc = rtc_device_register("rtc-rp5c01", &dev->dev, &rp5c01_rtc_ops,
172 THIS_MODULE); 253 THIS_MODULE);
173 if (IS_ERR(rtc)) { 254 if (IS_ERR(rtc)) {
@@ -177,8 +258,15 @@ static int __init rp5c01_rtc_probe(struct platform_device *dev)
177 258
178 priv->rtc = rtc; 259 priv->rtc = rtc;
179 platform_set_drvdata(dev, priv); 260 platform_set_drvdata(dev, priv);
261
262 error = sysfs_create_bin_file(&dev->dev.kobj, &priv->nvram_attr);
263 if (error)
264 goto out_unregister;
265
180 return 0; 266 return 0;
181 267
268out_unregister:
269 rtc_device_unregister(rtc);
182out_unmap: 270out_unmap:
183 iounmap(priv->regs); 271 iounmap(priv->regs);
184out_free_priv: 272out_free_priv:
@@ -190,6 +278,7 @@ static int __exit rp5c01_rtc_remove(struct platform_device *dev)
190{ 278{
191 struct rp5c01_priv *priv = platform_get_drvdata(dev); 279 struct rp5c01_priv *priv = platform_get_drvdata(dev);
192 280
281 sysfs_remove_bin_file(&dev->dev.kobj, &priv->nvram_attr);
193 rtc_device_unregister(priv->rtc); 282 rtc_device_unregister(priv->rtc);
194 iounmap(priv->regs); 283 iounmap(priv->regs);
195 kfree(priv); 284 kfree(priv);
diff --git a/drivers/rtc/rtc-rs5c313.c b/drivers/rtc/rtc-rs5c313.c
index e6ea3f5ee1eb..e3ff179b99ca 100644
--- a/drivers/rtc/rtc-rs5c313.c
+++ b/drivers/rtc/rtc-rs5c313.c
@@ -80,21 +80,21 @@
80/* SCSPTR1 data */ 80/* SCSPTR1 data */
81unsigned char scsptr1_data; 81unsigned char scsptr1_data;
82 82
83#define RS5C313_CEENABLE ctrl_outb(RS5C313_CE_RTCCE, RS5C313_CE); 83#define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
84#define RS5C313_CEDISABLE ctrl_outb(0x00, RS5C313_CE) 84#define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE)
85#define RS5C313_MISCOP ctrl_outb(0x02, 0xB0000008) 85#define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008)
86 86
87static void rs5c313_init_port(void) 87static void rs5c313_init_port(void)
88{ 88{
89 /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */ 89 /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
90 ctrl_outb(ctrl_inb(SCSMR1) & ~SCSMR1_CA, SCSMR1); 90 __raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
91 ctrl_outb(ctrl_inb(SCSCR1) & ~SCSCR1_CKE, SCSCR1); 91 __raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
92 92
93 /* And Initialize SCL for RS5C313 clock */ 93 /* And Initialize SCL for RS5C313 clock */
94 scsptr1_data = ctrl_inb(SCSPTR1) | SCL; /* SCL:H */ 94 scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */
95 ctrl_outb(scsptr1_data, SCSPTR1); 95 __raw_writeb(scsptr1_data, SCSPTR1);
96 scsptr1_data = ctrl_inb(SCSPTR1) | SCL_OEN; /* SCL output enable */ 96 scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */
97 ctrl_outb(scsptr1_data, SCSPTR1); 97 __raw_writeb(scsptr1_data, SCSPTR1);
98 RS5C313_CEDISABLE; /* CE:L */ 98 RS5C313_CEDISABLE; /* CE:L */
99} 99}
100 100
@@ -106,21 +106,21 @@ static void rs5c313_write_data(unsigned char data)
106 /* SDA:Write Data */ 106 /* SDA:Write Data */
107 scsptr1_data = (scsptr1_data & ~SDA) | 107 scsptr1_data = (scsptr1_data & ~SDA) |
108 ((((0x80 >> i) & data) >> (7 - i)) << 2); 108 ((((0x80 >> i) & data) >> (7 - i)) << 2);
109 ctrl_outb(scsptr1_data, SCSPTR1); 109 __raw_writeb(scsptr1_data, SCSPTR1);
110 if (i == 0) { 110 if (i == 0) {
111 scsptr1_data |= SDA_OEN; /* SDA:output enable */ 111 scsptr1_data |= SDA_OEN; /* SDA:output enable */
112 ctrl_outb(scsptr1_data, SCSPTR1); 112 __raw_writeb(scsptr1_data, SCSPTR1);
113 } 113 }
114 ndelay(700); 114 ndelay(700);
115 scsptr1_data &= ~SCL; /* SCL:L */ 115 scsptr1_data &= ~SCL; /* SCL:L */
116 ctrl_outb(scsptr1_data, SCSPTR1); 116 __raw_writeb(scsptr1_data, SCSPTR1);
117 ndelay(700); 117 ndelay(700);
118 scsptr1_data |= SCL; /* SCL:H */ 118 scsptr1_data |= SCL; /* SCL:H */
119 ctrl_outb(scsptr1_data, SCSPTR1); 119 __raw_writeb(scsptr1_data, SCSPTR1);
120 } 120 }
121 121
122 scsptr1_data &= ~SDA_OEN; /* SDA:output disable */ 122 scsptr1_data &= ~SDA_OEN; /* SDA:output disable */
123 ctrl_outb(scsptr1_data, SCSPTR1); 123 __raw_writeb(scsptr1_data, SCSPTR1);
124} 124}
125 125
126static unsigned char rs5c313_read_data(void) 126static unsigned char rs5c313_read_data(void)
@@ -131,12 +131,12 @@ static unsigned char rs5c313_read_data(void)
131 for (i = 0; i < 8; i++) { 131 for (i = 0; i < 8; i++) {
132 ndelay(700); 132 ndelay(700);
133 /* SDA:Read Data */ 133 /* SDA:Read Data */
134 data |= ((ctrl_inb(SCSPTR1) & SDA) >> 2) << (7 - i); 134 data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
135 scsptr1_data &= ~SCL; /* SCL:L */ 135 scsptr1_data &= ~SCL; /* SCL:L */
136 ctrl_outb(scsptr1_data, SCSPTR1); 136 __raw_writeb(scsptr1_data, SCSPTR1);
137 ndelay(700); 137 ndelay(700);
138 scsptr1_data |= SCL; /* SCL:H */ 138 scsptr1_data |= SCL; /* SCL:H */
139 ctrl_outb(scsptr1_data, SCSPTR1); 139 __raw_writeb(scsptr1_data, SCSPTR1);
140 } 140 }
141 return data & 0x0F; 141 return data & 0x0F;
142} 142}
diff --git a/drivers/rtc/rtc-rx8025.c b/drivers/rtc/rtc-rx8025.c
index 789f62f9b47d..1146e3522d3c 100644
--- a/drivers/rtc/rtc-rx8025.c
+++ b/drivers/rtc/rtc-rx8025.c
@@ -461,7 +461,7 @@ static struct rtc_class_ops rx8025_rtc_ops = {
461 * Clock precision adjustment support 461 * Clock precision adjustment support
462 * 462 *
463 * According to the RX8025 SA/NB application manual the frequency and 463 * According to the RX8025 SA/NB application manual the frequency and
464 * temperature charateristics can be approximated using the following 464 * temperature characteristics can be approximated using the following
465 * equation: 465 * equation:
466 * 466 *
467 * df = a * (ut - t)**2 467 * df = a * (ut - t)**2
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 70b68d35f969..cf953ecbfca9 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -1,5 +1,8 @@
1/* drivers/rtc/rtc-s3c.c 1/* drivers/rtc/rtc-s3c.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
3 * Copyright (c) 2004,2006 Simtec Electronics 6 * Copyright (c) 2004,2006 Simtec Electronics
4 * Ben Dooks, <ben@simtec.co.uk> 7 * Ben Dooks, <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/ 8 * http://armlinux.simtec.co.uk/
@@ -39,6 +42,7 @@ enum s3c_cpu_type {
39 42
40static struct resource *s3c_rtc_mem; 43static struct resource *s3c_rtc_mem;
41 44
45static struct clk *rtc_clk;
42static void __iomem *s3c_rtc_base; 46static void __iomem *s3c_rtc_base;
43static int s3c_rtc_alarmno = NO_IRQ; 47static int s3c_rtc_alarmno = NO_IRQ;
44static int s3c_rtc_tickno = NO_IRQ; 48static int s3c_rtc_tickno = NO_IRQ;
@@ -53,6 +57,10 @@ static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
53 struct rtc_device *rdev = id; 57 struct rtc_device *rdev = id;
54 58
55 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); 59 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
60
61 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
62 writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
63
56 return IRQ_HANDLED; 64 return IRQ_HANDLED;
57} 65}
58 66
@@ -61,6 +69,10 @@ static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
61 struct rtc_device *rdev = id; 69 struct rtc_device *rdev = id;
62 70
63 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); 71 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
72
73 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
74 writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
75
64 return IRQ_HANDLED; 76 return IRQ_HANDLED;
65} 77}
66 78
@@ -88,13 +100,13 @@ static int s3c_rtc_setpie(struct device *dev, int enabled)
88 spin_lock_irq(&s3c_rtc_pie_lock); 100 spin_lock_irq(&s3c_rtc_pie_lock);
89 101
90 if (s3c_rtc_cpu_type == TYPE_S3C64XX) { 102 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
91 tmp = readb(s3c_rtc_base + S3C2410_RTCCON); 103 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
92 tmp &= ~S3C64XX_RTCCON_TICEN; 104 tmp &= ~S3C64XX_RTCCON_TICEN;
93 105
94 if (enabled) 106 if (enabled)
95 tmp |= S3C64XX_RTCCON_TICEN; 107 tmp |= S3C64XX_RTCCON_TICEN;
96 108
97 writeb(tmp, s3c_rtc_base + S3C2410_RTCCON); 109 writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
98 } else { 110 } else {
99 tmp = readb(s3c_rtc_base + S3C2410_TICNT); 111 tmp = readb(s3c_rtc_base + S3C2410_TICNT);
100 tmp &= ~S3C2410_TICNT_ENABLE; 112 tmp &= ~S3C2410_TICNT_ENABLE;
@@ -128,7 +140,7 @@ static int s3c_rtc_setfreq(struct device *dev, int freq)
128 140
129 tmp |= (rtc_dev->max_user_freq / freq)-1; 141 tmp |= (rtc_dev->max_user_freq / freq)-1;
130 142
131 writeb(tmp, s3c_rtc_base + S3C2410_TICNT); 143 writel(tmp, s3c_rtc_base + S3C2410_TICNT);
132 spin_unlock_irq(&s3c_rtc_pie_lock); 144 spin_unlock_irq(&s3c_rtc_pie_lock);
133 145
134 return 0; 146 return 0;
@@ -159,8 +171,8 @@ static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
159 goto retry_get_time; 171 goto retry_get_time;
160 } 172 }
161 173
162 pr_debug("read time %02x.%02x.%02x %02x/%02x/%02x\n", 174 pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n",
163 rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, 175 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
164 rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); 176 rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
165 177
166 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); 178 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
@@ -173,7 +185,7 @@ static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
173 rtc_tm->tm_year += 100; 185 rtc_tm->tm_year += 100;
174 rtc_tm->tm_mon -= 1; 186 rtc_tm->tm_mon -= 1;
175 187
176 return 0; 188 return rtc_valid_tm(rtc_tm);
177} 189}
178 190
179static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) 191static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
@@ -181,8 +193,8 @@ static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
181 void __iomem *base = s3c_rtc_base; 193 void __iomem *base = s3c_rtc_base;
182 int year = tm->tm_year - 100; 194 int year = tm->tm_year - 100;
183 195
184 pr_debug("set time %02d.%02d.%02d %02d/%02d/%02d\n", 196 pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n",
185 tm->tm_year, tm->tm_mon, tm->tm_mday, 197 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
186 tm->tm_hour, tm->tm_min, tm->tm_sec); 198 tm->tm_hour, tm->tm_min, tm->tm_sec);
187 199
188 /* we get around y2k by simply not supporting it */ 200 /* we get around y2k by simply not supporting it */
@@ -219,9 +231,9 @@ static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
219 231
220 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; 232 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
221 233
222 pr_debug("read alarm %02x %02x.%02x.%02x %02x/%02x/%02x\n", 234 pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
223 alm_en, 235 alm_en,
224 alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, 236 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
225 alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); 237 alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
226 238
227 239
@@ -230,34 +242,34 @@ static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
230 if (alm_en & S3C2410_RTCALM_SECEN) 242 if (alm_en & S3C2410_RTCALM_SECEN)
231 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); 243 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
232 else 244 else
233 alm_tm->tm_sec = 0xff; 245 alm_tm->tm_sec = -1;
234 246
235 if (alm_en & S3C2410_RTCALM_MINEN) 247 if (alm_en & S3C2410_RTCALM_MINEN)
236 alm_tm->tm_min = bcd2bin(alm_tm->tm_min); 248 alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
237 else 249 else
238 alm_tm->tm_min = 0xff; 250 alm_tm->tm_min = -1;
239 251
240 if (alm_en & S3C2410_RTCALM_HOUREN) 252 if (alm_en & S3C2410_RTCALM_HOUREN)
241 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); 253 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
242 else 254 else
243 alm_tm->tm_hour = 0xff; 255 alm_tm->tm_hour = -1;
244 256
245 if (alm_en & S3C2410_RTCALM_DAYEN) 257 if (alm_en & S3C2410_RTCALM_DAYEN)
246 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); 258 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
247 else 259 else
248 alm_tm->tm_mday = 0xff; 260 alm_tm->tm_mday = -1;
249 261
250 if (alm_en & S3C2410_RTCALM_MONEN) { 262 if (alm_en & S3C2410_RTCALM_MONEN) {
251 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); 263 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
252 alm_tm->tm_mon -= 1; 264 alm_tm->tm_mon -= 1;
253 } else { 265 } else {
254 alm_tm->tm_mon = 0xff; 266 alm_tm->tm_mon = -1;
255 } 267 }
256 268
257 if (alm_en & S3C2410_RTCALM_YEAREN) 269 if (alm_en & S3C2410_RTCALM_YEAREN)
258 alm_tm->tm_year = bcd2bin(alm_tm->tm_year); 270 alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
259 else 271 else
260 alm_tm->tm_year = 0xffff; 272 alm_tm->tm_year = -1;
261 273
262 return 0; 274 return 0;
263} 275}
@@ -268,10 +280,10 @@ static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
268 void __iomem *base = s3c_rtc_base; 280 void __iomem *base = s3c_rtc_base;
269 unsigned int alrm_en; 281 unsigned int alrm_en;
270 282
271 pr_debug("s3c_rtc_setalarm: %d, %02x/%02x/%02x %02x.%02x.%02x\n", 283 pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
272 alrm->enabled, 284 alrm->enabled,
273 tm->tm_mday & 0xff, tm->tm_mon & 0xff, tm->tm_year & 0xff, 285 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
274 tm->tm_hour & 0xff, tm->tm_min & 0xff, tm->tm_sec); 286 tm->tm_hour, tm->tm_min, tm->tm_sec);
275 287
276 288
277 alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; 289 alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
@@ -298,11 +310,6 @@ static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
298 310
299 s3c_rtc_setaie(alrm->enabled); 311 s3c_rtc_setaie(alrm->enabled);
300 312
301 if (alrm->enabled)
302 enable_irq_wake(s3c_rtc_alarmno);
303 else
304 disable_irq_wake(s3c_rtc_alarmno);
305
306 return 0; 313 return 0;
307} 314}
308 315
@@ -311,7 +318,7 @@ static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
311 unsigned int ticnt; 318 unsigned int ticnt;
312 319
313 if (s3c_rtc_cpu_type == TYPE_S3C64XX) { 320 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
314 ticnt = readb(s3c_rtc_base + S3C2410_RTCCON); 321 ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
315 ticnt &= S3C64XX_RTCCON_TICEN; 322 ticnt &= S3C64XX_RTCCON_TICEN;
316 } else { 323 } else {
317 ticnt = readb(s3c_rtc_base + S3C2410_TICNT); 324 ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
@@ -372,7 +379,8 @@ static const struct rtc_class_ops s3c_rtcops = {
372 .set_alarm = s3c_rtc_setalarm, 379 .set_alarm = s3c_rtc_setalarm,
373 .irq_set_freq = s3c_rtc_setfreq, 380 .irq_set_freq = s3c_rtc_setfreq,
374 .irq_set_state = s3c_rtc_setpie, 381 .irq_set_state = s3c_rtc_setpie,
375 .proc = s3c_rtc_proc, 382 .proc = s3c_rtc_proc,
383 .alarm_irq_enable = s3c_rtc_setaie,
376}; 384};
377 385
378static void s3c_rtc_enable(struct platform_device *pdev, int en) 386static void s3c_rtc_enable(struct platform_device *pdev, int en)
@@ -384,11 +392,11 @@ static void s3c_rtc_enable(struct platform_device *pdev, int en)
384 return; 392 return;
385 393
386 if (!en) { 394 if (!en) {
387 tmp = readb(base + S3C2410_RTCCON); 395 tmp = readw(base + S3C2410_RTCCON);
388 if (s3c_rtc_cpu_type == TYPE_S3C64XX) 396 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
389 tmp &= ~S3C64XX_RTCCON_TICEN; 397 tmp &= ~S3C64XX_RTCCON_TICEN;
390 tmp &= ~S3C2410_RTCCON_RTCEN; 398 tmp &= ~S3C2410_RTCCON_RTCEN;
391 writeb(tmp, base + S3C2410_RTCCON); 399 writew(tmp, base + S3C2410_RTCCON);
392 400
393 if (s3c_rtc_cpu_type == TYPE_S3C2410) { 401 if (s3c_rtc_cpu_type == TYPE_S3C2410) {
394 tmp = readb(base + S3C2410_TICNT); 402 tmp = readb(base + S3C2410_TICNT);
@@ -398,25 +406,28 @@ static void s3c_rtc_enable(struct platform_device *pdev, int en)
398 } else { 406 } else {
399 /* re-enable the device, and check it is ok */ 407 /* re-enable the device, and check it is ok */
400 408
401 if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){ 409 if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
402 dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); 410 dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
403 411
404 tmp = readb(base + S3C2410_RTCCON); 412 tmp = readw(base + S3C2410_RTCCON);
405 writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON); 413 writew(tmp | S3C2410_RTCCON_RTCEN,
414 base + S3C2410_RTCCON);
406 } 415 }
407 416
408 if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){ 417 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
409 dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); 418 dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
410 419
411 tmp = readb(base + S3C2410_RTCCON); 420 tmp = readw(base + S3C2410_RTCCON);
412 writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON); 421 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
422 base + S3C2410_RTCCON);
413 } 423 }
414 424
415 if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){ 425 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
416 dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); 426 dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
417 427
418 tmp = readb(base + S3C2410_RTCCON); 428 tmp = readw(base + S3C2410_RTCCON);
419 writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON); 429 writew(tmp & ~S3C2410_RTCCON_CLKRST,
430 base + S3C2410_RTCCON);
420 } 431 }
421 } 432 }
422} 433}
@@ -431,6 +442,10 @@ static int __devexit s3c_rtc_remove(struct platform_device *dev)
431 s3c_rtc_setpie(&dev->dev, 0); 442 s3c_rtc_setpie(&dev->dev, 0);
432 s3c_rtc_setaie(0); 443 s3c_rtc_setaie(0);
433 444
445 clk_disable(rtc_clk);
446 clk_put(rtc_clk);
447 rtc_clk = NULL;
448
434 iounmap(s3c_rtc_base); 449 iounmap(s3c_rtc_base);
435 release_resource(s3c_rtc_mem); 450 release_resource(s3c_rtc_mem);
436 kfree(s3c_rtc_mem); 451 kfree(s3c_rtc_mem);
@@ -441,6 +456,7 @@ static int __devexit s3c_rtc_remove(struct platform_device *dev)
441static int __devinit s3c_rtc_probe(struct platform_device *pdev) 456static int __devinit s3c_rtc_probe(struct platform_device *pdev)
442{ 457{
443 struct rtc_device *rtc; 458 struct rtc_device *rtc;
459 struct rtc_time rtc_tm;
444 struct resource *res; 460 struct resource *res;
445 int ret; 461 int ret;
446 462
@@ -488,12 +504,22 @@ static int __devinit s3c_rtc_probe(struct platform_device *pdev)
488 goto err_nomap; 504 goto err_nomap;
489 } 505 }
490 506
507 rtc_clk = clk_get(&pdev->dev, "rtc");
508 if (IS_ERR(rtc_clk)) {
509 dev_err(&pdev->dev, "failed to find rtc clock source\n");
510 ret = PTR_ERR(rtc_clk);
511 rtc_clk = NULL;
512 goto err_clk;
513 }
514
515 clk_enable(rtc_clk);
516
491 /* check to see if everything is setup correctly */ 517 /* check to see if everything is setup correctly */
492 518
493 s3c_rtc_enable(pdev, 1); 519 s3c_rtc_enable(pdev, 1);
494 520
495 pr_debug("s3c2410_rtc: RTCCON=%02x\n", 521 pr_debug("s3c2410_rtc: RTCCON=%02x\n",
496 readb(s3c_rtc_base + S3C2410_RTCCON)); 522 readw(s3c_rtc_base + S3C2410_RTCCON));
497 523
498 device_init_wakeup(&pdev->dev, 1); 524 device_init_wakeup(&pdev->dev, 1);
499 525
@@ -510,6 +536,23 @@ static int __devinit s3c_rtc_probe(struct platform_device *pdev)
510 536
511 s3c_rtc_cpu_type = platform_get_device_id(pdev)->driver_data; 537 s3c_rtc_cpu_type = platform_get_device_id(pdev)->driver_data;
512 538
539 /* Check RTC Time */
540
541 s3c_rtc_gettime(NULL, &rtc_tm);
542
543 if (rtc_valid_tm(&rtc_tm)) {
544 rtc_tm.tm_year = 100;
545 rtc_tm.tm_mon = 0;
546 rtc_tm.tm_mday = 1;
547 rtc_tm.tm_hour = 0;
548 rtc_tm.tm_min = 0;
549 rtc_tm.tm_sec = 0;
550
551 s3c_rtc_settime(NULL, &rtc_tm);
552
553 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
554 }
555
513 if (s3c_rtc_cpu_type == TYPE_S3C64XX) 556 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
514 rtc->max_user_freq = 32768; 557 rtc->max_user_freq = 32768;
515 else 558 else
@@ -523,6 +566,10 @@ static int __devinit s3c_rtc_probe(struct platform_device *pdev)
523 566
524 err_nortc: 567 err_nortc:
525 s3c_rtc_enable(pdev, 0); 568 s3c_rtc_enable(pdev, 0);
569 clk_disable(rtc_clk);
570 clk_put(rtc_clk);
571
572 err_clk:
526 iounmap(s3c_rtc_base); 573 iounmap(s3c_rtc_base);
527 574
528 err_nomap: 575 err_nomap:
@@ -543,10 +590,14 @@ static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
543 /* save TICNT for anyone using periodic interrupts */ 590 /* save TICNT for anyone using periodic interrupts */
544 ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT); 591 ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
545 if (s3c_rtc_cpu_type == TYPE_S3C64XX) { 592 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
546 ticnt_en_save = readb(s3c_rtc_base + S3C2410_RTCCON); 593 ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
547 ticnt_en_save &= S3C64XX_RTCCON_TICEN; 594 ticnt_en_save &= S3C64XX_RTCCON_TICEN;
548 } 595 }
549 s3c_rtc_enable(pdev, 0); 596 s3c_rtc_enable(pdev, 0);
597
598 if (device_may_wakeup(&pdev->dev))
599 enable_irq_wake(s3c_rtc_alarmno);
600
550 return 0; 601 return 0;
551} 602}
552 603
@@ -557,9 +608,13 @@ static int s3c_rtc_resume(struct platform_device *pdev)
557 s3c_rtc_enable(pdev, 1); 608 s3c_rtc_enable(pdev, 1);
558 writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT); 609 writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
559 if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) { 610 if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
560 tmp = readb(s3c_rtc_base + S3C2410_RTCCON); 611 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
561 writeb(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON); 612 writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
562 } 613 }
614
615 if (device_may_wakeup(&pdev->dev))
616 disable_irq_wake(s3c_rtc_alarmno);
617
563 return 0; 618 return 0;
564} 619}
565#else 620#else
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 16:20:25 -0400