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-rw-r--r--drivers/rtc/Kconfig46
-rw-r--r--drivers/rtc/Makefile3
-rw-r--r--drivers/rtc/rtc-bq32k.c62
-rw-r--r--drivers/rtc/rtc-cmos.c5
-rw-r--r--drivers/rtc/rtc-ds1307.c67
-rw-r--r--drivers/rtc/rtc-efi.c1
-rw-r--r--drivers/rtc/rtc-isl12022.c2
-rw-r--r--drivers/rtc/rtc-max77686.c140
-rw-r--r--drivers/rtc/rtc-max77802.c502
-rw-r--r--drivers/rtc/rtc-mpc5121.c2
-rw-r--r--drivers/rtc/rtc-pcf8563.c4
-rw-r--r--drivers/rtc/rtc-pcf8583.c18
-rw-r--r--drivers/rtc/rtc-pm8xxx.c222
-rw-r--r--drivers/rtc/rtc-rk808.c414
-rw-r--r--drivers/rtc/rtc-rs5c372.c11
-rw-r--r--drivers/rtc/rtc-s3c.c855
-rw-r--r--drivers/rtc/rtc-sun6i.c447
17 files changed, 2261 insertions, 540 deletions
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index a168e96142b9..6dd12ddbabc6 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -288,6 +288,26 @@ config RTC_DRV_MAX77686
288 This driver can also be built as a module. If so, the module 288 This driver can also be built as a module. If so, the module
289 will be called rtc-max77686. 289 will be called rtc-max77686.
290 290
291config RTC_DRV_RK808
292 tristate "Rockchip RK808 RTC"
293 depends on MFD_RK808
294 help
295 If you say yes here you will get support for the
296 RTC of RK808 PMIC.
297
298 This driver can also be built as a module. If so, the module
299 will be called rk808-rtc.
300
301config RTC_DRV_MAX77802
302 tristate "Maxim 77802 RTC"
303 depends on MFD_MAX77686
304 help
305 If you say yes here you will get support for the
306 RTC of Maxim MAX77802 PMIC.
307
308 This driver can also be built as a module. If so, the module
309 will be called rtc-max77802.
310
291config RTC_DRV_RS5C372 311config RTC_DRV_RS5C372
292 tristate "Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A" 312 tristate "Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A"
293 help 313 help
@@ -732,6 +752,7 @@ config RTC_DRV_DS1216
732 752
733config RTC_DRV_DS1286 753config RTC_DRV_DS1286
734 tristate "Dallas DS1286" 754 tristate "Dallas DS1286"
755 depends on HAS_IOMEM
735 help 756 help
736 If you say yes here you get support for the Dallas DS1286 RTC chips. 757 If you say yes here you get support for the Dallas DS1286 RTC chips.
737 758
@@ -743,6 +764,7 @@ config RTC_DRV_DS1302
743 764
744config RTC_DRV_DS1511 765config RTC_DRV_DS1511
745 tristate "Dallas DS1511" 766 tristate "Dallas DS1511"
767 depends on HAS_IOMEM
746 help 768 help
747 If you say yes here you get support for the 769 If you say yes here you get support for the
748 Dallas DS1511 timekeeping/watchdog chip. 770 Dallas DS1511 timekeeping/watchdog chip.
@@ -752,6 +774,7 @@ config RTC_DRV_DS1511
752 774
753config RTC_DRV_DS1553 775config RTC_DRV_DS1553
754 tristate "Maxim/Dallas DS1553" 776 tristate "Maxim/Dallas DS1553"
777 depends on HAS_IOMEM
755 help 778 help
756 If you say yes here you get support for the 779 If you say yes here you get support for the
757 Maxim/Dallas DS1553 timekeeping chip. 780 Maxim/Dallas DS1553 timekeeping chip.
@@ -761,6 +784,7 @@ config RTC_DRV_DS1553
761 784
762config RTC_DRV_DS1742 785config RTC_DRV_DS1742
763 tristate "Maxim/Dallas DS1742/1743" 786 tristate "Maxim/Dallas DS1742/1743"
787 depends on HAS_IOMEM
764 help 788 help
765 If you say yes here you get support for the 789 If you say yes here you get support for the
766 Maxim/Dallas DS1742/1743 timekeeping chip. 790 Maxim/Dallas DS1742/1743 timekeeping chip.
@@ -806,7 +830,7 @@ config RTC_DRV_DA9063
806 830
807config RTC_DRV_EFI 831config RTC_DRV_EFI
808 tristate "EFI RTC" 832 tristate "EFI RTC"
809 depends on EFI 833 depends on EFI && !X86
810 help 834 help
811 If you say yes here you will get support for the EFI 835 If you say yes here you will get support for the EFI
812 Real Time Clock. 836 Real Time Clock.
@@ -816,6 +840,7 @@ config RTC_DRV_EFI
816 840
817config RTC_DRV_STK17TA8 841config RTC_DRV_STK17TA8
818 tristate "Simtek STK17TA8" 842 tristate "Simtek STK17TA8"
843 depends on HAS_IOMEM
819 help 844 help
820 If you say yes here you get support for the 845 If you say yes here you get support for the
821 Simtek STK17TA8 timekeeping chip. 846 Simtek STK17TA8 timekeeping chip.
@@ -834,6 +859,7 @@ config RTC_DRV_M48T86
834 859
835config RTC_DRV_M48T35 860config RTC_DRV_M48T35
836 tristate "ST M48T35" 861 tristate "ST M48T35"
862 depends on HAS_IOMEM
837 help 863 help
838 If you say Y here you will get support for the 864 If you say Y here you will get support for the
839 ST M48T35 RTC chip. 865 ST M48T35 RTC chip.
@@ -843,6 +869,7 @@ config RTC_DRV_M48T35
843 869
844config RTC_DRV_M48T59 870config RTC_DRV_M48T59
845 tristate "ST M48T59/M48T08/M48T02" 871 tristate "ST M48T59/M48T08/M48T02"
872 depends on HAS_IOMEM
846 help 873 help
847 If you say Y here you will get support for the 874 If you say Y here you will get support for the
848 ST M48T59 RTC chip and compatible ST M48T08 and M48T02. 875 ST M48T59 RTC chip and compatible ST M48T08 and M48T02.
@@ -855,6 +882,7 @@ config RTC_DRV_M48T59
855 882
856config RTC_DRV_MSM6242 883config RTC_DRV_MSM6242
857 tristate "Oki MSM6242" 884 tristate "Oki MSM6242"
885 depends on HAS_IOMEM
858 help 886 help
859 If you say yes here you get support for the Oki MSM6242 887 If you say yes here you get support for the Oki MSM6242
860 timekeeping chip. It is used in some Amiga models (e.g. A2000). 888 timekeeping chip. It is used in some Amiga models (e.g. A2000).
@@ -864,6 +892,7 @@ config RTC_DRV_MSM6242
864 892
865config RTC_DRV_BQ4802 893config RTC_DRV_BQ4802
866 tristate "TI BQ4802" 894 tristate "TI BQ4802"
895 depends on HAS_IOMEM
867 help 896 help
868 If you say Y here you will get support for the TI 897 If you say Y here you will get support for the TI
869 BQ4802 RTC chip. 898 BQ4802 RTC chip.
@@ -873,6 +902,7 @@ config RTC_DRV_BQ4802
873 902
874config RTC_DRV_RP5C01 903config RTC_DRV_RP5C01
875 tristate "Ricoh RP5C01" 904 tristate "Ricoh RP5C01"
905 depends on HAS_IOMEM
876 help 906 help
877 If you say yes here you get support for the Ricoh RP5C01 907 If you say yes here you get support for the Ricoh RP5C01
878 timekeeping chip. It is used in some Amiga models (e.g. A3000 908 timekeeping chip. It is used in some Amiga models (e.g. A3000
@@ -1175,9 +1205,16 @@ config RTC_DRV_SUN4V
1175 If you say Y here you will get support for the Hypervisor 1205 If you say Y here you will get support for the Hypervisor
1176 based RTC on SUN4V systems. 1206 based RTC on SUN4V systems.
1177 1207
1208config RTC_DRV_SUN6I
1209 tristate "Allwinner A31 RTC"
1210 depends on MACH_SUN6I || MACH_SUN8I
1211 help
1212 If you say Y here you will get support for the RTC found on
1213 Allwinner A31.
1214
1178config RTC_DRV_SUNXI 1215config RTC_DRV_SUNXI
1179 tristate "Allwinner sun4i/sun7i RTC" 1216 tristate "Allwinner sun4i/sun7i RTC"
1180 depends on ARCH_SUNXI 1217 depends on MACH_SUN4I || MACH_SUN7I
1181 help 1218 help
1182 If you say Y here you will get support for the RTC found on 1219 If you say Y here you will get support for the RTC found on
1183 Allwinner A10/A20. 1220 Allwinner A10/A20.
@@ -1198,7 +1235,7 @@ config RTC_DRV_TX4939
1198 1235
1199config RTC_DRV_MV 1236config RTC_DRV_MV
1200 tristate "Marvell SoC RTC" 1237 tristate "Marvell SoC RTC"
1201 depends on ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU 1238 depends on ARCH_DOVE || ARCH_MVEBU
1202 help 1239 help
1203 If you say yes here you will get support for the in-chip RTC 1240 If you say yes here you will get support for the in-chip RTC
1204 that can be found in some of Marvell's SoC devices, such as 1241 that can be found in some of Marvell's SoC devices, such as
@@ -1283,7 +1320,7 @@ config RTC_DRV_LPC32XX
1283 1320
1284config RTC_DRV_PM8XXX 1321config RTC_DRV_PM8XXX
1285 tristate "Qualcomm PMIC8XXX RTC" 1322 tristate "Qualcomm PMIC8XXX RTC"
1286 depends on MFD_PM8XXX 1323 depends on MFD_PM8XXX || MFD_SPMI_PMIC
1287 help 1324 help
1288 If you say yes here you get support for the 1325 If you say yes here you get support for the
1289 Qualcomm PMIC8XXX RTC. 1326 Qualcomm PMIC8XXX RTC.
@@ -1367,6 +1404,7 @@ config RTC_DRV_MOXART
1367 1404
1368config RTC_DRV_XGENE 1405config RTC_DRV_XGENE
1369 tristate "APM X-Gene RTC" 1406 tristate "APM X-Gene RTC"
1407 depends on HAS_IOMEM
1370 help 1408 help
1371 If you say yes here you get support for the APM X-Gene SoC real time 1409 If you say yes here you get support for the APM X-Gene SoC real time
1372 clock. 1410 clock.
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 56f061c7c815..b188323c096a 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_RTC_DRV_MAX8998) += rtc-max8998.o
85obj-$(CONFIG_RTC_DRV_MAX8997) += rtc-max8997.o 85obj-$(CONFIG_RTC_DRV_MAX8997) += rtc-max8997.o
86obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o 86obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o
87obj-$(CONFIG_RTC_DRV_MAX77686) += rtc-max77686.o 87obj-$(CONFIG_RTC_DRV_MAX77686) += rtc-max77686.o
88obj-$(CONFIG_RTC_DRV_MAX77802) += rtc-max77802.o
88obj-$(CONFIG_RTC_DRV_MC13XXX) += rtc-mc13xxx.o 89obj-$(CONFIG_RTC_DRV_MC13XXX) += rtc-mc13xxx.o
89obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o 90obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o
90obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o 91obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
@@ -109,6 +110,7 @@ obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o
109obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o 110obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o
110obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o 111obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o
111obj-$(CONFIG_RTC_DRV_RC5T583) += rtc-rc5t583.o 112obj-$(CONFIG_RTC_DRV_RC5T583) += rtc-rc5t583.o
113obj-$(CONFIG_RTC_DRV_RK808) += rtc-rk808.o
112obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c01.o 114obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c01.o
113obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o 115obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o
114obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o 116obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o
@@ -128,6 +130,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
128obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o 130obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
129obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o 131obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
130obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o 132obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
133obj-$(CONFIG_RTC_DRV_SUN6I) += rtc-sun6i.o
131obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o 134obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o
132obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o 135obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
133obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o 136obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
diff --git a/drivers/rtc/rtc-bq32k.c b/drivers/rtc/rtc-bq32k.c
index c74bf0dc52cc..92679df6d6e2 100644
--- a/drivers/rtc/rtc-bq32k.c
+++ b/drivers/rtc/rtc-bq32k.c
@@ -2,10 +2,14 @@
2 * Driver for TI BQ32000 RTC. 2 * Driver for TI BQ32000 RTC.
3 * 3 *
4 * Copyright (C) 2009 Semihalf. 4 * Copyright (C) 2009 Semihalf.
5 * Copyright (C) 2014 Pavel Machek <pavel@denx.de>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 *
11 * You can get hardware description at
12 * http://www.ti.com/lit/ds/symlink/bq32000.pdf
9 */ 13 */
10 14
11#include <linux/module.h> 15#include <linux/module.h>
@@ -27,6 +31,10 @@
27#define BQ32K_CENT 0x40 /* Century flag */ 31#define BQ32K_CENT 0x40 /* Century flag */
28#define BQ32K_CENT_EN 0x80 /* Century flag enable bit */ 32#define BQ32K_CENT_EN 0x80 /* Century flag enable bit */
29 33
34#define BQ32K_CALIBRATION 0x07 /* CAL_CFG1, calibration and control */
35#define BQ32K_TCH2 0x08 /* Trickle charge enable */
36#define BQ32K_CFG2 0x09 /* Trickle charger control */
37
30struct bq32k_regs { 38struct bq32k_regs {
31 uint8_t seconds; 39 uint8_t seconds;
32 uint8_t minutes; 40 uint8_t minutes;
@@ -122,6 +130,57 @@ static const struct rtc_class_ops bq32k_rtc_ops = {
122 .set_time = bq32k_rtc_set_time, 130 .set_time = bq32k_rtc_set_time,
123}; 131};
124 132
133static int trickle_charger_of_init(struct device *dev, struct device_node *node)
134{
135 unsigned char reg;
136 int error;
137 u32 ohms = 0;
138
139 if (of_property_read_u32(node, "trickle-resistor-ohms" , &ohms))
140 return 0;
141
142 switch (ohms) {
143 case 180+940:
144 /*
145 * TCHE[3:0] == 0x05, TCH2 == 1, TCFE == 0 (charging
146 * over diode and 940ohm resistor)
147 */
148
149 if (of_property_read_bool(node, "trickle-diode-disable")) {
150 dev_err(dev, "diode and resistor mismatch\n");
151 return -EINVAL;
152 }
153 reg = 0x05;
154 break;
155
156 case 180+20000:
157 /* diode disabled */
158
159 if (!of_property_read_bool(node, "trickle-diode-disable")) {
160 dev_err(dev, "bq32k: diode and resistor mismatch\n");
161 return -EINVAL;
162 }
163 reg = 0x45;
164 break;
165
166 default:
167 dev_err(dev, "invalid resistor value (%d)\n", ohms);
168 return -EINVAL;
169 }
170
171 error = bq32k_write(dev, &reg, BQ32K_CFG2, 1);
172 if (error)
173 return error;
174
175 reg = 0x20;
176 error = bq32k_write(dev, &reg, BQ32K_TCH2, 1);
177 if (error)
178 return error;
179
180 dev_info(dev, "Enabled trickle RTC battery charge.\n");
181 return 0;
182}
183
125static int bq32k_probe(struct i2c_client *client, 184static int bq32k_probe(struct i2c_client *client,
126 const struct i2c_device_id *id) 185 const struct i2c_device_id *id)
127{ 186{
@@ -153,6 +212,9 @@ static int bq32k_probe(struct i2c_client *client,
153 if (error) 212 if (error)
154 return error; 213 return error;
155 214
215 if (client && client->dev.of_node)
216 trickle_charger_of_init(dev, client->dev.of_node);
217
156 rtc = devm_rtc_device_register(&client->dev, bq32k_driver.driver.name, 218 rtc = devm_rtc_device_register(&client->dev, bq32k_driver.driver.name,
157 &bq32k_rtc_ops, THIS_MODULE); 219 &bq32k_rtc_ops, THIS_MODULE);
158 if (IS_ERR(rtc)) 220 if (IS_ERR(rtc))
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index b0e4a3eb33c7..5b2e76159b41 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -856,7 +856,7 @@ static void __exit cmos_do_remove(struct device *dev)
856 cmos->dev = NULL; 856 cmos->dev = NULL;
857} 857}
858 858
859#ifdef CONFIG_PM_SLEEP 859#ifdef CONFIG_PM
860 860
861static int cmos_suspend(struct device *dev) 861static int cmos_suspend(struct device *dev)
862{ 862{
@@ -907,6 +907,8 @@ static inline int cmos_poweroff(struct device *dev)
907 return cmos_suspend(dev); 907 return cmos_suspend(dev);
908} 908}
909 909
910#ifdef CONFIG_PM_SLEEP
911
910static int cmos_resume(struct device *dev) 912static int cmos_resume(struct device *dev)
911{ 913{
912 struct cmos_rtc *cmos = dev_get_drvdata(dev); 914 struct cmos_rtc *cmos = dev_get_drvdata(dev);
@@ -954,6 +956,7 @@ static int cmos_resume(struct device *dev)
954 return 0; 956 return 0;
955} 957}
956 958
959#endif
957#else 960#else
958 961
959static inline int cmos_poweroff(struct device *dev) 962static inline int cmos_poweroff(struct device *dev)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index f03d5ba96db1..bb43cf703efc 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -126,9 +126,14 @@ struct chip_desc {
126 u16 nvram_offset; 126 u16 nvram_offset;
127 u16 nvram_size; 127 u16 nvram_size;
128 u16 trickle_charger_reg; 128 u16 trickle_charger_reg;
129 u8 trickle_charger_setup;
130 u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
129}; 131};
130 132
131static const struct chip_desc chips[last_ds_type] = { 133static u8 do_trickle_setup_ds1339(struct i2c_client *,
134 uint32_t ohms, bool diode);
135
136static struct chip_desc chips[last_ds_type] = {
132 [ds_1307] = { 137 [ds_1307] = {
133 .nvram_offset = 8, 138 .nvram_offset = 8,
134 .nvram_size = 56, 139 .nvram_size = 56,
@@ -143,6 +148,7 @@ static const struct chip_desc chips[last_ds_type] = {
143 [ds_1339] = { 148 [ds_1339] = {
144 .alarm = 1, 149 .alarm = 1,
145 .trickle_charger_reg = 0x10, 150 .trickle_charger_reg = 0x10,
151 .do_trickle_setup = &do_trickle_setup_ds1339,
146 }, 152 },
147 [ds_1340] = { 153 [ds_1340] = {
148 .trickle_charger_reg = 0x08, 154 .trickle_charger_reg = 0x08,
@@ -833,15 +839,58 @@ ds1307_nvram_write(struct file *filp, struct kobject *kobj,
833 return count; 839 return count;
834} 840}
835 841
842
836/*----------------------------------------------------------------------*/ 843/*----------------------------------------------------------------------*/
837 844
845static u8 do_trickle_setup_ds1339(struct i2c_client *client,
846 uint32_t ohms, bool diode)
847{
848 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
849 DS1307_TRICKLE_CHARGER_NO_DIODE;
850
851 switch (ohms) {
852 case 250:
853 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
854 break;
855 case 2000:
856 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
857 break;
858 case 4000:
859 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
860 break;
861 default:
862 dev_warn(&client->dev,
863 "Unsupported ohm value %u in dt\n", ohms);
864 return 0;
865 }
866 return setup;
867}
868
869static void ds1307_trickle_of_init(struct i2c_client *client,
870 struct chip_desc *chip)
871{
872 uint32_t ohms = 0;
873 bool diode = true;
874
875 if (!chip->do_trickle_setup)
876 goto out;
877 if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms))
878 goto out;
879 if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
880 diode = false;
881 chip->trickle_charger_setup = chip->do_trickle_setup(client,
882 ohms, diode);
883out:
884 return;
885}
886
838static int ds1307_probe(struct i2c_client *client, 887static int ds1307_probe(struct i2c_client *client,
839 const struct i2c_device_id *id) 888 const struct i2c_device_id *id)
840{ 889{
841 struct ds1307 *ds1307; 890 struct ds1307 *ds1307;
842 int err = -ENODEV; 891 int err = -ENODEV;
843 int tmp; 892 int tmp;
844 const struct chip_desc *chip = &chips[id->driver_data]; 893 struct chip_desc *chip = &chips[id->driver_data];
845 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 894 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
846 bool want_irq = false; 895 bool want_irq = false;
847 unsigned char *buf; 896 unsigned char *buf;
@@ -866,9 +915,19 @@ static int ds1307_probe(struct i2c_client *client,
866 ds1307->client = client; 915 ds1307->client = client;
867 ds1307->type = id->driver_data; 916 ds1307->type = id->driver_data;
868 917
869 if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg) 918 if (!pdata && client->dev.of_node)
919 ds1307_trickle_of_init(client, chip);
920 else if (pdata && pdata->trickle_charger_setup)
921 chip->trickle_charger_setup = pdata->trickle_charger_setup;
922
923 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
924 dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
925 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
926 chip->trickle_charger_reg);
870 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg, 927 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
871 DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup); 928 DS13XX_TRICKLE_CHARGER_MAGIC |
929 chip->trickle_charger_setup);
930 }
872 931
873 buf = ds1307->regs; 932 buf = ds1307->regs;
874 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) { 933 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
diff --git a/drivers/rtc/rtc-efi.c b/drivers/rtc/rtc-efi.c
index c384fec6d173..53b589dc34eb 100644
--- a/drivers/rtc/rtc-efi.c
+++ b/drivers/rtc/rtc-efi.c
@@ -236,3 +236,4 @@ MODULE_ALIAS("platform:rtc-efi");
236MODULE_AUTHOR("dann frazier <dannf@hp.com>"); 236MODULE_AUTHOR("dann frazier <dannf@hp.com>");
237MODULE_LICENSE("GPL"); 237MODULE_LICENSE("GPL");
238MODULE_DESCRIPTION("EFI RTC driver"); 238MODULE_DESCRIPTION("EFI RTC driver");
239MODULE_ALIAS("platform:rtc-efi");
diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c
index aa55f081c505..ee3ba7e6b45e 100644
--- a/drivers/rtc/rtc-isl12022.c
+++ b/drivers/rtc/rtc-isl12022.c
@@ -274,7 +274,7 @@ static int isl12022_probe(struct i2c_client *client,
274} 274}
275 275
276#ifdef CONFIG_OF 276#ifdef CONFIG_OF
277static struct of_device_id isl12022_dt_match[] = { 277static const struct of_device_id isl12022_dt_match[] = {
278 { .compatible = "isl,isl12022" }, 278 { .compatible = "isl,isl12022" },
279 { }, 279 { },
280}; 280};
diff --git a/drivers/rtc/rtc-max77686.c b/drivers/rtc/rtc-max77686.c
index d20a7f0786eb..cf73e969c8cc 100644
--- a/drivers/rtc/rtc-max77686.c
+++ b/drivers/rtc/rtc-max77686.c
@@ -32,15 +32,6 @@
32#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT) 32#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
33#define RTC_RBUDR_SHIFT 4 33#define RTC_RBUDR_SHIFT 4
34#define RTC_RBUDR_MASK (1 << RTC_RBUDR_SHIFT) 34#define RTC_RBUDR_MASK (1 << RTC_RBUDR_SHIFT)
35/* WTSR and SMPL Register */
36#define WTSRT_SHIFT 0
37#define SMPLT_SHIFT 2
38#define WTSR_EN_SHIFT 6
39#define SMPL_EN_SHIFT 7
40#define WTSRT_MASK (3 << WTSRT_SHIFT)
41#define SMPLT_MASK (3 << SMPLT_SHIFT)
42#define WTSR_EN_MASK (1 << WTSR_EN_SHIFT)
43#define SMPL_EN_MASK (1 << SMPL_EN_SHIFT)
44/* RTC Hour register */ 35/* RTC Hour register */
45#define HOUR_PM_SHIFT 6 36#define HOUR_PM_SHIFT 6
46#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT) 37#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
@@ -49,7 +40,6 @@
49#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT) 40#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
50 41
51#define MAX77686_RTC_UPDATE_DELAY 16 42#define MAX77686_RTC_UPDATE_DELAY 16
52#undef MAX77686_RTC_WTSR_SMPL
53 43
54enum { 44enum {
55 RTC_SEC = 0, 45 RTC_SEC = 0,
@@ -80,16 +70,6 @@ enum MAX77686_RTC_OP {
80 MAX77686_RTC_READ, 70 MAX77686_RTC_READ,
81}; 71};
82 72
83static inline int max77686_rtc_calculate_wday(u8 shifted)
84{
85 int counter = -1;
86 while (shifted) {
87 shifted >>= 1;
88 counter++;
89 }
90 return counter;
91}
92
93static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm, 73static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
94 int rtc_24hr_mode) 74 int rtc_24hr_mode)
95{ 75{
@@ -103,7 +83,8 @@ static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
103 tm->tm_hour += 12; 83 tm->tm_hour += 12;
104 } 84 }
105 85
106 tm->tm_wday = max77686_rtc_calculate_wday(data[RTC_WEEKDAY] & 0x7f); 86 /* Only a single bit is set in data[], so fls() would be equivalent */
87 tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f) - 1;
107 tm->tm_mday = data[RTC_DATE] & 0x1f; 88 tm->tm_mday = data[RTC_DATE] & 0x1f;
108 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; 89 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
109 tm->tm_year = (data[RTC_YEAR] & 0x7f) + 100; 90 tm->tm_year = (data[RTC_YEAR] & 0x7f) + 100;
@@ -412,64 +393,6 @@ static const struct rtc_class_ops max77686_rtc_ops = {
412 .alarm_irq_enable = max77686_rtc_alarm_irq_enable, 393 .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
413}; 394};
414 395
415#ifdef MAX77686_RTC_WTSR_SMPL
416static void max77686_rtc_enable_wtsr(struct max77686_rtc_info *info, bool enable)
417{
418 int ret;
419 unsigned int val, mask;
420
421 if (enable)
422 val = (1 << WTSR_EN_SHIFT) | (3 << WTSRT_SHIFT);
423 else
424 val = 0;
425
426 mask = WTSR_EN_MASK | WTSRT_MASK;
427
428 dev_info(info->dev, "%s: %s WTSR\n", __func__,
429 enable ? "enable" : "disable");
430
431 ret = regmap_update_bits(info->max77686->rtc_regmap,
432 MAX77686_WTSR_SMPL_CNTL, mask, val);
433 if (ret < 0) {
434 dev_err(info->dev, "%s: fail to update WTSR reg(%d)\n",
435 __func__, ret);
436 return;
437 }
438
439 max77686_rtc_update(info, MAX77686_RTC_WRITE);
440}
441
442static void max77686_rtc_enable_smpl(struct max77686_rtc_info *info, bool enable)
443{
444 int ret;
445 unsigned int val, mask;
446
447 if (enable)
448 val = (1 << SMPL_EN_SHIFT) | (0 << SMPLT_SHIFT);
449 else
450 val = 0;
451
452 mask = SMPL_EN_MASK | SMPLT_MASK;
453
454 dev_info(info->dev, "%s: %s SMPL\n", __func__,
455 enable ? "enable" : "disable");
456
457 ret = regmap_update_bits(info->max77686->rtc_regmap,
458 MAX77686_WTSR_SMPL_CNTL, mask, val);
459 if (ret < 0) {
460 dev_err(info->dev, "%s: fail to update SMPL reg(%d)\n",
461 __func__, ret);
462 return;
463 }
464
465 max77686_rtc_update(info, MAX77686_RTC_WRITE);
466
467 val = 0;
468 regmap_read(info->max77686->rtc_regmap, MAX77686_WTSR_SMPL_CNTL, &val);
469 dev_info(info->dev, "%s: WTSR_SMPL(0x%02x)\n", __func__, val);
470}
471#endif /* MAX77686_RTC_WTSR_SMPL */
472
473static int max77686_rtc_init_reg(struct max77686_rtc_info *info) 396static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
474{ 397{
475 u8 data[2]; 398 u8 data[2];
@@ -519,19 +442,12 @@ static int max77686_rtc_probe(struct platform_device *pdev)
519 goto err_rtc; 442 goto err_rtc;
520 } 443 }
521 444
522#ifdef MAX77686_RTC_WTSR_SMPL
523 max77686_rtc_enable_wtsr(info, true);
524 max77686_rtc_enable_smpl(info, true);
525#endif
526
527 device_init_wakeup(&pdev->dev, 1); 445 device_init_wakeup(&pdev->dev, 1);
528 446
529 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "max77686-rtc", 447 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "max77686-rtc",
530 &max77686_rtc_ops, THIS_MODULE); 448 &max77686_rtc_ops, THIS_MODULE);
531 449
532 if (IS_ERR(info->rtc_dev)) { 450 if (IS_ERR(info->rtc_dev)) {
533 dev_info(&pdev->dev, "%s: fail\n", __func__);
534
535 ret = PTR_ERR(info->rtc_dev); 451 ret = PTR_ERR(info->rtc_dev);
536 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); 452 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
537 if (ret == 0) 453 if (ret == 0)
@@ -539,6 +455,12 @@ static int max77686_rtc_probe(struct platform_device *pdev)
539 goto err_rtc; 455 goto err_rtc;
540 } 456 }
541 457
458 if (!max77686->rtc_irq_data) {
459 ret = -EINVAL;
460 dev_err(&pdev->dev, "%s: no RTC regmap IRQ chip\n", __func__);
461 goto err_rtc;
462 }
463
542 info->virq = regmap_irq_get_virq(max77686->rtc_irq_data, 464 info->virq = regmap_irq_get_virq(max77686->rtc_irq_data,
543 MAX77686_RTCIRQ_RTCA1); 465 MAX77686_RTCIRQ_RTCA1);
544 if (!info->virq) { 466 if (!info->virq) {
@@ -556,33 +478,33 @@ err_rtc:
556 return ret; 478 return ret;
557} 479}
558 480
559static void max77686_rtc_shutdown(struct platform_device *pdev) 481#ifdef CONFIG_PM_SLEEP
482static int max77686_rtc_suspend(struct device *dev)
560{ 483{
561#ifdef MAX77686_RTC_WTSR_SMPL 484 if (device_may_wakeup(dev)) {
562 struct max77686_rtc_info *info = platform_get_drvdata(pdev); 485 struct max77686_rtc_info *info = dev_get_drvdata(dev);
563 int i; 486
564 u8 val = 0; 487 return enable_irq_wake(info->virq);
565
566 for (i = 0; i < 3; i++) {
567 max77686_rtc_enable_wtsr(info, false);
568 regmap_read(info->max77686->rtc_regmap, MAX77686_WTSR_SMPL_CNTL, &val);
569 dev_info(info->dev, "%s: WTSR_SMPL reg(0x%02x)\n", __func__,
570 val);
571 if (val & WTSR_EN_MASK) {
572 dev_emerg(info->dev, "%s: fail to disable WTSR\n",
573 __func__);
574 } else {
575 dev_info(info->dev, "%s: success to disable WTSR\n",
576 __func__);
577 break;
578 }
579 } 488 }
580 489
581 /* Disable SMPL when power off */ 490 return 0;
582 max77686_rtc_enable_smpl(info, false);
583#endif /* MAX77686_RTC_WTSR_SMPL */
584} 491}
585 492
493static int max77686_rtc_resume(struct device *dev)
494{
495 if (device_may_wakeup(dev)) {
496 struct max77686_rtc_info *info = dev_get_drvdata(dev);
497
498 return disable_irq_wake(info->virq);
499 }
500
501 return 0;
502}
503#endif
504
505static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
506 max77686_rtc_suspend, max77686_rtc_resume);
507
586static const struct platform_device_id rtc_id[] = { 508static const struct platform_device_id rtc_id[] = {
587 { "max77686-rtc", 0 }, 509 { "max77686-rtc", 0 },
588 {}, 510 {},
@@ -592,9 +514,9 @@ static struct platform_driver max77686_rtc_driver = {
592 .driver = { 514 .driver = {
593 .name = "max77686-rtc", 515 .name = "max77686-rtc",
594 .owner = THIS_MODULE, 516 .owner = THIS_MODULE,
517 .pm = &max77686_rtc_pm_ops,
595 }, 518 },
596 .probe = max77686_rtc_probe, 519 .probe = max77686_rtc_probe,
597 .shutdown = max77686_rtc_shutdown,
598 .id_table = rtc_id, 520 .id_table = rtc_id,
599}; 521};
600 522
diff --git a/drivers/rtc/rtc-max77802.c b/drivers/rtc/rtc-max77802.c
new file mode 100644
index 000000000000..566471335b33
--- /dev/null
+++ b/drivers/rtc/rtc-max77802.c
@@ -0,0 +1,502 @@
1/*
2 * RTC driver for Maxim MAX77802
3 *
4 * Copyright (C) 2013 Google, Inc
5 *
6 * Copyright (C) 2012 Samsung Electronics Co.Ltd
7 *
8 * based on rtc-max8997.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <linux/slab.h>
18#include <linux/rtc.h>
19#include <linux/delay.h>
20#include <linux/mutex.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/mfd/max77686-private.h>
24#include <linux/irqdomain.h>
25#include <linux/regmap.h>
26
27/* RTC Control Register */
28#define BCD_EN_SHIFT 0
29#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
30#define MODEL24_SHIFT 1
31#define MODEL24_MASK (1 << MODEL24_SHIFT)
32/* RTC Update Register1 */
33#define RTC_UDR_SHIFT 0
34#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
35#define RTC_RBUDR_SHIFT 4
36#define RTC_RBUDR_MASK (1 << RTC_RBUDR_SHIFT)
37/* RTC Hour register */
38#define HOUR_PM_SHIFT 6
39#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
40/* RTC Alarm Enable */
41#define ALARM_ENABLE_SHIFT 7
42#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
43
44/* For the RTCAE1 register, we write this value to enable the alarm */
45#define ALARM_ENABLE_VALUE 0x77
46
47#define MAX77802_RTC_UPDATE_DELAY_US 200
48
49enum {
50 RTC_SEC = 0,
51 RTC_MIN,
52 RTC_HOUR,
53 RTC_WEEKDAY,
54 RTC_MONTH,
55 RTC_YEAR,
56 RTC_DATE,
57 RTC_NR_TIME
58};
59
60struct max77802_rtc_info {
61 struct device *dev;
62 struct max77686_dev *max77802;
63 struct i2c_client *rtc;
64 struct rtc_device *rtc_dev;
65 struct mutex lock;
66
67 struct regmap *regmap;
68
69 int virq;
70 int rtc_24hr_mode;
71};
72
73enum MAX77802_RTC_OP {
74 MAX77802_RTC_WRITE,
75 MAX77802_RTC_READ,
76};
77
78static void max77802_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
79 int rtc_24hr_mode)
80{
81 tm->tm_sec = data[RTC_SEC] & 0xff;
82 tm->tm_min = data[RTC_MIN] & 0xff;
83 if (rtc_24hr_mode)
84 tm->tm_hour = data[RTC_HOUR] & 0x1f;
85 else {
86 tm->tm_hour = data[RTC_HOUR] & 0x0f;
87 if (data[RTC_HOUR] & HOUR_PM_MASK)
88 tm->tm_hour += 12;
89 }
90
91 /* Only a single bit is set in data[], so fls() would be equivalent */
92 tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0xff) - 1;
93 tm->tm_mday = data[RTC_DATE] & 0x1f;
94 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
95
96 tm->tm_year = data[RTC_YEAR] & 0xff;
97 tm->tm_yday = 0;
98 tm->tm_isdst = 0;
99}
100
101static int max77802_rtc_tm_to_data(struct rtc_time *tm, u8 *data)
102{
103 data[RTC_SEC] = tm->tm_sec;
104 data[RTC_MIN] = tm->tm_min;
105 data[RTC_HOUR] = tm->tm_hour;
106 data[RTC_WEEKDAY] = 1 << tm->tm_wday;
107 data[RTC_DATE] = tm->tm_mday;
108 data[RTC_MONTH] = tm->tm_mon + 1;
109 data[RTC_YEAR] = tm->tm_year;
110
111 return 0;
112}
113
114static int max77802_rtc_update(struct max77802_rtc_info *info,
115 enum MAX77802_RTC_OP op)
116{
117 int ret;
118 unsigned int data;
119
120 if (op == MAX77802_RTC_WRITE)
121 data = 1 << RTC_UDR_SHIFT;
122 else
123 data = 1 << RTC_RBUDR_SHIFT;
124
125 ret = regmap_update_bits(info->max77802->regmap,
126 MAX77802_RTC_UPDATE0, data, data);
127 if (ret < 0)
128 dev_err(info->dev, "%s: fail to write update reg(ret=%d, data=0x%x)\n",
129 __func__, ret, data);
130 else {
131 /* Minimum delay required before RTC update. */
132 usleep_range(MAX77802_RTC_UPDATE_DELAY_US,
133 MAX77802_RTC_UPDATE_DELAY_US * 2);
134 }
135
136 return ret;
137}
138
139static int max77802_rtc_read_time(struct device *dev, struct rtc_time *tm)
140{
141 struct max77802_rtc_info *info = dev_get_drvdata(dev);
142 u8 data[RTC_NR_TIME];
143 int ret;
144
145 mutex_lock(&info->lock);
146
147 ret = max77802_rtc_update(info, MAX77802_RTC_READ);
148 if (ret < 0)
149 goto out;
150
151 ret = regmap_bulk_read(info->max77802->regmap,
152 MAX77802_RTC_SEC, data, RTC_NR_TIME);
153 if (ret < 0) {
154 dev_err(info->dev, "%s: fail to read time reg(%d)\n", __func__,
155 ret);
156 goto out;
157 }
158
159 max77802_rtc_data_to_tm(data, tm, info->rtc_24hr_mode);
160
161 ret = rtc_valid_tm(tm);
162
163out:
164 mutex_unlock(&info->lock);
165 return ret;
166}
167
168static int max77802_rtc_set_time(struct device *dev, struct rtc_time *tm)
169{
170 struct max77802_rtc_info *info = dev_get_drvdata(dev);
171 u8 data[RTC_NR_TIME];
172 int ret;
173
174 ret = max77802_rtc_tm_to_data(tm, data);
175 if (ret < 0)
176 return ret;
177
178 mutex_lock(&info->lock);
179
180 ret = regmap_bulk_write(info->max77802->regmap,
181 MAX77802_RTC_SEC, data, RTC_NR_TIME);
182 if (ret < 0) {
183 dev_err(info->dev, "%s: fail to write time reg(%d)\n", __func__,
184 ret);
185 goto out;
186 }
187
188 ret = max77802_rtc_update(info, MAX77802_RTC_WRITE);
189
190out:
191 mutex_unlock(&info->lock);
192 return ret;
193}
194
195static int max77802_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
196{
197 struct max77802_rtc_info *info = dev_get_drvdata(dev);
198 u8 data[RTC_NR_TIME];
199 unsigned int val;
200 int ret;
201
202 mutex_lock(&info->lock);
203
204 ret = max77802_rtc_update(info, MAX77802_RTC_READ);
205 if (ret < 0)
206 goto out;
207
208 ret = regmap_bulk_read(info->max77802->regmap,
209 MAX77802_ALARM1_SEC, data, RTC_NR_TIME);
210 if (ret < 0) {
211 dev_err(info->dev, "%s:%d fail to read alarm reg(%d)\n",
212 __func__, __LINE__, ret);
213 goto out;
214 }
215
216 max77802_rtc_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
217
218 alrm->enabled = 0;
219 ret = regmap_read(info->max77802->regmap,
220 MAX77802_RTC_AE1, &val);
221 if (ret < 0) {
222 dev_err(info->dev, "%s:%d fail to read alarm enable(%d)\n",
223 __func__, __LINE__, ret);
224 goto out;
225 }
226 if (val)
227 alrm->enabled = 1;
228
229 alrm->pending = 0;
230 ret = regmap_read(info->max77802->regmap, MAX77802_REG_STATUS2, &val);
231 if (ret < 0) {
232 dev_err(info->dev, "%s:%d fail to read status2 reg(%d)\n",
233 __func__, __LINE__, ret);
234 goto out;
235 }
236
237 if (val & (1 << 2)) /* RTCA1 */
238 alrm->pending = 1;
239
240out:
241 mutex_unlock(&info->lock);
242 return 0;
243}
244
245static int max77802_rtc_stop_alarm(struct max77802_rtc_info *info)
246{
247 int ret;
248
249 if (!mutex_is_locked(&info->lock))
250 dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
251
252 ret = max77802_rtc_update(info, MAX77802_RTC_READ);
253 if (ret < 0)
254 goto out;
255
256 ret = regmap_write(info->max77802->regmap,
257 MAX77802_RTC_AE1, 0);
258 if (ret < 0) {
259 dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
260 __func__, ret);
261 goto out;
262 }
263
264 ret = max77802_rtc_update(info, MAX77802_RTC_WRITE);
265out:
266 return ret;
267}
268
269static int max77802_rtc_start_alarm(struct max77802_rtc_info *info)
270{
271 int ret;
272
273 if (!mutex_is_locked(&info->lock))
274 dev_warn(info->dev, "%s: should have mutex locked\n",
275 __func__);
276
277 ret = max77802_rtc_update(info, MAX77802_RTC_READ);
278 if (ret < 0)
279 goto out;
280
281 ret = regmap_write(info->max77802->regmap,
282 MAX77802_RTC_AE1,
283 ALARM_ENABLE_VALUE);
284
285 if (ret < 0) {
286 dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
287 __func__, ret);
288 goto out;
289 }
290
291 ret = max77802_rtc_update(info, MAX77802_RTC_WRITE);
292out:
293 return ret;
294}
295
296static int max77802_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
297{
298 struct max77802_rtc_info *info = dev_get_drvdata(dev);
299 u8 data[RTC_NR_TIME];
300 int ret;
301
302 ret = max77802_rtc_tm_to_data(&alrm->time, data);
303 if (ret < 0)
304 return ret;
305
306 mutex_lock(&info->lock);
307
308 ret = max77802_rtc_stop_alarm(info);
309 if (ret < 0)
310 goto out;
311
312 ret = regmap_bulk_write(info->max77802->regmap,
313 MAX77802_ALARM1_SEC, data, RTC_NR_TIME);
314
315 if (ret < 0) {
316 dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
317 __func__, ret);
318 goto out;
319 }
320
321 ret = max77802_rtc_update(info, MAX77802_RTC_WRITE);
322 if (ret < 0)
323 goto out;
324
325 if (alrm->enabled)
326 ret = max77802_rtc_start_alarm(info);
327out:
328 mutex_unlock(&info->lock);
329 return ret;
330}
331
332static int max77802_rtc_alarm_irq_enable(struct device *dev,
333 unsigned int enabled)
334{
335 struct max77802_rtc_info *info = dev_get_drvdata(dev);
336 int ret;
337
338 mutex_lock(&info->lock);
339 if (enabled)
340 ret = max77802_rtc_start_alarm(info);
341 else
342 ret = max77802_rtc_stop_alarm(info);
343 mutex_unlock(&info->lock);
344
345 return ret;
346}
347
348static irqreturn_t max77802_rtc_alarm_irq(int irq, void *data)
349{
350 struct max77802_rtc_info *info = data;
351
352 dev_dbg(info->dev, "%s:irq(%d)\n", __func__, irq);
353
354 rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
355
356 return IRQ_HANDLED;
357}
358
359static const struct rtc_class_ops max77802_rtc_ops = {
360 .read_time = max77802_rtc_read_time,
361 .set_time = max77802_rtc_set_time,
362 .read_alarm = max77802_rtc_read_alarm,
363 .set_alarm = max77802_rtc_set_alarm,
364 .alarm_irq_enable = max77802_rtc_alarm_irq_enable,
365};
366
367static int max77802_rtc_init_reg(struct max77802_rtc_info *info)
368{
369 u8 data[2];
370 int ret;
371
372 max77802_rtc_update(info, MAX77802_RTC_READ);
373
374 /* Set RTC control register : Binary mode, 24hour mdoe */
375 data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
376 data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
377
378 info->rtc_24hr_mode = 1;
379
380 ret = regmap_bulk_write(info->max77802->regmap,
381 MAX77802_RTC_CONTROLM, data, ARRAY_SIZE(data));
382 if (ret < 0) {
383 dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
384 __func__, ret);
385 return ret;
386 }
387
388 ret = max77802_rtc_update(info, MAX77802_RTC_WRITE);
389 return ret;
390}
391
392static int max77802_rtc_probe(struct platform_device *pdev)
393{
394 struct max77686_dev *max77802 = dev_get_drvdata(pdev->dev.parent);
395 struct max77802_rtc_info *info;
396 int ret;
397
398 dev_dbg(&pdev->dev, "%s\n", __func__);
399
400 info = devm_kzalloc(&pdev->dev, sizeof(struct max77802_rtc_info),
401 GFP_KERNEL);
402 if (!info)
403 return -ENOMEM;
404
405 mutex_init(&info->lock);
406 info->dev = &pdev->dev;
407 info->max77802 = max77802;
408 info->rtc = max77802->i2c;
409
410 platform_set_drvdata(pdev, info);
411
412 ret = max77802_rtc_init_reg(info);
413
414 if (ret < 0) {
415 dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
416 return ret;
417 }
418
419 device_init_wakeup(&pdev->dev, 1);
420
421 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "max77802-rtc",
422 &max77802_rtc_ops, THIS_MODULE);
423
424 if (IS_ERR(info->rtc_dev)) {
425 ret = PTR_ERR(info->rtc_dev);
426 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
427 if (ret == 0)
428 ret = -EINVAL;
429 return ret;
430 }
431
432 if (!max77802->rtc_irq_data) {
433 dev_err(&pdev->dev, "No RTC regmap IRQ chip\n");
434 return -EINVAL;
435 }
436
437 info->virq = regmap_irq_get_virq(max77802->rtc_irq_data,
438 MAX77686_RTCIRQ_RTCA1);
439
440 if (info->virq <= 0) {
441 dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n",
442 MAX77686_RTCIRQ_RTCA1);
443 return -EINVAL;
444 }
445
446 ret = devm_request_threaded_irq(&pdev->dev, info->virq, NULL,
447 max77802_rtc_alarm_irq, 0, "rtc-alarm1",
448 info);
449 if (ret < 0)
450 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
451 info->virq, ret);
452
453 return ret;
454}
455
456#ifdef CONFIG_PM_SLEEP
457static int max77802_rtc_suspend(struct device *dev)
458{
459 if (device_may_wakeup(dev)) {
460 struct max77802_rtc_info *info = dev_get_drvdata(dev);
461
462 return enable_irq_wake(info->virq);
463 }
464
465 return 0;
466}
467
468static int max77802_rtc_resume(struct device *dev)
469{
470 if (device_may_wakeup(dev)) {
471 struct max77802_rtc_info *info = dev_get_drvdata(dev);
472
473 return disable_irq_wake(info->virq);
474 }
475
476 return 0;
477}
478#endif
479
480static SIMPLE_DEV_PM_OPS(max77802_rtc_pm_ops,
481 max77802_rtc_suspend, max77802_rtc_resume);
482
483static const struct platform_device_id rtc_id[] = {
484 { "max77802-rtc", 0 },
485 {},
486};
487
488static struct platform_driver max77802_rtc_driver = {
489 .driver = {
490 .name = "max77802-rtc",
491 .owner = THIS_MODULE,
492 .pm = &max77802_rtc_pm_ops,
493 },
494 .probe = max77802_rtc_probe,
495 .id_table = rtc_id,
496};
497
498module_platform_driver(max77802_rtc_driver);
499
500MODULE_DESCRIPTION("Maxim MAX77802 RTC driver");
501MODULE_AUTHOR("Simon Glass <sjg@chromium.org>");
502MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-mpc5121.c b/drivers/rtc/rtc-mpc5121.c
index dc4f14255cc3..3b965ad6f4d5 100644
--- a/drivers/rtc/rtc-mpc5121.c
+++ b/drivers/rtc/rtc-mpc5121.c
@@ -401,7 +401,7 @@ static int mpc5121_rtc_remove(struct platform_device *op)
401} 401}
402 402
403#ifdef CONFIG_OF 403#ifdef CONFIG_OF
404static struct of_device_id mpc5121_rtc_match[] = { 404static const struct of_device_id mpc5121_rtc_match[] = {
405 { .compatible = "fsl,mpc5121-rtc", }, 405 { .compatible = "fsl,mpc5121-rtc", },
406 { .compatible = "fsl,mpc5200-rtc", }, 406 { .compatible = "fsl,mpc5200-rtc", },
407 {}, 407 {},
diff --git a/drivers/rtc/rtc-pcf8563.c b/drivers/rtc/rtc-pcf8563.c
index 5a197d9dc7e7..c2ef0a22ee94 100644
--- a/drivers/rtc/rtc-pcf8563.c
+++ b/drivers/rtc/rtc-pcf8563.c
@@ -167,8 +167,8 @@ static irqreturn_t pcf8563_irq(int irq, void *dev_id)
167 char pending; 167 char pending;
168 168
169 err = pcf8563_get_alarm_mode(pcf8563->client, NULL, &pending); 169 err = pcf8563_get_alarm_mode(pcf8563->client, NULL, &pending);
170 if (err < 0) 170 if (err)
171 return err; 171 return IRQ_NONE;
172 172
173 if (pending) { 173 if (pending) {
174 rtc_update_irq(pcf8563->rtc, 1, RTC_IRQF | RTC_AF); 174 rtc_update_irq(pcf8563->rtc, 1, RTC_IRQF | RTC_AF);
diff --git a/drivers/rtc/rtc-pcf8583.c b/drivers/rtc/rtc-pcf8583.c
index c2639845186b..5911a6dca291 100644
--- a/drivers/rtc/rtc-pcf8583.c
+++ b/drivers/rtc/rtc-pcf8583.c
@@ -176,7 +176,11 @@ static int pcf8583_rtc_read_time(struct device *dev, struct rtc_time *tm)
176{ 176{
177 struct i2c_client *client = to_i2c_client(dev); 177 struct i2c_client *client = to_i2c_client(dev);
178 unsigned char ctrl, year[2]; 178 unsigned char ctrl, year[2];
179 struct rtc_mem mem = { CMOS_YEAR, sizeof(year), year }; 179 struct rtc_mem mem = {
180 .loc = CMOS_YEAR,
181 .nr = sizeof(year),
182 .data = year
183 };
180 int real_year, year_offset, err; 184 int real_year, year_offset, err;
181 185
182 /* 186 /*
@@ -222,8 +226,16 @@ static int pcf8583_rtc_set_time(struct device *dev, struct rtc_time *tm)
222{ 226{
223 struct i2c_client *client = to_i2c_client(dev); 227 struct i2c_client *client = to_i2c_client(dev);
224 unsigned char year[2], chk; 228 unsigned char year[2], chk;
225 struct rtc_mem cmos_year = { CMOS_YEAR, sizeof(year), year }; 229 struct rtc_mem cmos_year = {
226 struct rtc_mem cmos_check = { CMOS_CHECKSUM, 1, &chk }; 230 .loc = CMOS_YEAR,
231 .nr = sizeof(year),
232 .data = year
233 };
234 struct rtc_mem cmos_check = {
235 .loc = CMOS_CHECKSUM,
236 .nr = 1,
237 .data = &chk
238 };
227 unsigned int proper_year = tm->tm_year + 1900; 239 unsigned int proper_year = tm->tm_year + 1900;
228 int ret; 240 int ret;
229 241
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index 197699f358c7..5adcf111fc14 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -27,21 +27,36 @@
27 27
28/* RTC_CTRL register bit fields */ 28/* RTC_CTRL register bit fields */
29#define PM8xxx_RTC_ENABLE BIT(7) 29#define PM8xxx_RTC_ENABLE BIT(7)
30#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
31#define PM8xxx_RTC_ALARM_CLEAR BIT(0) 30#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
32 31
33#define NUM_8_BIT_RTC_REGS 0x4 32#define NUM_8_BIT_RTC_REGS 0x4
34 33
35/** 34/**
35 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
36 * @ctrl: base address of control register
37 * @write: base address of write register
38 * @read: base address of read register
39 * @alarm_ctrl: base address of alarm control register
40 * @alarm_ctrl2: base address of alarm control2 register
41 * @alarm_rw: base address of alarm read-write register
42 * @alarm_en: alarm enable mask
43 */
44struct pm8xxx_rtc_regs {
45 unsigned int ctrl;
46 unsigned int write;
47 unsigned int read;
48 unsigned int alarm_ctrl;
49 unsigned int alarm_ctrl2;
50 unsigned int alarm_rw;
51 unsigned int alarm_en;
52};
53
54/**
36 * struct pm8xxx_rtc - rtc driver internal structure 55 * struct pm8xxx_rtc - rtc driver internal structure
37 * @rtc: rtc device for this driver. 56 * @rtc: rtc device for this driver.
38 * @regmap: regmap used to access RTC registers 57 * @regmap: regmap used to access RTC registers
39 * @allow_set_time: indicates whether writing to the RTC is allowed 58 * @allow_set_time: indicates whether writing to the RTC is allowed
40 * @rtc_alarm_irq: rtc alarm irq number. 59 * @rtc_alarm_irq: rtc alarm irq number.
41 * @rtc_base: address of rtc control register.
42 * @rtc_read_base: base address of read registers.
43 * @rtc_write_base: base address of write registers.
44 * @alarm_rw_base: base address of alarm registers.
45 * @ctrl_reg: rtc control register. 60 * @ctrl_reg: rtc control register.
46 * @rtc_dev: device structure. 61 * @rtc_dev: device structure.
47 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg. 62 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
@@ -51,11 +66,7 @@ struct pm8xxx_rtc {
51 struct regmap *regmap; 66 struct regmap *regmap;
52 bool allow_set_time; 67 bool allow_set_time;
53 int rtc_alarm_irq; 68 int rtc_alarm_irq;
54 int rtc_base; 69 const struct pm8xxx_rtc_regs *regs;
55 int rtc_read_base;
56 int rtc_write_base;
57 int alarm_rw_base;
58 u8 ctrl_reg;
59 struct device *rtc_dev; 70 struct device *rtc_dev;
60 spinlock_t ctrl_reg_lock; 71 spinlock_t ctrl_reg_lock;
61}; 72};
@@ -71,8 +82,10 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
71{ 82{
72 int rc, i; 83 int rc, i;
73 unsigned long secs, irq_flags; 84 unsigned long secs, irq_flags;
74 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg; 85 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0;
86 unsigned int ctrl_reg;
75 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 87 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
88 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
76 89
77 if (!rtc_dd->allow_set_time) 90 if (!rtc_dd->allow_set_time)
78 return -EACCES; 91 return -EACCES;
@@ -87,30 +100,30 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
87 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); 100 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
88 101
89 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 102 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
90 ctrl_reg = rtc_dd->ctrl_reg;
91 103
92 if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) { 104 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
105 if (rc)
106 goto rtc_rw_fail;
107
108 if (ctrl_reg & regs->alarm_en) {
93 alarm_enabled = 1; 109 alarm_enabled = 1;
94 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; 110 ctrl_reg &= ~regs->alarm_en;
95 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); 111 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
96 if (rc) { 112 if (rc) {
97 dev_err(dev, "Write to RTC control register failed\n"); 113 dev_err(dev, "Write to RTC control register failed\n");
98 goto rtc_rw_fail; 114 goto rtc_rw_fail;
99 } 115 }
100 rtc_dd->ctrl_reg = ctrl_reg;
101 } else {
102 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
103 } 116 }
104 117
105 /* Write 0 to Byte[0] */ 118 /* Write 0 to Byte[0] */
106 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0); 119 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
107 if (rc) { 120 if (rc) {
108 dev_err(dev, "Write to RTC write data register failed\n"); 121 dev_err(dev, "Write to RTC write data register failed\n");
109 goto rtc_rw_fail; 122 goto rtc_rw_fail;
110 } 123 }
111 124
112 /* Write Byte[1], Byte[2], Byte[3] */ 125 /* Write Byte[1], Byte[2], Byte[3] */
113 rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1, 126 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
114 &value[1], sizeof(value) - 1); 127 &value[1], sizeof(value) - 1);
115 if (rc) { 128 if (rc) {
116 dev_err(dev, "Write to RTC write data register failed\n"); 129 dev_err(dev, "Write to RTC write data register failed\n");
@@ -118,25 +131,23 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
118 } 131 }
119 132
120 /* Write Byte[0] */ 133 /* Write Byte[0] */
121 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, value[0]); 134 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
122 if (rc) { 135 if (rc) {
123 dev_err(dev, "Write to RTC write data register failed\n"); 136 dev_err(dev, "Write to RTC write data register failed\n");
124 goto rtc_rw_fail; 137 goto rtc_rw_fail;
125 } 138 }
126 139
127 if (alarm_enabled) { 140 if (alarm_enabled) {
128 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; 141 ctrl_reg |= regs->alarm_en;
129 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); 142 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
130 if (rc) { 143 if (rc) {
131 dev_err(dev, "Write to RTC control register failed\n"); 144 dev_err(dev, "Write to RTC control register failed\n");
132 goto rtc_rw_fail; 145 goto rtc_rw_fail;
133 } 146 }
134 rtc_dd->ctrl_reg = ctrl_reg;
135 } 147 }
136 148
137rtc_rw_fail: 149rtc_rw_fail:
138 if (alarm_enabled) 150 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
139 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
140 151
141 return rc; 152 return rc;
142} 153}
@@ -148,9 +159,9 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
148 unsigned long secs; 159 unsigned long secs;
149 unsigned int reg; 160 unsigned int reg;
150 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 161 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
162 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
151 163
152 rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base, 164 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
153 value, sizeof(value));
154 if (rc) { 165 if (rc) {
155 dev_err(dev, "RTC read data register failed\n"); 166 dev_err(dev, "RTC read data register failed\n");
156 return rc; 167 return rc;
@@ -160,14 +171,14 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
160 * Read the LSB again and check if there has been a carry over. 171 * Read the LSB again and check if there has been a carry over.
161 * If there is, redo the read operation. 172 * If there is, redo the read operation.
162 */ 173 */
163 rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_read_base, &reg); 174 rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
164 if (rc < 0) { 175 if (rc < 0) {
165 dev_err(dev, "RTC read data register failed\n"); 176 dev_err(dev, "RTC read data register failed\n");
166 return rc; 177 return rc;
167 } 178 }
168 179
169 if (unlikely(reg < value[0])) { 180 if (unlikely(reg < value[0])) {
170 rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base, 181 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
171 value, sizeof(value)); 182 value, sizeof(value));
172 if (rc) { 183 if (rc) {
173 dev_err(dev, "RTC read data register failed\n"); 184 dev_err(dev, "RTC read data register failed\n");
@@ -195,9 +206,11 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
195static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 206static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
196{ 207{
197 int rc, i; 208 int rc, i;
198 u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg; 209 u8 value[NUM_8_BIT_RTC_REGS];
210 unsigned int ctrl_reg;
199 unsigned long secs, irq_flags; 211 unsigned long secs, irq_flags;
200 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 212 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
213 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
201 214
202 rtc_tm_to_time(&alarm->time, &secs); 215 rtc_tm_to_time(&alarm->time, &secs);
203 216
@@ -208,28 +221,28 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
208 221
209 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 222 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
210 223
211 rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->alarm_rw_base, value, 224 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
212 sizeof(value)); 225 sizeof(value));
213 if (rc) { 226 if (rc) {
214 dev_err(dev, "Write to RTC ALARM register failed\n"); 227 dev_err(dev, "Write to RTC ALARM register failed\n");
215 goto rtc_rw_fail; 228 goto rtc_rw_fail;
216 } 229 }
217 230
218 ctrl_reg = rtc_dd->ctrl_reg; 231 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
232 if (rc)
233 goto rtc_rw_fail;
219 234
220 if (alarm->enabled) 235 if (alarm->enabled)
221 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; 236 ctrl_reg |= regs->alarm_en;
222 else 237 else
223 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; 238 ctrl_reg &= ~regs->alarm_en;
224 239
225 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); 240 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
226 if (rc) { 241 if (rc) {
227 dev_err(dev, "Write to RTC control register failed\n"); 242 dev_err(dev, "Write to RTC alarm control register failed\n");
228 goto rtc_rw_fail; 243 goto rtc_rw_fail;
229 } 244 }
230 245
231 rtc_dd->ctrl_reg = ctrl_reg;
232
233 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", 246 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
234 alarm->time.tm_hour, alarm->time.tm_min, 247 alarm->time.tm_hour, alarm->time.tm_min,
235 alarm->time.tm_sec, alarm->time.tm_mday, 248 alarm->time.tm_sec, alarm->time.tm_mday,
@@ -245,8 +258,9 @@ static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
245 u8 value[NUM_8_BIT_RTC_REGS]; 258 u8 value[NUM_8_BIT_RTC_REGS];
246 unsigned long secs; 259 unsigned long secs;
247 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 260 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
261 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
248 262
249 rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->alarm_rw_base, value, 263 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
250 sizeof(value)); 264 sizeof(value));
251 if (rc) { 265 if (rc) {
252 dev_err(dev, "RTC alarm time read failed\n"); 266 dev_err(dev, "RTC alarm time read failed\n");
@@ -276,25 +290,26 @@ static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
276 int rc; 290 int rc;
277 unsigned long irq_flags; 291 unsigned long irq_flags;
278 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 292 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
279 u8 ctrl_reg; 293 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
294 unsigned int ctrl_reg;
280 295
281 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 296 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
282 297
283 ctrl_reg = rtc_dd->ctrl_reg; 298 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
299 if (rc)
300 goto rtc_rw_fail;
284 301
285 if (enable) 302 if (enable)
286 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; 303 ctrl_reg |= regs->alarm_en;
287 else 304 else
288 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; 305 ctrl_reg &= ~regs->alarm_en;
289 306
290 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); 307 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
291 if (rc) { 308 if (rc) {
292 dev_err(dev, "Write to RTC control register failed\n"); 309 dev_err(dev, "Write to RTC control register failed\n");
293 goto rtc_rw_fail; 310 goto rtc_rw_fail;
294 } 311 }
295 312
296 rtc_dd->ctrl_reg = ctrl_reg;
297
298rtc_rw_fail: 313rtc_rw_fail:
299 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 314 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
300 return rc; 315 return rc;
@@ -311,6 +326,7 @@ static const struct rtc_class_ops pm8xxx_rtc_ops = {
311static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) 326static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
312{ 327{
313 struct pm8xxx_rtc *rtc_dd = dev_id; 328 struct pm8xxx_rtc *rtc_dd = dev_id;
329 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
314 unsigned int ctrl_reg; 330 unsigned int ctrl_reg;
315 int rc; 331 int rc;
316 unsigned long irq_flags; 332 unsigned long irq_flags;
@@ -320,48 +336,100 @@ static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
320 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 336 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
321 337
322 /* Clear the alarm enable bit */ 338 /* Clear the alarm enable bit */
323 ctrl_reg = rtc_dd->ctrl_reg; 339 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
324 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; 340 if (rc) {
341 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
342 goto rtc_alarm_handled;
343 }
344
345 ctrl_reg &= ~regs->alarm_en;
325 346
326 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); 347 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
327 if (rc) { 348 if (rc) {
328 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 349 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
329 dev_err(rtc_dd->rtc_dev, 350 dev_err(rtc_dd->rtc_dev,
330 "Write to RTC control register failed\n"); 351 "Write to alarm control register failed\n");
331 goto rtc_alarm_handled; 352 goto rtc_alarm_handled;
332 } 353 }
333 354
334 rtc_dd->ctrl_reg = ctrl_reg;
335 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 355 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
336 356
337 /* Clear RTC alarm register */ 357 /* Clear RTC alarm register */
338 rc = regmap_read(rtc_dd->regmap, 358 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
339 rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
340 &ctrl_reg);
341 if (rc) { 359 if (rc) {
342 dev_err(rtc_dd->rtc_dev, 360 dev_err(rtc_dd->rtc_dev,
343 "RTC Alarm control register read failed\n"); 361 "RTC Alarm control2 register read failed\n");
344 goto rtc_alarm_handled; 362 goto rtc_alarm_handled;
345 } 363 }
346 364
347 ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR; 365 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
348 rc = regmap_write(rtc_dd->regmap, 366 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
349 rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
350 ctrl_reg);
351 if (rc) 367 if (rc)
352 dev_err(rtc_dd->rtc_dev, 368 dev_err(rtc_dd->rtc_dev,
353 "Write to RTC Alarm control register failed\n"); 369 "Write to RTC Alarm control2 register failed\n");
354 370
355rtc_alarm_handled: 371rtc_alarm_handled:
356 return IRQ_HANDLED; 372 return IRQ_HANDLED;
357} 373}
358 374
375static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
376{
377 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
378 unsigned int ctrl_reg;
379 int rc;
380
381 /* Check if the RTC is on, else turn it on */
382 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
383 if (rc)
384 return rc;
385
386 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
387 ctrl_reg |= PM8xxx_RTC_ENABLE;
388 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
389 if (rc)
390 return rc;
391 }
392
393 return 0;
394}
395
396static const struct pm8xxx_rtc_regs pm8921_regs = {
397 .ctrl = 0x11d,
398 .write = 0x11f,
399 .read = 0x123,
400 .alarm_rw = 0x127,
401 .alarm_ctrl = 0x11d,
402 .alarm_ctrl2 = 0x11e,
403 .alarm_en = BIT(1),
404};
405
406static const struct pm8xxx_rtc_regs pm8058_regs = {
407 .ctrl = 0x1e8,
408 .write = 0x1ea,
409 .read = 0x1ee,
410 .alarm_rw = 0x1f2,
411 .alarm_ctrl = 0x1e8,
412 .alarm_ctrl2 = 0x1e9,
413 .alarm_en = BIT(1),
414};
415
416static const struct pm8xxx_rtc_regs pm8941_regs = {
417 .ctrl = 0x6046,
418 .write = 0x6040,
419 .read = 0x6048,
420 .alarm_rw = 0x6140,
421 .alarm_ctrl = 0x6146,
422 .alarm_ctrl2 = 0x6148,
423 .alarm_en = BIT(7),
424};
425
359/* 426/*
360 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out 427 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
361 */ 428 */
362static const struct of_device_id pm8xxx_id_table[] = { 429static const struct of_device_id pm8xxx_id_table[] = {
363 { .compatible = "qcom,pm8921-rtc", .data = (void *) 0x11D }, 430 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
364 { .compatible = "qcom,pm8058-rtc", .data = (void *) 0x1E8 }, 431 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
432 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
365 { }, 433 { },
366}; 434};
367MODULE_DEVICE_TABLE(of, pm8xxx_id_table); 435MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
@@ -369,7 +437,6 @@ MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
369static int pm8xxx_rtc_probe(struct platform_device *pdev) 437static int pm8xxx_rtc_probe(struct platform_device *pdev)
370{ 438{
371 int rc; 439 int rc;
372 unsigned int ctrl_reg;
373 struct pm8xxx_rtc *rtc_dd; 440 struct pm8xxx_rtc *rtc_dd;
374 const struct of_device_id *match; 441 const struct of_device_id *match;
375 442
@@ -399,33 +466,12 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
399 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node, 466 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
400 "allow-set-time"); 467 "allow-set-time");
401 468
402 rtc_dd->rtc_base = (long) match->data; 469 rtc_dd->regs = match->data;
403
404 /* Setup RTC register addresses */
405 rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
406 rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
407 rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;
408
409 rtc_dd->rtc_dev = &pdev->dev; 470 rtc_dd->rtc_dev = &pdev->dev;
410 471
411 /* Check if the RTC is on, else turn it on */ 472 rc = pm8xxx_rtc_enable(rtc_dd);
412 rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_base, &ctrl_reg); 473 if (rc)
413 if (rc) {
414 dev_err(&pdev->dev, "RTC control register read failed!\n");
415 return rc; 474 return rc;
416 }
417
418 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
419 ctrl_reg |= PM8xxx_RTC_ENABLE;
420 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
421 if (rc) {
422 dev_err(&pdev->dev,
423 "Write to RTC control register failed\n");
424 return rc;
425 }
426 }
427
428 rtc_dd->ctrl_reg = ctrl_reg;
429 475
430 platform_set_drvdata(pdev, rtc_dd); 476 platform_set_drvdata(pdev, rtc_dd);
431 477
diff --git a/drivers/rtc/rtc-rk808.c b/drivers/rtc/rtc-rk808.c
new file mode 100644
index 000000000000..df42257668ac
--- /dev/null
+++ b/drivers/rtc/rtc-rk808.c
@@ -0,0 +1,414 @@
1/*
2 * RTC driver for Rockchip RK808
3 *
4 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5 *
6 * Author: Chris Zhong <zyw@rock-chips.com>
7 * Author: Zhang Qing <zhangqing@rock-chips.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/rtc.h>
22#include <linux/bcd.h>
23#include <linux/mfd/rk808.h>
24#include <linux/platform_device.h>
25#include <linux/i2c.h>
26
27/* RTC_CTRL_REG bitfields */
28#define BIT_RTC_CTRL_REG_STOP_RTC_M BIT(0)
29
30/* RK808 has a shadowed register for saving a "frozen" RTC time.
31 * When user setting "GET_TIME" to 1, the time will save in this shadowed
32 * register. If set "READSEL" to 1, user read rtc time register, actually
33 * get the time of that moment. If we need the real time, clr this bit.
34 */
35#define BIT_RTC_CTRL_REG_RTC_GET_TIME BIT(6)
36#define BIT_RTC_CTRL_REG_RTC_READSEL_M BIT(7)
37#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M BIT(3)
38#define RTC_STATUS_MASK 0xFE
39
40#define SECONDS_REG_MSK 0x7F
41#define MINUTES_REG_MAK 0x7F
42#define HOURS_REG_MSK 0x3F
43#define DAYS_REG_MSK 0x3F
44#define MONTHS_REG_MSK 0x1F
45#define YEARS_REG_MSK 0xFF
46#define WEEKS_REG_MSK 0x7
47
48/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
49
50#define NUM_TIME_REGS (RK808_WEEKS_REG - RK808_SECONDS_REG + 1)
51#define NUM_ALARM_REGS (RK808_ALARM_YEARS_REG - RK808_ALARM_SECONDS_REG + 1)
52
53struct rk808_rtc {
54 struct rk808 *rk808;
55 struct rtc_device *rtc;
56 int irq;
57};
58
59/* Read current time and date in RTC */
60static int rk808_rtc_readtime(struct device *dev, struct rtc_time *tm)
61{
62 struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
63 struct rk808 *rk808 = rk808_rtc->rk808;
64 u8 rtc_data[NUM_TIME_REGS];
65 int ret;
66
67 /* Force an update of the shadowed registers right now */
68 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
69 BIT_RTC_CTRL_REG_RTC_GET_TIME,
70 0);
71 if (ret) {
72 dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret);
73 return ret;
74 }
75
76 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
77 BIT_RTC_CTRL_REG_RTC_GET_TIME,
78 BIT_RTC_CTRL_REG_RTC_GET_TIME);
79 if (ret) {
80 dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret);
81 return ret;
82 }
83
84 ret = regmap_bulk_read(rk808->regmap, RK808_SECONDS_REG,
85 rtc_data, NUM_TIME_REGS);
86 if (ret) {
87 dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
88 return ret;
89 }
90
91 tm->tm_sec = bcd2bin(rtc_data[0] & SECONDS_REG_MSK);
92 tm->tm_min = bcd2bin(rtc_data[1] & MINUTES_REG_MAK);
93 tm->tm_hour = bcd2bin(rtc_data[2] & HOURS_REG_MSK);
94 tm->tm_mday = bcd2bin(rtc_data[3] & DAYS_REG_MSK);
95 tm->tm_mon = (bcd2bin(rtc_data[4] & MONTHS_REG_MSK)) - 1;
96 tm->tm_year = (bcd2bin(rtc_data[5] & YEARS_REG_MSK)) + 100;
97 tm->tm_wday = bcd2bin(rtc_data[6] & WEEKS_REG_MSK);
98 dev_dbg(dev, "RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
99 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
100 tm->tm_wday, tm->tm_hour , tm->tm_min, tm->tm_sec);
101
102 return ret;
103}
104
105/* Set current time and date in RTC */
106static int rk808_rtc_set_time(struct device *dev, struct rtc_time *tm)
107{
108 struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
109 struct rk808 *rk808 = rk808_rtc->rk808;
110 u8 rtc_data[NUM_TIME_REGS];
111 int ret;
112
113 rtc_data[0] = bin2bcd(tm->tm_sec);
114 rtc_data[1] = bin2bcd(tm->tm_min);
115 rtc_data[2] = bin2bcd(tm->tm_hour);
116 rtc_data[3] = bin2bcd(tm->tm_mday);
117 rtc_data[4] = bin2bcd(tm->tm_mon + 1);
118 rtc_data[5] = bin2bcd(tm->tm_year - 100);
119 rtc_data[6] = bin2bcd(tm->tm_wday);
120 dev_dbg(dev, "set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
121 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
122 tm->tm_wday, tm->tm_hour , tm->tm_min, tm->tm_sec);
123
124 /* Stop RTC while updating the RTC registers */
125 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
126 BIT_RTC_CTRL_REG_STOP_RTC_M,
127 BIT_RTC_CTRL_REG_STOP_RTC_M);
128 if (ret) {
129 dev_err(dev, "Failed to update RTC control: %d\n", ret);
130 return ret;
131 }
132
133 ret = regmap_bulk_write(rk808->regmap, RK808_SECONDS_REG,
134 rtc_data, NUM_TIME_REGS);
135 if (ret) {
136 dev_err(dev, "Failed to bull write rtc_data: %d\n", ret);
137 return ret;
138 }
139 /* Start RTC again */
140 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
141 BIT_RTC_CTRL_REG_STOP_RTC_M, 0);
142 if (ret) {
143 dev_err(dev, "Failed to update RTC control: %d\n", ret);
144 return ret;
145 }
146 return 0;
147}
148
149/* Read alarm time and date in RTC */
150static int rk808_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
151{
152 struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
153 struct rk808 *rk808 = rk808_rtc->rk808;
154 u8 alrm_data[NUM_ALARM_REGS];
155 uint32_t int_reg;
156 int ret;
157
158 ret = regmap_bulk_read(rk808->regmap, RK808_ALARM_SECONDS_REG,
159 alrm_data, NUM_ALARM_REGS);
160
161 alrm->time.tm_sec = bcd2bin(alrm_data[0] & SECONDS_REG_MSK);
162 alrm->time.tm_min = bcd2bin(alrm_data[1] & MINUTES_REG_MAK);
163 alrm->time.tm_hour = bcd2bin(alrm_data[2] & HOURS_REG_MSK);
164 alrm->time.tm_mday = bcd2bin(alrm_data[3] & DAYS_REG_MSK);
165 alrm->time.tm_mon = (bcd2bin(alrm_data[4] & MONTHS_REG_MSK)) - 1;
166 alrm->time.tm_year = (bcd2bin(alrm_data[5] & YEARS_REG_MSK)) + 100;
167
168 ret = regmap_read(rk808->regmap, RK808_RTC_INT_REG, &int_reg);
169 if (ret) {
170 dev_err(dev, "Failed to read RTC INT REG: %d\n", ret);
171 return ret;
172 }
173
174 dev_dbg(dev, "alrm read RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
175 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
176 alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
177 alrm->time.tm_min, alrm->time.tm_sec);
178
179 alrm->enabled = (int_reg & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M) ? 1 : 0;
180
181 return 0;
182}
183
184static int rk808_rtc_stop_alarm(struct rk808_rtc *rk808_rtc)
185{
186 struct rk808 *rk808 = rk808_rtc->rk808;
187 int ret;
188
189 ret = regmap_update_bits(rk808->regmap, RK808_RTC_INT_REG,
190 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, 0);
191
192 return ret;
193}
194
195static int rk808_rtc_start_alarm(struct rk808_rtc *rk808_rtc)
196{
197 struct rk808 *rk808 = rk808_rtc->rk808;
198 int ret;
199
200 ret = regmap_update_bits(rk808->regmap, RK808_RTC_INT_REG,
201 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M,
202 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
203
204 return ret;
205}
206
207static int rk808_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
208{
209 struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
210 struct rk808 *rk808 = rk808_rtc->rk808;
211 u8 alrm_data[NUM_ALARM_REGS];
212 int ret;
213
214 ret = rk808_rtc_stop_alarm(rk808_rtc);
215 if (ret) {
216 dev_err(dev, "Failed to stop alarm: %d\n", ret);
217 return ret;
218 }
219 dev_dbg(dev, "alrm set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
220 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
221 alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
222 alrm->time.tm_min, alrm->time.tm_sec);
223
224 alrm_data[0] = bin2bcd(alrm->time.tm_sec);
225 alrm_data[1] = bin2bcd(alrm->time.tm_min);
226 alrm_data[2] = bin2bcd(alrm->time.tm_hour);
227 alrm_data[3] = bin2bcd(alrm->time.tm_mday);
228 alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1);
229 alrm_data[5] = bin2bcd(alrm->time.tm_year - 100);
230
231 ret = regmap_bulk_write(rk808->regmap, RK808_ALARM_SECONDS_REG,
232 alrm_data, NUM_ALARM_REGS);
233 if (ret) {
234 dev_err(dev, "Failed to bulk write: %d\n", ret);
235 return ret;
236 }
237 if (alrm->enabled) {
238 ret = rk808_rtc_start_alarm(rk808_rtc);
239 if (ret) {
240 dev_err(dev, "Failed to start alarm: %d\n", ret);
241 return ret;
242 }
243 }
244 return 0;
245}
246
247static int rk808_rtc_alarm_irq_enable(struct device *dev,
248 unsigned int enabled)
249{
250 struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
251
252 if (enabled)
253 return rk808_rtc_start_alarm(rk808_rtc);
254
255 return rk808_rtc_stop_alarm(rk808_rtc);
256}
257
258/*
259 * We will just handle setting the frequency and make use the framework for
260 * reading the periodic interupts.
261 *
262 * @freq: Current periodic IRQ freq:
263 * bit 0: every second
264 * bit 1: every minute
265 * bit 2: every hour
266 * bit 3: every day
267 */
268static irqreturn_t rk808_alarm_irq(int irq, void *data)
269{
270 struct rk808_rtc *rk808_rtc = data;
271 struct rk808 *rk808 = rk808_rtc->rk808;
272 struct i2c_client *client = rk808->i2c;
273 int ret;
274
275 ret = regmap_write(rk808->regmap, RK808_RTC_STATUS_REG,
276 RTC_STATUS_MASK);
277 if (ret) {
278 dev_err(&client->dev,
279 "%s:Failed to update RTC status: %d\n", __func__, ret);
280 return ret;
281 }
282
283 rtc_update_irq(rk808_rtc->rtc, 1, RTC_IRQF | RTC_AF);
284 dev_dbg(&client->dev,
285 "%s:irq=%d\n", __func__, irq);
286 return IRQ_HANDLED;
287}
288
289static const struct rtc_class_ops rk808_rtc_ops = {
290 .read_time = rk808_rtc_readtime,
291 .set_time = rk808_rtc_set_time,
292 .read_alarm = rk808_rtc_readalarm,
293 .set_alarm = rk808_rtc_setalarm,
294 .alarm_irq_enable = rk808_rtc_alarm_irq_enable,
295};
296
297#ifdef CONFIG_PM_SLEEP
298/* Turn off the alarm if it should not be a wake source. */
299static int rk808_rtc_suspend(struct device *dev)
300{
301 struct platform_device *pdev = to_platform_device(dev);
302 struct rk808_rtc *rk808_rtc = dev_get_drvdata(&pdev->dev);
303
304 if (device_may_wakeup(dev))
305 enable_irq_wake(rk808_rtc->irq);
306
307 return 0;
308}
309
310/* Enable the alarm if it should be enabled (in case it was disabled to
311 * prevent use as a wake source).
312 */
313static int rk808_rtc_resume(struct device *dev)
314{
315 struct platform_device *pdev = to_platform_device(dev);
316 struct rk808_rtc *rk808_rtc = dev_get_drvdata(&pdev->dev);
317
318 if (device_may_wakeup(dev))
319 disable_irq_wake(rk808_rtc->irq);
320
321 return 0;
322}
323#endif
324
325static SIMPLE_DEV_PM_OPS(rk808_rtc_pm_ops,
326 rk808_rtc_suspend, rk808_rtc_resume);
327
328static int rk808_rtc_probe(struct platform_device *pdev)
329{
330 struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
331 struct rk808_rtc *rk808_rtc;
332 struct rtc_time tm;
333 int ret;
334
335 rk808_rtc = devm_kzalloc(&pdev->dev, sizeof(*rk808_rtc), GFP_KERNEL);
336 if (rk808_rtc == NULL)
337 return -ENOMEM;
338
339 platform_set_drvdata(pdev, rk808_rtc);
340 rk808_rtc->rk808 = rk808;
341
342 /* start rtc running by default, and use shadowed timer. */
343 ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
344 BIT_RTC_CTRL_REG_STOP_RTC_M |
345 BIT_RTC_CTRL_REG_RTC_READSEL_M,
346 BIT_RTC_CTRL_REG_RTC_READSEL_M);
347 if (ret) {
348 dev_err(&pdev->dev,
349 "Failed to update RTC control: %d\n", ret);
350 return ret;
351 }
352
353 ret = regmap_write(rk808->regmap, RK808_RTC_STATUS_REG,
354 RTC_STATUS_MASK);
355 if (ret) {
356 dev_err(&pdev->dev,
357 "Failed to write RTC status: %d\n", ret);
358 return ret;
359 }
360
361 /* set init time */
362 ret = rk808_rtc_readtime(&pdev->dev, &tm);
363 if (ret) {
364 dev_err(&pdev->dev, "Failed to read RTC time\n");
365 return ret;
366 }
367 ret = rtc_valid_tm(&tm);
368 if (ret)
369 dev_warn(&pdev->dev, "invalid date/time\n");
370
371 device_init_wakeup(&pdev->dev, 1);
372
373 rk808_rtc->rtc = devm_rtc_device_register(&pdev->dev, "rk808-rtc",
374 &rk808_rtc_ops, THIS_MODULE);
375 if (IS_ERR(rk808_rtc->rtc)) {
376 ret = PTR_ERR(rk808_rtc->rtc);
377 return ret;
378 }
379
380 rk808_rtc->irq = platform_get_irq(pdev, 0);
381 if (rk808_rtc->irq < 0) {
382 if (rk808_rtc->irq != -EPROBE_DEFER)
383 dev_err(&pdev->dev, "Wake up is not possible as irq = %d\n",
384 rk808_rtc->irq);
385 return rk808_rtc->irq;
386 }
387
388 /* request alarm irq of rk808 */
389 ret = devm_request_threaded_irq(&pdev->dev, rk808_rtc->irq, NULL,
390 rk808_alarm_irq, 0,
391 "RTC alarm", rk808_rtc);
392 if (ret) {
393 dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",
394 rk808_rtc->irq, ret);
395 }
396
397 return ret;
398}
399
400static struct platform_driver rk808_rtc_driver = {
401 .probe = rk808_rtc_probe,
402 .driver = {
403 .name = "rk808-rtc",
404 .pm = &rk808_rtc_pm_ops,
405 },
406};
407
408module_platform_driver(rk808_rtc_driver);
409
410MODULE_DESCRIPTION("RTC driver for the rk808 series PMICs");
411MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
412MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
413MODULE_LICENSE("GPL");
414MODULE_ALIAS("platform:rk808-rtc");
diff --git a/drivers/rtc/rtc-rs5c372.c b/drivers/rtc/rtc-rs5c372.c
index ccf54f06396b..28871cd7e3b5 100644
--- a/drivers/rtc/rtc-rs5c372.c
+++ b/drivers/rtc/rtc-rs5c372.c
@@ -142,12 +142,11 @@ static int rs5c_get_regs(struct rs5c372 *rs5c)
142 } 142 }
143 143
144 dev_dbg(&client->dev, 144 dev_dbg(&client->dev,
145 "%02x %02x %02x (%02x) %02x %02x %02x (%02x), " 145 "%3ph (%02x) %3ph (%02x), %3ph, %3ph; %02x %02x\n",
146 "%02x %02x %02x, %02x %02x %02x; %02x %02x\n", 146 rs5c->regs + 0, rs5c->regs[3],
147 rs5c->regs[0], rs5c->regs[1], rs5c->regs[2], rs5c->regs[3], 147 rs5c->regs + 4, rs5c->regs[7],
148 rs5c->regs[4], rs5c->regs[5], rs5c->regs[6], rs5c->regs[7], 148 rs5c->regs + 8, rs5c->regs + 11,
149 rs5c->regs[8], rs5c->regs[9], rs5c->regs[10], rs5c->regs[11], 149 rs5c->regs[14], rs5c->regs[15]);
150 rs5c->regs[12], rs5c->regs[13], rs5c->regs[14], rs5c->regs[15]);
151 150
152 return 0; 151 return 0;
153} 152}
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 4958a363b2c7..806072238c00 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -32,155 +32,150 @@
32#include <asm/irq.h> 32#include <asm/irq.h>
33#include "rtc-s3c.h" 33#include "rtc-s3c.h"
34 34
35enum s3c_cpu_type { 35struct s3c_rtc {
36 TYPE_S3C2410, 36 struct device *dev;
37 TYPE_S3C2416, 37 struct rtc_device *rtc;
38 TYPE_S3C2443,
39 TYPE_S3C64XX,
40};
41 38
42struct s3c_rtc_drv_data { 39 void __iomem *base;
43 int cpu_type; 40 struct clk *rtc_clk;
44}; 41 struct clk *rtc_src_clk;
42 bool enabled;
43
44 struct s3c_rtc_data *data;
45 45
46/* I have yet to find an S3C implementation with more than one 46 int irq_alarm;
47 * of these rtc blocks in */ 47 int irq_tick;
48 48
49static struct clk *rtc_clk; 49 spinlock_t pie_lock;
50static void __iomem *s3c_rtc_base; 50 spinlock_t alarm_clk_lock;
51static int s3c_rtc_alarmno;
52static int s3c_rtc_tickno;
53static enum s3c_cpu_type s3c_rtc_cpu_type;
54 51
55static DEFINE_SPINLOCK(s3c_rtc_pie_lock); 52 int ticnt_save, ticnt_en_save;
53 bool wake_en;
54};
55
56struct s3c_rtc_data {
57 int max_user_freq;
58 bool needs_src_clk;
59
60 void (*irq_handler) (struct s3c_rtc *info, int mask);
61 void (*set_freq) (struct s3c_rtc *info, int freq);
62 void (*enable_tick) (struct s3c_rtc *info, struct seq_file *seq);
63 void (*select_tick_clk) (struct s3c_rtc *info);
64 void (*save_tick_cnt) (struct s3c_rtc *info);
65 void (*restore_tick_cnt) (struct s3c_rtc *info);
66 void (*enable) (struct s3c_rtc *info);
67 void (*disable) (struct s3c_rtc *info);
68};
56 69
57static void s3c_rtc_alarm_clk_enable(bool enable) 70static void s3c_rtc_alarm_clk_enable(struct s3c_rtc *info, bool enable)
58{ 71{
59 static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
60 static bool alarm_clk_enabled;
61 unsigned long irq_flags; 72 unsigned long irq_flags;
62 73
63 spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags); 74 spin_lock_irqsave(&info->alarm_clk_lock, irq_flags);
64 if (enable) { 75 if (enable) {
65 if (!alarm_clk_enabled) { 76 if (!info->enabled) {
66 clk_enable(rtc_clk); 77 clk_enable(info->rtc_clk);
67 alarm_clk_enabled = true; 78 if (info->data->needs_src_clk)
79 clk_enable(info->rtc_src_clk);
80 info->enabled = true;
68 } 81 }
69 } else { 82 } else {
70 if (alarm_clk_enabled) { 83 if (info->enabled) {
71 clk_disable(rtc_clk); 84 if (info->data->needs_src_clk)
72 alarm_clk_enabled = false; 85 clk_disable(info->rtc_src_clk);
86 clk_disable(info->rtc_clk);
87 info->enabled = false;
73 } 88 }
74 } 89 }
75 spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags); 90 spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags);
76} 91}
77 92
78/* IRQ Handlers */ 93/* IRQ Handlers */
79 94static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
80static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
81{ 95{
82 struct rtc_device *rdev = id; 96 struct s3c_rtc *info = (struct s3c_rtc *)id;
83
84 clk_enable(rtc_clk);
85 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
86
87 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
88 writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
89
90 clk_disable(rtc_clk);
91 97
92 s3c_rtc_alarm_clk_enable(false); 98 if (info->data->irq_handler)
99 info->data->irq_handler(info, S3C2410_INTP_TIC);
93 100
94 return IRQ_HANDLED; 101 return IRQ_HANDLED;
95} 102}
96 103
97static irqreturn_t s3c_rtc_tickirq(int irq, void *id) 104static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
98{ 105{
99 struct rtc_device *rdev = id; 106 struct s3c_rtc *info = (struct s3c_rtc *)id;
100 107
101 clk_enable(rtc_clk); 108 if (info->data->irq_handler)
102 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); 109 info->data->irq_handler(info, S3C2410_INTP_ALM);
103 110
104 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
105 writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
106
107 clk_disable(rtc_clk);
108 return IRQ_HANDLED; 111 return IRQ_HANDLED;
109} 112}
110 113
111/* Update control registers */ 114/* Update control registers */
112static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) 115static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
113{ 116{
117 struct s3c_rtc *info = dev_get_drvdata(dev);
114 unsigned int tmp; 118 unsigned int tmp;
115 119
116 dev_dbg(dev, "%s: aie=%d\n", __func__, enabled); 120 dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled);
117 121
118 clk_enable(rtc_clk); 122 clk_enable(info->rtc_clk);
119 tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; 123 if (info->data->needs_src_clk)
124 clk_enable(info->rtc_src_clk);
125 tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
120 126
121 if (enabled) 127 if (enabled)
122 tmp |= S3C2410_RTCALM_ALMEN; 128 tmp |= S3C2410_RTCALM_ALMEN;
123 129
124 writeb(tmp, s3c_rtc_base + S3C2410_RTCALM); 130 writeb(tmp, info->base + S3C2410_RTCALM);
125 clk_disable(rtc_clk); 131 if (info->data->needs_src_clk)
132 clk_disable(info->rtc_src_clk);
133 clk_disable(info->rtc_clk);
126 134
127 s3c_rtc_alarm_clk_enable(enabled); 135 s3c_rtc_alarm_clk_enable(info, enabled);
128 136
129 return 0; 137 return 0;
130} 138}
131 139
132static int s3c_rtc_setfreq(struct device *dev, int freq) 140/* Set RTC frequency */
141static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq)
133{ 142{
134 struct platform_device *pdev = to_platform_device(dev);
135 struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
136 unsigned int tmp = 0;
137 int val;
138
139 if (!is_power_of_2(freq)) 143 if (!is_power_of_2(freq))
140 return -EINVAL; 144 return -EINVAL;
141 145
142 clk_enable(rtc_clk); 146 clk_enable(info->rtc_clk);
143 spin_lock_irq(&s3c_rtc_pie_lock); 147 if (info->data->needs_src_clk)
148 clk_enable(info->rtc_src_clk);
149 spin_lock_irq(&info->pie_lock);
144 150
145 if (s3c_rtc_cpu_type != TYPE_S3C64XX) { 151 if (info->data->set_freq)
146 tmp = readb(s3c_rtc_base + S3C2410_TICNT); 152 info->data->set_freq(info, freq);
147 tmp &= S3C2410_TICNT_ENABLE;
148 }
149 153
150 val = (rtc_dev->max_user_freq / freq) - 1; 154 spin_unlock_irq(&info->pie_lock);
151 155 if (info->data->needs_src_clk)
152 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { 156 clk_disable(info->rtc_src_clk);
153 tmp |= S3C2443_TICNT_PART(val); 157 clk_disable(info->rtc_clk);
154 writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
155
156 if (s3c_rtc_cpu_type == TYPE_S3C2416)
157 writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
158 } else {
159 tmp |= val;
160 }
161
162 writel(tmp, s3c_rtc_base + S3C2410_TICNT);
163 spin_unlock_irq(&s3c_rtc_pie_lock);
164 clk_disable(rtc_clk);
165 158
166 return 0; 159 return 0;
167} 160}
168 161
169/* Time read/write */ 162/* Time read/write */
170
171static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 163static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
172{ 164{
165 struct s3c_rtc *info = dev_get_drvdata(dev);
173 unsigned int have_retried = 0; 166 unsigned int have_retried = 0;
174 void __iomem *base = s3c_rtc_base;
175 167
176 clk_enable(rtc_clk); 168 clk_enable(info->rtc_clk);
169 if (info->data->needs_src_clk)
170 clk_enable(info->rtc_src_clk);
171
177 retry_get_time: 172 retry_get_time:
178 rtc_tm->tm_min = readb(base + S3C2410_RTCMIN); 173 rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN);
179 rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR); 174 rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR);
180 rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE); 175 rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE);
181 rtc_tm->tm_mon = readb(base + S3C2410_RTCMON); 176 rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON);
182 rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR); 177 rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR);
183 rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC); 178 rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC);
184 179
185 /* the only way to work out whether the system was mid-update 180 /* the only way to work out whether the system was mid-update
186 * when we read it is to check the second counter, and if it 181 * when we read it is to check the second counter, and if it
@@ -207,13 +202,16 @@ static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
207 202
208 rtc_tm->tm_mon -= 1; 203 rtc_tm->tm_mon -= 1;
209 204
210 clk_disable(rtc_clk); 205 if (info->data->needs_src_clk)
206 clk_disable(info->rtc_src_clk);
207 clk_disable(info->rtc_clk);
208
211 return rtc_valid_tm(rtc_tm); 209 return rtc_valid_tm(rtc_tm);
212} 210}
213 211
214static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) 212static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
215{ 213{
216 void __iomem *base = s3c_rtc_base; 214 struct s3c_rtc *info = dev_get_drvdata(dev);
217 int year = tm->tm_year - 100; 215 int year = tm->tm_year - 100;
218 216
219 dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n", 217 dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
@@ -227,33 +225,42 @@ static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
227 return -EINVAL; 225 return -EINVAL;
228 } 226 }
229 227
230 clk_enable(rtc_clk); 228 clk_enable(info->rtc_clk);
231 writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC); 229 if (info->data->needs_src_clk)
232 writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN); 230 clk_enable(info->rtc_src_clk);
233 writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR); 231
234 writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE); 232 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC);
235 writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON); 233 writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN);
236 writeb(bin2bcd(year), base + S3C2410_RTCYEAR); 234 writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR);
237 clk_disable(rtc_clk); 235 writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE);
236 writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON);
237 writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR);
238
239 if (info->data->needs_src_clk)
240 clk_disable(info->rtc_src_clk);
241 clk_disable(info->rtc_clk);
238 242
239 return 0; 243 return 0;
240} 244}
241 245
242static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) 246static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
243{ 247{
248 struct s3c_rtc *info = dev_get_drvdata(dev);
244 struct rtc_time *alm_tm = &alrm->time; 249 struct rtc_time *alm_tm = &alrm->time;
245 void __iomem *base = s3c_rtc_base;
246 unsigned int alm_en; 250 unsigned int alm_en;
247 251
248 clk_enable(rtc_clk); 252 clk_enable(info->rtc_clk);
249 alm_tm->tm_sec = readb(base + S3C2410_ALMSEC); 253 if (info->data->needs_src_clk)
250 alm_tm->tm_min = readb(base + S3C2410_ALMMIN); 254 clk_enable(info->rtc_src_clk);
251 alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
252 alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
253 alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
254 alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
255 255
256 alm_en = readb(base + S3C2410_RTCALM); 256 alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC);
257 alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN);
258 alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR);
259 alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON);
260 alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE);
261 alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR);
262
263 alm_en = readb(info->base + S3C2410_RTCALM);
257 264
258 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; 265 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
259 266
@@ -297,65 +304,74 @@ static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
297 else 304 else
298 alm_tm->tm_year = -1; 305 alm_tm->tm_year = -1;
299 306
300 clk_disable(rtc_clk); 307 if (info->data->needs_src_clk)
308 clk_disable(info->rtc_src_clk);
309 clk_disable(info->rtc_clk);
310
301 return 0; 311 return 0;
302} 312}
303 313
304static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) 314static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
305{ 315{
316 struct s3c_rtc *info = dev_get_drvdata(dev);
306 struct rtc_time *tm = &alrm->time; 317 struct rtc_time *tm = &alrm->time;
307 void __iomem *base = s3c_rtc_base;
308 unsigned int alrm_en; 318 unsigned int alrm_en;
309 319
310 clk_enable(rtc_clk); 320 clk_enable(info->rtc_clk);
321 if (info->data->needs_src_clk)
322 clk_enable(info->rtc_src_clk);
323
311 dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", 324 dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
312 alrm->enabled, 325 alrm->enabled,
313 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, 326 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
314 tm->tm_hour, tm->tm_min, tm->tm_sec); 327 tm->tm_hour, tm->tm_min, tm->tm_sec);
315 328
316 alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; 329 alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
317 writeb(0x00, base + S3C2410_RTCALM); 330 writeb(0x00, info->base + S3C2410_RTCALM);
318 331
319 if (tm->tm_sec < 60 && tm->tm_sec >= 0) { 332 if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
320 alrm_en |= S3C2410_RTCALM_SECEN; 333 alrm_en |= S3C2410_RTCALM_SECEN;
321 writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC); 334 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC);
322 } 335 }
323 336
324 if (tm->tm_min < 60 && tm->tm_min >= 0) { 337 if (tm->tm_min < 60 && tm->tm_min >= 0) {
325 alrm_en |= S3C2410_RTCALM_MINEN; 338 alrm_en |= S3C2410_RTCALM_MINEN;
326 writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN); 339 writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN);
327 } 340 }
328 341
329 if (tm->tm_hour < 24 && tm->tm_hour >= 0) { 342 if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
330 alrm_en |= S3C2410_RTCALM_HOUREN; 343 alrm_en |= S3C2410_RTCALM_HOUREN;
331 writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR); 344 writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR);
332 } 345 }
333 346
334 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); 347 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
335 348
336 writeb(alrm_en, base + S3C2410_RTCALM); 349 writeb(alrm_en, info->base + S3C2410_RTCALM);
337 350
338 s3c_rtc_setaie(dev, alrm->enabled); 351 s3c_rtc_setaie(dev, alrm->enabled);
339 352
340 clk_disable(rtc_clk); 353 if (info->data->needs_src_clk)
354 clk_disable(info->rtc_src_clk);
355 clk_disable(info->rtc_clk);
356
341 return 0; 357 return 0;
342} 358}
343 359
344static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) 360static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
345{ 361{
346 unsigned int ticnt; 362 struct s3c_rtc *info = dev_get_drvdata(dev);
347 363
348 clk_enable(rtc_clk); 364 clk_enable(info->rtc_clk);
349 if (s3c_rtc_cpu_type == TYPE_S3C64XX) { 365 if (info->data->needs_src_clk)
350 ticnt = readw(s3c_rtc_base + S3C2410_RTCCON); 366 clk_enable(info->rtc_src_clk);
351 ticnt &= S3C64XX_RTCCON_TICEN; 367
352 } else { 368 if (info->data->enable_tick)
353 ticnt = readb(s3c_rtc_base + S3C2410_TICNT); 369 info->data->enable_tick(info, seq);
354 ticnt &= S3C2410_TICNT_ENABLE; 370
355 } 371 if (info->data->needs_src_clk)
372 clk_disable(info->rtc_src_clk);
373 clk_disable(info->rtc_clk);
356 374
357 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
358 clk_disable(rtc_clk);
359 return 0; 375 return 0;
360} 376}
361 377
@@ -368,152 +384,201 @@ static const struct rtc_class_ops s3c_rtcops = {
368 .alarm_irq_enable = s3c_rtc_setaie, 384 .alarm_irq_enable = s3c_rtc_setaie,
369}; 385};
370 386
371static void s3c_rtc_enable(struct platform_device *pdev, int en) 387static void s3c24xx_rtc_enable(struct s3c_rtc *info)
372{ 388{
373 void __iomem *base = s3c_rtc_base; 389 unsigned int con, tmp;
374 unsigned int tmp;
375 390
376 if (s3c_rtc_base == NULL) 391 clk_enable(info->rtc_clk);
377 return; 392 if (info->data->needs_src_clk)
378 393 clk_enable(info->rtc_src_clk);
379 clk_enable(rtc_clk);
380 if (!en) {
381 tmp = readw(base + S3C2410_RTCCON);
382 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
383 tmp &= ~S3C64XX_RTCCON_TICEN;
384 tmp &= ~S3C2410_RTCCON_RTCEN;
385 writew(tmp, base + S3C2410_RTCCON);
386
387 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
388 tmp = readb(base + S3C2410_TICNT);
389 tmp &= ~S3C2410_TICNT_ENABLE;
390 writeb(tmp, base + S3C2410_TICNT);
391 }
392 } else {
393 /* re-enable the device, and check it is ok */
394 394
395 if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) { 395 con = readw(info->base + S3C2410_RTCCON);
396 dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); 396 /* re-enable the device, and check it is ok */
397 if ((con & S3C2410_RTCCON_RTCEN) == 0) {
398 dev_info(info->dev, "rtc disabled, re-enabling\n");
397 399
398 tmp = readw(base + S3C2410_RTCCON); 400 tmp = readw(info->base + S3C2410_RTCCON);
399 writew(tmp | S3C2410_RTCCON_RTCEN, 401 writew(tmp | S3C2410_RTCCON_RTCEN,
400 base + S3C2410_RTCCON); 402 info->base + S3C2410_RTCCON);
401 } 403 }
402 404
403 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) { 405 if (con & S3C2410_RTCCON_CNTSEL) {
404 dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); 406 dev_info(info->dev, "removing RTCCON_CNTSEL\n");
405 407
406 tmp = readw(base + S3C2410_RTCCON); 408 tmp = readw(info->base + S3C2410_RTCCON);
407 writew(tmp & ~S3C2410_RTCCON_CNTSEL, 409 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
408 base + S3C2410_RTCCON); 410 info->base + S3C2410_RTCCON);
409 } 411 }
410 412
411 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) { 413 if (con & S3C2410_RTCCON_CLKRST) {
412 dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); 414 dev_info(info->dev, "removing RTCCON_CLKRST\n");
413 415
414 tmp = readw(base + S3C2410_RTCCON); 416 tmp = readw(info->base + S3C2410_RTCCON);
415 writew(tmp & ~S3C2410_RTCCON_CLKRST, 417 writew(tmp & ~S3C2410_RTCCON_CLKRST,
416 base + S3C2410_RTCCON); 418 info->base + S3C2410_RTCCON);
417 }
418 } 419 }
419 clk_disable(rtc_clk); 420
421 if (info->data->needs_src_clk)
422 clk_disable(info->rtc_src_clk);
423 clk_disable(info->rtc_clk);
420} 424}
421 425
422static int s3c_rtc_remove(struct platform_device *dev) 426static void s3c24xx_rtc_disable(struct s3c_rtc *info)
423{ 427{
424 s3c_rtc_setaie(&dev->dev, 0); 428 unsigned int con;
429
430 clk_enable(info->rtc_clk);
431 if (info->data->needs_src_clk)
432 clk_enable(info->rtc_src_clk);
433
434 con = readw(info->base + S3C2410_RTCCON);
435 con &= ~S3C2410_RTCCON_RTCEN;
436 writew(con, info->base + S3C2410_RTCCON);
425 437
426 clk_unprepare(rtc_clk); 438 con = readb(info->base + S3C2410_TICNT);
427 rtc_clk = NULL; 439 con &= ~S3C2410_TICNT_ENABLE;
440 writeb(con, info->base + S3C2410_TICNT);
441
442 if (info->data->needs_src_clk)
443 clk_disable(info->rtc_src_clk);
444 clk_disable(info->rtc_clk);
445}
446
447static void s3c6410_rtc_disable(struct s3c_rtc *info)
448{
449 unsigned int con;
450
451 clk_enable(info->rtc_clk);
452 if (info->data->needs_src_clk)
453 clk_enable(info->rtc_src_clk);
454
455 con = readw(info->base + S3C2410_RTCCON);
456 con &= ~S3C64XX_RTCCON_TICEN;
457 con &= ~S3C2410_RTCCON_RTCEN;
458 writew(con, info->base + S3C2410_RTCCON);
459
460 if (info->data->needs_src_clk)
461 clk_disable(info->rtc_src_clk);
462 clk_disable(info->rtc_clk);
463}
464
465static int s3c_rtc_remove(struct platform_device *pdev)
466{
467 struct s3c_rtc *info = platform_get_drvdata(pdev);
468
469 s3c_rtc_setaie(info->dev, 0);
470
471 clk_unprepare(info->rtc_clk);
472 info->rtc_clk = NULL;
428 473
429 return 0; 474 return 0;
430} 475}
431 476
432static const struct of_device_id s3c_rtc_dt_match[]; 477static const struct of_device_id s3c_rtc_dt_match[];
433 478
434static inline int s3c_rtc_get_driver_data(struct platform_device *pdev) 479static struct s3c_rtc_data *s3c_rtc_get_data(struct platform_device *pdev)
435{ 480{
436#ifdef CONFIG_OF 481 const struct of_device_id *match;
437 struct s3c_rtc_drv_data *data; 482
438 if (pdev->dev.of_node) { 483 match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
439 const struct of_device_id *match; 484 return (struct s3c_rtc_data *)match->data;
440 match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
441 data = (struct s3c_rtc_drv_data *) match->data;
442 return data->cpu_type;
443 }
444#endif
445 return platform_get_device_id(pdev)->driver_data;
446} 485}
447 486
448static int s3c_rtc_probe(struct platform_device *pdev) 487static int s3c_rtc_probe(struct platform_device *pdev)
449{ 488{
450 struct rtc_device *rtc; 489 struct s3c_rtc *info = NULL;
451 struct rtc_time rtc_tm; 490 struct rtc_time rtc_tm;
452 struct resource *res; 491 struct resource *res;
453 int ret; 492 int ret;
454 int tmp;
455 493
456 dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev); 494 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
495 if (!info)
496 return -ENOMEM;
457 497
458 /* find the IRQs */ 498 /* find the IRQs */
459 499 info->irq_tick = platform_get_irq(pdev, 1);
460 s3c_rtc_tickno = platform_get_irq(pdev, 1); 500 if (info->irq_tick < 0) {
461 if (s3c_rtc_tickno < 0) {
462 dev_err(&pdev->dev, "no irq for rtc tick\n"); 501 dev_err(&pdev->dev, "no irq for rtc tick\n");
463 return s3c_rtc_tickno; 502 return info->irq_tick;
503 }
504
505 info->dev = &pdev->dev;
506 info->data = s3c_rtc_get_data(pdev);
507 if (!info->data) {
508 dev_err(&pdev->dev, "failed getting s3c_rtc_data\n");
509 return -EINVAL;
464 } 510 }
511 spin_lock_init(&info->pie_lock);
512 spin_lock_init(&info->alarm_clk_lock);
513
514 platform_set_drvdata(pdev, info);
465 515
466 s3c_rtc_alarmno = platform_get_irq(pdev, 0); 516 info->irq_alarm = platform_get_irq(pdev, 0);
467 if (s3c_rtc_alarmno < 0) { 517 if (info->irq_alarm < 0) {
468 dev_err(&pdev->dev, "no irq for alarm\n"); 518 dev_err(&pdev->dev, "no irq for alarm\n");
469 return s3c_rtc_alarmno; 519 return info->irq_alarm;
470 } 520 }
471 521
472 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", 522 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
473 s3c_rtc_tickno, s3c_rtc_alarmno); 523 info->irq_tick, info->irq_alarm);
474 524
475 /* get the memory region */ 525 /* get the memory region */
476
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 526 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res); 527 info->base = devm_ioremap_resource(&pdev->dev, res);
479 if (IS_ERR(s3c_rtc_base)) 528 if (IS_ERR(info->base))
480 return PTR_ERR(s3c_rtc_base); 529 return PTR_ERR(info->base);
481 530
482 rtc_clk = devm_clk_get(&pdev->dev, "rtc"); 531 info->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
483 if (IS_ERR(rtc_clk)) { 532 if (IS_ERR(info->rtc_clk)) {
484 dev_err(&pdev->dev, "failed to find rtc clock source\n"); 533 dev_err(&pdev->dev, "failed to find rtc clock\n");
485 ret = PTR_ERR(rtc_clk); 534 return PTR_ERR(info->rtc_clk);
486 rtc_clk = NULL; 535 }
487 return ret; 536 clk_prepare_enable(info->rtc_clk);
537
538 if (info->data->needs_src_clk) {
539 info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src");
540 if (IS_ERR(info->rtc_src_clk)) {
541 dev_err(&pdev->dev,
542 "failed to find rtc source clock\n");
543 return PTR_ERR(info->rtc_src_clk);
544 }
545 clk_prepare_enable(info->rtc_src_clk);
488 } 546 }
489
490 clk_prepare_enable(rtc_clk);
491 547
492 /* check to see if everything is setup correctly */ 548 /* check to see if everything is setup correctly */
493 549 if (info->data->enable)
494 s3c_rtc_enable(pdev, 1); 550 info->data->enable(info);
495 551
496 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", 552 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
497 readw(s3c_rtc_base + S3C2410_RTCCON)); 553 readw(info->base + S3C2410_RTCCON));
498 554
499 device_init_wakeup(&pdev->dev, 1); 555 device_init_wakeup(&pdev->dev, 1);
500 556
501 /* register RTC and exit */ 557 /* register RTC and exit */
502 558 info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
503 rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
504 THIS_MODULE); 559 THIS_MODULE);
505 560 if (IS_ERR(info->rtc)) {
506 if (IS_ERR(rtc)) {
507 dev_err(&pdev->dev, "cannot attach rtc\n"); 561 dev_err(&pdev->dev, "cannot attach rtc\n");
508 ret = PTR_ERR(rtc); 562 ret = PTR_ERR(info->rtc);
509 goto err_nortc; 563 goto err_nortc;
510 } 564 }
511 565
512 s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev); 566 ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq,
567 0, "s3c2410-rtc alarm", info);
568 if (ret) {
569 dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret);
570 goto err_nortc;
571 }
513 572
514 /* Check RTC Time */ 573 ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq,
574 0, "s3c2410-rtc tick", info);
575 if (ret) {
576 dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret);
577 goto err_nortc;
578 }
515 579
516 s3c_rtc_gettime(NULL, &rtc_tm); 580 /* Check RTC Time */
581 s3c_rtc_gettime(&pdev->dev, &rtc_tm);
517 582
518 if (rtc_valid_tm(&rtc_tm)) { 583 if (rtc_valid_tm(&rtc_tm)) {
519 rtc_tm.tm_year = 100; 584 rtc_tm.tm_year = 100;
@@ -523,163 +588,312 @@ static int s3c_rtc_probe(struct platform_device *pdev)
523 rtc_tm.tm_min = 0; 588 rtc_tm.tm_min = 0;
524 rtc_tm.tm_sec = 0; 589 rtc_tm.tm_sec = 0;
525 590
526 s3c_rtc_settime(NULL, &rtc_tm); 591 s3c_rtc_settime(&pdev->dev, &rtc_tm);
527 592
528 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); 593 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
529 } 594 }
530 595
531 if (s3c_rtc_cpu_type != TYPE_S3C2410) 596 if (info->data->select_tick_clk)
532 rtc->max_user_freq = 32768; 597 info->data->select_tick_clk(info);
533 else
534 rtc->max_user_freq = 128;
535 598
536 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { 599 s3c_rtc_setfreq(info, 1);
537 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
538 tmp |= S3C2443_RTCCON_TICSEL;
539 writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
540 }
541 600
542 platform_set_drvdata(pdev, rtc); 601 if (info->data->needs_src_clk)
543 602 clk_disable(info->rtc_src_clk);
544 s3c_rtc_setfreq(&pdev->dev, 1); 603 clk_disable(info->rtc_clk);
545
546 ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq,
547 0, "s3c2410-rtc alarm", rtc);
548 if (ret) {
549 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
550 goto err_nortc;
551 }
552
553 ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq,
554 0, "s3c2410-rtc tick", rtc);
555 if (ret) {
556 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
557 goto err_nortc;
558 }
559
560 clk_disable(rtc_clk);
561 604
562 return 0; 605 return 0;
563 606
564 err_nortc: 607 err_nortc:
565 s3c_rtc_enable(pdev, 0); 608 if (info->data->disable)
566 clk_disable_unprepare(rtc_clk); 609 info->data->disable(info);
610 clk_disable_unprepare(info->rtc_clk);
567 611
568 return ret; 612 return ret;
569} 613}
570 614
571#ifdef CONFIG_PM_SLEEP 615#ifdef CONFIG_PM_SLEEP
572/* RTC Power management control */
573
574static int ticnt_save, ticnt_en_save;
575static bool wake_en;
576 616
577static int s3c_rtc_suspend(struct device *dev) 617static int s3c_rtc_suspend(struct device *dev)
578{ 618{
579 struct platform_device *pdev = to_platform_device(dev); 619 struct s3c_rtc *info = dev_get_drvdata(dev);
620
621 clk_enable(info->rtc_clk);
622 if (info->data->needs_src_clk)
623 clk_enable(info->rtc_src_clk);
580 624
581 clk_enable(rtc_clk);
582 /* save TICNT for anyone using periodic interrupts */ 625 /* save TICNT for anyone using periodic interrupts */
583 if (s3c_rtc_cpu_type == TYPE_S3C64XX) { 626 if (info->data->save_tick_cnt)
584 ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON); 627 info->data->save_tick_cnt(info);
585 ticnt_en_save &= S3C64XX_RTCCON_TICEN;
586 ticnt_save = readl(s3c_rtc_base + S3C2410_TICNT);
587 } else {
588 ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
589 }
590 s3c_rtc_enable(pdev, 0);
591 628
592 if (device_may_wakeup(dev) && !wake_en) { 629 if (info->data->disable)
593 if (enable_irq_wake(s3c_rtc_alarmno) == 0) 630 info->data->disable(info);
594 wake_en = true; 631
632 if (device_may_wakeup(dev) && !info->wake_en) {
633 if (enable_irq_wake(info->irq_alarm) == 0)
634 info->wake_en = true;
595 else 635 else
596 dev_err(dev, "enable_irq_wake failed\n"); 636 dev_err(dev, "enable_irq_wake failed\n");
597 } 637 }
598 clk_disable(rtc_clk); 638
639 if (info->data->needs_src_clk)
640 clk_disable(info->rtc_src_clk);
641 clk_disable(info->rtc_clk);
599 642
600 return 0; 643 return 0;
601} 644}
602 645
603static int s3c_rtc_resume(struct device *dev) 646static int s3c_rtc_resume(struct device *dev)
604{ 647{
605 struct platform_device *pdev = to_platform_device(dev); 648 struct s3c_rtc *info = dev_get_drvdata(dev);
606 unsigned int tmp;
607 649
608 clk_enable(rtc_clk); 650 clk_enable(info->rtc_clk);
609 s3c_rtc_enable(pdev, 1); 651 if (info->data->needs_src_clk)
610 if (s3c_rtc_cpu_type == TYPE_S3C64XX) { 652 clk_enable(info->rtc_src_clk);
611 writel(ticnt_save, s3c_rtc_base + S3C2410_TICNT); 653
612 if (ticnt_en_save) { 654 if (info->data->enable)
613 tmp = readw(s3c_rtc_base + S3C2410_RTCCON); 655 info->data->enable(info);
614 writew(tmp | ticnt_en_save, 656
615 s3c_rtc_base + S3C2410_RTCCON); 657 if (info->data->restore_tick_cnt)
616 } 658 info->data->restore_tick_cnt(info);
617 } else {
618 writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
619 }
620 659
621 if (device_may_wakeup(dev) && wake_en) { 660 if (device_may_wakeup(dev) && info->wake_en) {
622 disable_irq_wake(s3c_rtc_alarmno); 661 disable_irq_wake(info->irq_alarm);
623 wake_en = false; 662 info->wake_en = false;
624 } 663 }
625 clk_disable(rtc_clk); 664
665 if (info->data->needs_src_clk)
666 clk_disable(info->rtc_src_clk);
667 clk_disable(info->rtc_clk);
626 668
627 return 0; 669 return 0;
628} 670}
629#endif 671#endif
630
631static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); 672static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
632 673
633#ifdef CONFIG_OF 674static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask)
634static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = { 675{
635 [TYPE_S3C2410] = { TYPE_S3C2410 }, 676 clk_enable(info->rtc_clk);
636 [TYPE_S3C2416] = { TYPE_S3C2416 }, 677 if (info->data->needs_src_clk)
637 [TYPE_S3C2443] = { TYPE_S3C2443 }, 678 clk_enable(info->rtc_src_clk);
638 [TYPE_S3C64XX] = { TYPE_S3C64XX }, 679 rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
680 if (info->data->needs_src_clk)
681 clk_disable(info->rtc_src_clk);
682 clk_disable(info->rtc_clk);
683
684 s3c_rtc_alarm_clk_enable(info, false);
685}
686
687static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask)
688{
689 clk_enable(info->rtc_clk);
690 if (info->data->needs_src_clk)
691 clk_enable(info->rtc_src_clk);
692 rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
693 writeb(mask, info->base + S3C2410_INTP);
694 if (info->data->needs_src_clk)
695 clk_disable(info->rtc_src_clk);
696 clk_disable(info->rtc_clk);
697
698 s3c_rtc_alarm_clk_enable(info, false);
699}
700
701static void s3c2410_rtc_setfreq(struct s3c_rtc *info, int freq)
702{
703 unsigned int tmp = 0;
704 int val;
705
706 tmp = readb(info->base + S3C2410_TICNT);
707 tmp &= S3C2410_TICNT_ENABLE;
708
709 val = (info->rtc->max_user_freq / freq) - 1;
710 tmp |= val;
711
712 writel(tmp, info->base + S3C2410_TICNT);
713}
714
715static void s3c2416_rtc_setfreq(struct s3c_rtc *info, int freq)
716{
717 unsigned int tmp = 0;
718 int val;
719
720 tmp = readb(info->base + S3C2410_TICNT);
721 tmp &= S3C2410_TICNT_ENABLE;
722
723 val = (info->rtc->max_user_freq / freq) - 1;
724
725 tmp |= S3C2443_TICNT_PART(val);
726 writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1);
727
728 writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2);
729
730 writel(tmp, info->base + S3C2410_TICNT);
731}
732
733static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq)
734{
735 unsigned int tmp = 0;
736 int val;
737
738 tmp = readb(info->base + S3C2410_TICNT);
739 tmp &= S3C2410_TICNT_ENABLE;
740
741 val = (info->rtc->max_user_freq / freq) - 1;
742
743 tmp |= S3C2443_TICNT_PART(val);
744 writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1);
745
746 writel(tmp, info->base + S3C2410_TICNT);
747}
748
749static void s3c6410_rtc_setfreq(struct s3c_rtc *info, int freq)
750{
751 int val;
752
753 val = (info->rtc->max_user_freq / freq) - 1;
754 writel(val, info->base + S3C2410_TICNT);
755}
756
757static void s3c24xx_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq)
758{
759 unsigned int ticnt;
760
761 ticnt = readb(info->base + S3C2410_TICNT);
762 ticnt &= S3C2410_TICNT_ENABLE;
763
764 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
765}
766
767static void s3c2416_rtc_select_tick_clk(struct s3c_rtc *info)
768{
769 unsigned int con;
770
771 con = readw(info->base + S3C2410_RTCCON);
772 con |= S3C2443_RTCCON_TICSEL;
773 writew(con, info->base + S3C2410_RTCCON);
774}
775
776static void s3c6410_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq)
777{
778 unsigned int ticnt;
779
780 ticnt = readw(info->base + S3C2410_RTCCON);
781 ticnt &= S3C64XX_RTCCON_TICEN;
782
783 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
784}
785
786static void s3c24xx_rtc_save_tick_cnt(struct s3c_rtc *info)
787{
788 info->ticnt_save = readb(info->base + S3C2410_TICNT);
789}
790
791static void s3c24xx_rtc_restore_tick_cnt(struct s3c_rtc *info)
792{
793 writeb(info->ticnt_save, info->base + S3C2410_TICNT);
794}
795
796static void s3c6410_rtc_save_tick_cnt(struct s3c_rtc *info)
797{
798 info->ticnt_en_save = readw(info->base + S3C2410_RTCCON);
799 info->ticnt_en_save &= S3C64XX_RTCCON_TICEN;
800 info->ticnt_save = readl(info->base + S3C2410_TICNT);
801}
802
803static void s3c6410_rtc_restore_tick_cnt(struct s3c_rtc *info)
804{
805 unsigned int con;
806
807 writel(info->ticnt_save, info->base + S3C2410_TICNT);
808 if (info->ticnt_en_save) {
809 con = readw(info->base + S3C2410_RTCCON);
810 writew(con | info->ticnt_en_save,
811 info->base + S3C2410_RTCCON);
812 }
813}
814
815static struct s3c_rtc_data const s3c2410_rtc_data = {
816 .max_user_freq = 128,
817 .irq_handler = s3c24xx_rtc_irq,
818 .set_freq = s3c2410_rtc_setfreq,
819 .enable_tick = s3c24xx_rtc_enable_tick,
820 .save_tick_cnt = s3c24xx_rtc_save_tick_cnt,
821 .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt,
822 .enable = s3c24xx_rtc_enable,
823 .disable = s3c24xx_rtc_disable,
824};
825
826static struct s3c_rtc_data const s3c2416_rtc_data = {
827 .max_user_freq = 32768,
828 .irq_handler = s3c24xx_rtc_irq,
829 .set_freq = s3c2416_rtc_setfreq,
830 .enable_tick = s3c24xx_rtc_enable_tick,
831 .select_tick_clk = s3c2416_rtc_select_tick_clk,
832 .save_tick_cnt = s3c24xx_rtc_save_tick_cnt,
833 .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt,
834 .enable = s3c24xx_rtc_enable,
835 .disable = s3c24xx_rtc_disable,
836};
837
838static struct s3c_rtc_data const s3c2443_rtc_data = {
839 .max_user_freq = 32768,
840 .irq_handler = s3c24xx_rtc_irq,
841 .set_freq = s3c2443_rtc_setfreq,
842 .enable_tick = s3c24xx_rtc_enable_tick,
843 .select_tick_clk = s3c2416_rtc_select_tick_clk,
844 .save_tick_cnt = s3c24xx_rtc_save_tick_cnt,
845 .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt,
846 .enable = s3c24xx_rtc_enable,
847 .disable = s3c24xx_rtc_disable,
848};
849
850static struct s3c_rtc_data const s3c6410_rtc_data = {
851 .max_user_freq = 32768,
852 .irq_handler = s3c6410_rtc_irq,
853 .set_freq = s3c6410_rtc_setfreq,
854 .enable_tick = s3c6410_rtc_enable_tick,
855 .save_tick_cnt = s3c6410_rtc_save_tick_cnt,
856 .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt,
857 .enable = s3c24xx_rtc_enable,
858 .disable = s3c6410_rtc_disable,
859};
860
861static struct s3c_rtc_data const exynos3250_rtc_data = {
862 .max_user_freq = 32768,
863 .needs_src_clk = true,
864 .irq_handler = s3c6410_rtc_irq,
865 .set_freq = s3c6410_rtc_setfreq,
866 .enable_tick = s3c6410_rtc_enable_tick,
867 .save_tick_cnt = s3c6410_rtc_save_tick_cnt,
868 .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt,
869 .enable = s3c24xx_rtc_enable,
870 .disable = s3c6410_rtc_disable,
639}; 871};
640 872
641static const struct of_device_id s3c_rtc_dt_match[] = { 873static const struct of_device_id s3c_rtc_dt_match[] = {
642 { 874 {
643 .compatible = "samsung,s3c2410-rtc", 875 .compatible = "samsung,s3c2410-rtc",
644 .data = &s3c_rtc_drv_data_array[TYPE_S3C2410], 876 .data = (void *)&s3c2410_rtc_data,
645 }, { 877 }, {
646 .compatible = "samsung,s3c2416-rtc", 878 .compatible = "samsung,s3c2416-rtc",
647 .data = &s3c_rtc_drv_data_array[TYPE_S3C2416], 879 .data = (void *)&s3c2416_rtc_data,
648 }, { 880 }, {
649 .compatible = "samsung,s3c2443-rtc", 881 .compatible = "samsung,s3c2443-rtc",
650 .data = &s3c_rtc_drv_data_array[TYPE_S3C2443], 882 .data = (void *)&s3c2443_rtc_data,
651 }, { 883 }, {
652 .compatible = "samsung,s3c6410-rtc", 884 .compatible = "samsung,s3c6410-rtc",
653 .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX], 885 .data = (void *)&s3c6410_rtc_data,
654 },
655 {},
656};
657MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
658#endif
659
660static struct platform_device_id s3c_rtc_driver_ids[] = {
661 {
662 .name = "s3c2410-rtc",
663 .driver_data = TYPE_S3C2410,
664 }, {
665 .name = "s3c2416-rtc",
666 .driver_data = TYPE_S3C2416,
667 }, {
668 .name = "s3c2443-rtc",
669 .driver_data = TYPE_S3C2443,
670 }, { 886 }, {
671 .name = "s3c64xx-rtc", 887 .compatible = "samsung,exynos3250-rtc",
672 .driver_data = TYPE_S3C64XX, 888 .data = (void *)&exynos3250_rtc_data,
673 }, 889 },
674 { } 890 { /* sentinel */ },
675}; 891};
676 892MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
677MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
678 893
679static struct platform_driver s3c_rtc_driver = { 894static struct platform_driver s3c_rtc_driver = {
680 .probe = s3c_rtc_probe, 895 .probe = s3c_rtc_probe,
681 .remove = s3c_rtc_remove, 896 .remove = s3c_rtc_remove,
682 .id_table = s3c_rtc_driver_ids,
683 .driver = { 897 .driver = {
684 .name = "s3c-rtc", 898 .name = "s3c-rtc",
685 .owner = THIS_MODULE, 899 .owner = THIS_MODULE,
@@ -687,7 +901,6 @@ static struct platform_driver s3c_rtc_driver = {
687 .of_match_table = of_match_ptr(s3c_rtc_dt_match), 901 .of_match_table = of_match_ptr(s3c_rtc_dt_match),
688 }, 902 },
689}; 903};
690
691module_platform_driver(s3c_rtc_driver); 904module_platform_driver(s3c_rtc_driver);
692 905
693MODULE_DESCRIPTION("Samsung S3C RTC Driver"); 906MODULE_DESCRIPTION("Samsung S3C RTC Driver");
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
new file mode 100644
index 000000000000..c169a2cd4727
--- /dev/null
+++ b/drivers/rtc/rtc-sun6i.c
@@ -0,0 +1,447 @@
1/*
2 * An RTC driver for Allwinner A31/A23
3 *
4 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
5 *
6 * based on rtc-sunxi.c
7 *
8 * An RTC driver for Allwinner A10/A20
9 *
10 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 */
22
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/fs.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_device.h>
34#include <linux/platform_device.h>
35#include <linux/rtc.h>
36#include <linux/types.h>
37
38/* Control register */
39#define SUN6I_LOSC_CTRL 0x0000
40#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
41#define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
42#define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
43#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
44
45/* RTC */
46#define SUN6I_RTC_YMD 0x0010
47#define SUN6I_RTC_HMS 0x0014
48
49/* Alarm 0 (counter) */
50#define SUN6I_ALRM_COUNTER 0x0020
51#define SUN6I_ALRM_CUR_VAL 0x0024
52#define SUN6I_ALRM_EN 0x0028
53#define SUN6I_ALRM_EN_CNT_EN BIT(0)
54#define SUN6I_ALRM_IRQ_EN 0x002c
55#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
56#define SUN6I_ALRM_IRQ_STA 0x0030
57#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
58
59/* Alarm 1 (wall clock) */
60#define SUN6I_ALRM1_EN 0x0044
61#define SUN6I_ALRM1_IRQ_EN 0x0048
62#define SUN6I_ALRM1_IRQ_STA 0x004c
63#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
64
65/* Alarm config */
66#define SUN6I_ALARM_CONFIG 0x0050
67#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
68
69/*
70 * Get date values
71 */
72#define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
73#define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
74#define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
75#define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
76
77/*
78 * Get time values
79 */
80#define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
81#define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
82#define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
83
84/*
85 * Set date values
86 */
87#define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
88#define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
89#define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
90#define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
91
92/*
93 * Set time values
94 */
95#define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
96#define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
97#define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
98
99/*
100 * The year parameter passed to the driver is usually an offset relative to
101 * the year 1900. This macro is used to convert this offset to another one
102 * relative to the minimum year allowed by the hardware.
103 *
104 * The year range is 1970 - 2033. This range is selected to match Allwinner's
105 * driver, even though it is somewhat limited.
106 */
107#define SUN6I_YEAR_MIN 1970
108#define SUN6I_YEAR_MAX 2033
109#define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
110
111struct sun6i_rtc_dev {
112 struct rtc_device *rtc;
113 struct device *dev;
114 void __iomem *base;
115 int irq;
116 unsigned long alarm;
117};
118
119static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
120{
121 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
122 u32 val;
123
124 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
125
126 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
127 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
128 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
129
130 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
131
132 return IRQ_HANDLED;
133 }
134
135 return IRQ_NONE;
136}
137
138static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
139{
140 u32 alrm_val = 0;
141 u32 alrm_irq_val = 0;
142 u32 alrm_wake_val = 0;
143
144 if (to) {
145 alrm_val = SUN6I_ALRM_EN_CNT_EN;
146 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
147 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
148 } else {
149 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
150 chip->base + SUN6I_ALRM_IRQ_STA);
151 }
152
153 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
154 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
155 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
156}
157
158static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
159{
160 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
161 u32 date, time;
162
163 /*
164 * read again in case it changes
165 */
166 do {
167 date = readl(chip->base + SUN6I_RTC_YMD);
168 time = readl(chip->base + SUN6I_RTC_HMS);
169 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
170 (time != readl(chip->base + SUN6I_RTC_HMS)));
171
172 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
173 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
174 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
175
176 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
177 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
178 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
179
180 rtc_tm->tm_mon -= 1;
181
182 /*
183 * switch from (data_year->min)-relative offset to
184 * a (1900)-relative one
185 */
186 rtc_tm->tm_year += SUN6I_YEAR_OFF;
187
188 return rtc_valid_tm(rtc_tm);
189}
190
191static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
192{
193 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
194 u32 alrm_st;
195 u32 alrm_en;
196
197 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
198 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
199 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
200 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
201 rtc_time_to_tm(chip->alarm, &wkalrm->time);
202
203 return 0;
204}
205
206static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
207{
208 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
209 struct rtc_time *alrm_tm = &wkalrm->time;
210 struct rtc_time tm_now;
211 unsigned long time_now = 0;
212 unsigned long time_set = 0;
213 unsigned long time_gap = 0;
214 int ret = 0;
215
216 ret = sun6i_rtc_gettime(dev, &tm_now);
217 if (ret < 0) {
218 dev_err(dev, "Error in getting time\n");
219 return -EINVAL;
220 }
221
222 rtc_tm_to_time(alrm_tm, &time_set);
223 rtc_tm_to_time(&tm_now, &time_now);
224 if (time_set <= time_now) {
225 dev_err(dev, "Date to set in the past\n");
226 return -EINVAL;
227 }
228
229 time_gap = time_set - time_now;
230
231 if (time_gap > U32_MAX) {
232 dev_err(dev, "Date too far in the future\n");
233 return -EINVAL;
234 }
235
236 sun6i_rtc_setaie(0, chip);
237 writel(0, chip->base + SUN6I_ALRM_COUNTER);
238 usleep_range(100, 300);
239
240 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
241 chip->alarm = time_set;
242
243 sun6i_rtc_setaie(wkalrm->enabled, chip);
244
245 return 0;
246}
247
248static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
249 unsigned int mask, unsigned int ms_timeout)
250{
251 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
252 u32 reg;
253
254 do {
255 reg = readl(chip->base + offset);
256 reg &= mask;
257
258 if (!reg)
259 return 0;
260
261 } while (time_before(jiffies, timeout));
262
263 return -ETIMEDOUT;
264}
265
266static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
267{
268 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
269 u32 date = 0;
270 u32 time = 0;
271 int year;
272
273 year = rtc_tm->tm_year + 1900;
274 if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
275 dev_err(dev, "rtc only supports year in range %d - %d\n",
276 SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
277 return -EINVAL;
278 }
279
280 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
281 rtc_tm->tm_mon += 1;
282
283 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
284 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
285 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
286
287 if (is_leap_year(year))
288 date |= SUN6I_LEAP_SET_VALUE(1);
289
290 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
291 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
292 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
293
294 /* Check whether registers are writable */
295 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
296 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
297 dev_err(dev, "rtc is still busy.\n");
298 return -EBUSY;
299 }
300
301 writel(time, chip->base + SUN6I_RTC_HMS);
302
303 /*
304 * After writing the RTC HH-MM-SS register, the
305 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
306 * be cleared until the real writing operation is finished
307 */
308
309 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
310 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
311 dev_err(dev, "Failed to set rtc time.\n");
312 return -ETIMEDOUT;
313 }
314
315 writel(date, chip->base + SUN6I_RTC_YMD);
316
317 /*
318 * After writing the RTC YY-MM-DD register, the
319 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
320 * be cleared until the real writing operation is finished
321 */
322
323 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
324 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
325 dev_err(dev, "Failed to set rtc time.\n");
326 return -ETIMEDOUT;
327 }
328
329 return 0;
330}
331
332static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
333{
334 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
335
336 if (!enabled)
337 sun6i_rtc_setaie(enabled, chip);
338
339 return 0;
340}
341
342static const struct rtc_class_ops sun6i_rtc_ops = {
343 .read_time = sun6i_rtc_gettime,
344 .set_time = sun6i_rtc_settime,
345 .read_alarm = sun6i_rtc_getalarm,
346 .set_alarm = sun6i_rtc_setalarm,
347 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
348};
349
350static int sun6i_rtc_probe(struct platform_device *pdev)
351{
352 struct sun6i_rtc_dev *chip;
353 struct resource *res;
354 int ret;
355
356 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
357 if (!chip)
358 return -ENOMEM;
359
360 platform_set_drvdata(pdev, chip);
361 chip->dev = &pdev->dev;
362
363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364 chip->base = devm_ioremap_resource(&pdev->dev, res);
365 if (IS_ERR(chip->base))
366 return PTR_ERR(chip->base);
367
368 chip->irq = platform_get_irq(pdev, 0);
369 if (chip->irq < 0) {
370 dev_err(&pdev->dev, "No IRQ resource\n");
371 return chip->irq;
372 }
373
374 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
375 0, dev_name(&pdev->dev), chip);
376 if (ret) {
377 dev_err(&pdev->dev, "Could not request IRQ\n");
378 return ret;
379 }
380
381 /* clear the alarm counter value */
382 writel(0, chip->base + SUN6I_ALRM_COUNTER);
383
384 /* disable counter alarm */
385 writel(0, chip->base + SUN6I_ALRM_EN);
386
387 /* disable counter alarm interrupt */
388 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
389
390 /* disable week alarm */
391 writel(0, chip->base + SUN6I_ALRM1_EN);
392
393 /* disable week alarm interrupt */
394 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
395
396 /* clear counter alarm pending interrupts */
397 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
398 chip->base + SUN6I_ALRM_IRQ_STA);
399
400 /* clear week alarm pending interrupts */
401 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
402 chip->base + SUN6I_ALRM1_IRQ_STA);
403
404 /* disable alarm wakeup */
405 writel(0, chip->base + SUN6I_ALARM_CONFIG);
406
407 chip->rtc = rtc_device_register("rtc-sun6i", &pdev->dev,
408 &sun6i_rtc_ops, THIS_MODULE);
409 if (IS_ERR(chip->rtc)) {
410 dev_err(&pdev->dev, "unable to register device\n");
411 return PTR_ERR(chip->rtc);
412 }
413
414 dev_info(&pdev->dev, "RTC enabled\n");
415
416 return 0;
417}
418
419static int sun6i_rtc_remove(struct platform_device *pdev)
420{
421 struct sun6i_rtc_dev *chip = platform_get_drvdata(pdev);
422
423 rtc_device_unregister(chip->rtc);
424
425 return 0;
426}
427
428static const struct of_device_id sun6i_rtc_dt_ids[] = {
429 { .compatible = "allwinner,sun6i-a31-rtc" },
430 { /* sentinel */ },
431};
432MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
433
434static struct platform_driver sun6i_rtc_driver = {
435 .probe = sun6i_rtc_probe,
436 .remove = sun6i_rtc_remove,
437 .driver = {
438 .name = "sun6i-rtc",
439 .of_match_table = sun6i_rtc_dt_ids,
440 },
441};
442
443module_platform_driver(sun6i_rtc_driver);
444
445MODULE_DESCRIPTION("sun6i RTC driver");
446MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
447MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-02 15:24:17 -0500