diff options
Diffstat (limited to 'drivers/rtc')
-rw-r--r-- | drivers/rtc/rtc-pm8xxx.c | 145 |
1 files changed, 57 insertions, 88 deletions
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index af60ee46075d..cdc9dc211eb0 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c | |||
@@ -13,11 +13,12 @@ | |||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/rtc.h> | 15 | #include <linux/rtc.h> |
16 | #include <linux/platform_device.h> | ||
16 | #include <linux/pm.h> | 17 | #include <linux/pm.h> |
18 | #include <linux/regmap.h> | ||
17 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
18 | #include <linux/spinlock.h> | 20 | #include <linux/spinlock.h> |
19 | 21 | ||
20 | #include <linux/mfd/pm8xxx/core.h> | ||
21 | #include <linux/mfd/pm8xxx/rtc.h> | 22 | #include <linux/mfd/pm8xxx/rtc.h> |
22 | 23 | ||
23 | 24 | ||
@@ -37,6 +38,7 @@ | |||
37 | /** | 38 | /** |
38 | * struct pm8xxx_rtc - rtc driver internal structure | 39 | * struct pm8xxx_rtc - rtc driver internal structure |
39 | * @rtc: rtc device for this driver. | 40 | * @rtc: rtc device for this driver. |
41 | * @regmap: regmap used to access RTC registers | ||
40 | * @rtc_alarm_irq: rtc alarm irq number. | 42 | * @rtc_alarm_irq: rtc alarm irq number. |
41 | * @rtc_base: address of rtc control register. | 43 | * @rtc_base: address of rtc control register. |
42 | * @rtc_read_base: base address of read registers. | 44 | * @rtc_read_base: base address of read registers. |
@@ -48,6 +50,7 @@ | |||
48 | */ | 50 | */ |
49 | struct pm8xxx_rtc { | 51 | struct pm8xxx_rtc { |
50 | struct rtc_device *rtc; | 52 | struct rtc_device *rtc; |
53 | struct regmap *regmap; | ||
51 | int rtc_alarm_irq; | 54 | int rtc_alarm_irq; |
52 | int rtc_base; | 55 | int rtc_base; |
53 | int rtc_read_base; | 56 | int rtc_read_base; |
@@ -59,44 +62,6 @@ struct pm8xxx_rtc { | |||
59 | }; | 62 | }; |
60 | 63 | ||
61 | /* | 64 | /* |
62 | * The RTC registers need to be read/written one byte at a time. This is a | ||
63 | * hardware limitation. | ||
64 | */ | ||
65 | static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val, | ||
66 | int base, int count) | ||
67 | { | ||
68 | int i, rc; | ||
69 | struct device *parent = rtc_dd->rtc_dev->parent; | ||
70 | |||
71 | for (i = 0; i < count; i++) { | ||
72 | rc = pm8xxx_readb(parent, base + i, &rtc_val[i]); | ||
73 | if (rc < 0) { | ||
74 | dev_err(rtc_dd->rtc_dev, "PMIC read failed\n"); | ||
75 | return rc; | ||
76 | } | ||
77 | } | ||
78 | |||
79 | return 0; | ||
80 | } | ||
81 | |||
82 | static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val, | ||
83 | int base, int count) | ||
84 | { | ||
85 | int i, rc; | ||
86 | struct device *parent = rtc_dd->rtc_dev->parent; | ||
87 | |||
88 | for (i = 0; i < count; i++) { | ||
89 | rc = pm8xxx_writeb(parent, base + i, rtc_val[i]); | ||
90 | if (rc < 0) { | ||
91 | dev_err(rtc_dd->rtc_dev, "PMIC write failed\n"); | ||
92 | return rc; | ||
93 | } | ||
94 | } | ||
95 | |||
96 | return 0; | ||
97 | } | ||
98 | |||
99 | /* | ||
100 | * Steps to write the RTC registers. | 65 | * Steps to write the RTC registers. |
101 | * 1. Disable alarm if enabled. | 66 | * 1. Disable alarm if enabled. |
102 | * 2. Write 0x00 to LSB. | 67 | * 2. Write 0x00 to LSB. |
@@ -107,7 +72,7 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
107 | { | 72 | { |
108 | int rc, i; | 73 | int rc, i; |
109 | unsigned long secs, irq_flags; | 74 | unsigned long secs, irq_flags; |
110 | u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg; | 75 | u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg; |
111 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | 76 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
112 | 77 | ||
113 | rtc_tm_to_time(tm, &secs); | 78 | rtc_tm_to_time(tm, &secs); |
@@ -125,9 +90,8 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
125 | if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) { | 90 | if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) { |
126 | alarm_enabled = 1; | 91 | alarm_enabled = 1; |
127 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; | 92 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; |
128 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, | 93 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); |
129 | 1); | 94 | if (rc) { |
130 | if (rc < 0) { | ||
131 | dev_err(dev, "Write to RTC control register failed\n"); | 95 | dev_err(dev, "Write to RTC control register failed\n"); |
132 | goto rtc_rw_fail; | 96 | goto rtc_rw_fail; |
133 | } | 97 | } |
@@ -137,33 +101,31 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
137 | } | 101 | } |
138 | 102 | ||
139 | /* Write 0 to Byte[0] */ | 103 | /* Write 0 to Byte[0] */ |
140 | reg = 0; | 104 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0); |
141 | rc = pm8xxx_write_wrapper(rtc_dd, ®, rtc_dd->rtc_write_base, 1); | 105 | if (rc) { |
142 | if (rc < 0) { | ||
143 | dev_err(dev, "Write to RTC write data register failed\n"); | 106 | dev_err(dev, "Write to RTC write data register failed\n"); |
144 | goto rtc_rw_fail; | 107 | goto rtc_rw_fail; |
145 | } | 108 | } |
146 | 109 | ||
147 | /* Write Byte[1], Byte[2], Byte[3] */ | 110 | /* Write Byte[1], Byte[2], Byte[3] */ |
148 | rc = pm8xxx_write_wrapper(rtc_dd, value + 1, | 111 | rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1, |
149 | rtc_dd->rtc_write_base + 1, 3); | 112 | &value[1], sizeof(value) - 1); |
150 | if (rc < 0) { | 113 | if (rc) { |
151 | dev_err(dev, "Write to RTC write data register failed\n"); | 114 | dev_err(dev, "Write to RTC write data register failed\n"); |
152 | goto rtc_rw_fail; | 115 | goto rtc_rw_fail; |
153 | } | 116 | } |
154 | 117 | ||
155 | /* Write Byte[0] */ | 118 | /* Write Byte[0] */ |
156 | rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->rtc_write_base, 1); | 119 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, value[0]); |
157 | if (rc < 0) { | 120 | if (rc) { |
158 | dev_err(dev, "Write to RTC write data register failed\n"); | 121 | dev_err(dev, "Write to RTC write data register failed\n"); |
159 | goto rtc_rw_fail; | 122 | goto rtc_rw_fail; |
160 | } | 123 | } |
161 | 124 | ||
162 | if (alarm_enabled) { | 125 | if (alarm_enabled) { |
163 | ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; | 126 | ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; |
164 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, | 127 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); |
165 | 1); | 128 | if (rc) { |
166 | if (rc < 0) { | ||
167 | dev_err(dev, "Write to RTC control register failed\n"); | 129 | dev_err(dev, "Write to RTC control register failed\n"); |
168 | goto rtc_rw_fail; | 130 | goto rtc_rw_fail; |
169 | } | 131 | } |
@@ -180,13 +142,14 @@ rtc_rw_fail: | |||
180 | static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) | 142 | static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) |
181 | { | 143 | { |
182 | int rc; | 144 | int rc; |
183 | u8 value[NUM_8_BIT_RTC_REGS], reg; | 145 | u8 value[NUM_8_BIT_RTC_REGS]; |
184 | unsigned long secs; | 146 | unsigned long secs; |
147 | unsigned int reg; | ||
185 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | 148 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
186 | 149 | ||
187 | rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base, | 150 | rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base, |
188 | NUM_8_BIT_RTC_REGS); | 151 | value, sizeof(value)); |
189 | if (rc < 0) { | 152 | if (rc) { |
190 | dev_err(dev, "RTC read data register failed\n"); | 153 | dev_err(dev, "RTC read data register failed\n"); |
191 | return rc; | 154 | return rc; |
192 | } | 155 | } |
@@ -195,17 +158,16 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) | |||
195 | * Read the LSB again and check if there has been a carry over. | 158 | * Read the LSB again and check if there has been a carry over. |
196 | * If there is, redo the read operation. | 159 | * If there is, redo the read operation. |
197 | */ | 160 | */ |
198 | rc = pm8xxx_read_wrapper(rtc_dd, ®, rtc_dd->rtc_read_base, 1); | 161 | rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_read_base, ®); |
199 | if (rc < 0) { | 162 | if (rc < 0) { |
200 | dev_err(dev, "RTC read data register failed\n"); | 163 | dev_err(dev, "RTC read data register failed\n"); |
201 | return rc; | 164 | return rc; |
202 | } | 165 | } |
203 | 166 | ||
204 | if (unlikely(reg < value[0])) { | 167 | if (unlikely(reg < value[0])) { |
205 | rc = pm8xxx_read_wrapper(rtc_dd, value, | 168 | rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base, |
206 | rtc_dd->rtc_read_base, | 169 | value, sizeof(value)); |
207 | NUM_8_BIT_RTC_REGS); | 170 | if (rc) { |
208 | if (rc < 0) { | ||
209 | dev_err(dev, "RTC read data register failed\n"); | 171 | dev_err(dev, "RTC read data register failed\n"); |
210 | return rc; | 172 | return rc; |
211 | } | 173 | } |
@@ -244,9 +206,9 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
244 | 206 | ||
245 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | 207 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); |
246 | 208 | ||
247 | rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base, | 209 | rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->alarm_rw_base, value, |
248 | NUM_8_BIT_RTC_REGS); | 210 | sizeof(value)); |
249 | if (rc < 0) { | 211 | if (rc) { |
250 | dev_err(dev, "Write to RTC ALARM register failed\n"); | 212 | dev_err(dev, "Write to RTC ALARM register failed\n"); |
251 | goto rtc_rw_fail; | 213 | goto rtc_rw_fail; |
252 | } | 214 | } |
@@ -258,8 +220,8 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
258 | else | 220 | else |
259 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; | 221 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; |
260 | 222 | ||
261 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); | 223 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); |
262 | if (rc < 0) { | 224 | if (rc) { |
263 | dev_err(dev, "Write to RTC control register failed\n"); | 225 | dev_err(dev, "Write to RTC control register failed\n"); |
264 | goto rtc_rw_fail; | 226 | goto rtc_rw_fail; |
265 | } | 227 | } |
@@ -282,9 +244,9 @@ static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
282 | unsigned long secs; | 244 | unsigned long secs; |
283 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | 245 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
284 | 246 | ||
285 | rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base, | 247 | rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->alarm_rw_base, value, |
286 | NUM_8_BIT_RTC_REGS); | 248 | sizeof(value)); |
287 | if (rc < 0) { | 249 | if (rc) { |
288 | dev_err(dev, "RTC alarm time read failed\n"); | 250 | dev_err(dev, "RTC alarm time read failed\n"); |
289 | return rc; | 251 | return rc; |
290 | } | 252 | } |
@@ -323,8 +285,8 @@ static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) | |||
323 | else | 285 | else |
324 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; | 286 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; |
325 | 287 | ||
326 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); | 288 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); |
327 | if (rc < 0) { | 289 | if (rc) { |
328 | dev_err(dev, "Write to RTC control register failed\n"); | 290 | dev_err(dev, "Write to RTC control register failed\n"); |
329 | goto rtc_rw_fail; | 291 | goto rtc_rw_fail; |
330 | } | 292 | } |
@@ -346,7 +308,7 @@ static struct rtc_class_ops pm8xxx_rtc_ops = { | |||
346 | static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) | 308 | static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) |
347 | { | 309 | { |
348 | struct pm8xxx_rtc *rtc_dd = dev_id; | 310 | struct pm8xxx_rtc *rtc_dd = dev_id; |
349 | u8 ctrl_reg; | 311 | unsigned int ctrl_reg; |
350 | int rc; | 312 | int rc; |
351 | unsigned long irq_flags; | 313 | unsigned long irq_flags; |
352 | 314 | ||
@@ -358,8 +320,8 @@ static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) | |||
358 | ctrl_reg = rtc_dd->ctrl_reg; | 320 | ctrl_reg = rtc_dd->ctrl_reg; |
359 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; | 321 | ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; |
360 | 322 | ||
361 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); | 323 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); |
362 | if (rc < 0) { | 324 | if (rc) { |
363 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | 325 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
364 | dev_err(rtc_dd->rtc_dev, | 326 | dev_err(rtc_dd->rtc_dev, |
365 | "Write to RTC control register failed\n"); | 327 | "Write to RTC control register failed\n"); |
@@ -370,18 +332,20 @@ static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) | |||
370 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | 332 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
371 | 333 | ||
372 | /* Clear RTC alarm register */ | 334 | /* Clear RTC alarm register */ |
373 | rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base + | 335 | rc = regmap_read(rtc_dd->regmap, |
374 | PM8XXX_ALARM_CTRL_OFFSET, 1); | 336 | rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET, |
375 | if (rc < 0) { | 337 | &ctrl_reg); |
338 | if (rc) { | ||
376 | dev_err(rtc_dd->rtc_dev, | 339 | dev_err(rtc_dd->rtc_dev, |
377 | "RTC Alarm control register read failed\n"); | 340 | "RTC Alarm control register read failed\n"); |
378 | goto rtc_alarm_handled; | 341 | goto rtc_alarm_handled; |
379 | } | 342 | } |
380 | 343 | ||
381 | ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR; | 344 | ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR; |
382 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base + | 345 | rc = regmap_write(rtc_dd->regmap, |
383 | PM8XXX_ALARM_CTRL_OFFSET, 1); | 346 | rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET, |
384 | if (rc < 0) | 347 | ctrl_reg); |
348 | if (rc) | ||
385 | dev_err(rtc_dd->rtc_dev, | 349 | dev_err(rtc_dd->rtc_dev, |
386 | "Write to RTC Alarm control register failed\n"); | 350 | "Write to RTC Alarm control register failed\n"); |
387 | 351 | ||
@@ -392,7 +356,7 @@ rtc_alarm_handled: | |||
392 | static int pm8xxx_rtc_probe(struct platform_device *pdev) | 356 | static int pm8xxx_rtc_probe(struct platform_device *pdev) |
393 | { | 357 | { |
394 | int rc; | 358 | int rc; |
395 | u8 ctrl_reg; | 359 | unsigned int ctrl_reg; |
396 | bool rtc_write_enable = false; | 360 | bool rtc_write_enable = false; |
397 | struct pm8xxx_rtc *rtc_dd; | 361 | struct pm8xxx_rtc *rtc_dd; |
398 | struct resource *rtc_resource; | 362 | struct resource *rtc_resource; |
@@ -409,6 +373,12 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) | |||
409 | /* Initialise spinlock to protect RTC control register */ | 373 | /* Initialise spinlock to protect RTC control register */ |
410 | spin_lock_init(&rtc_dd->ctrl_reg_lock); | 374 | spin_lock_init(&rtc_dd->ctrl_reg_lock); |
411 | 375 | ||
376 | rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL); | ||
377 | if (!rtc_dd->regmap) { | ||
378 | dev_err(&pdev->dev, "Parent regmap unavailable.\n"); | ||
379 | return -ENXIO; | ||
380 | } | ||
381 | |||
412 | rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); | 382 | rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); |
413 | if (rtc_dd->rtc_alarm_irq < 0) { | 383 | if (rtc_dd->rtc_alarm_irq < 0) { |
414 | dev_err(&pdev->dev, "Alarm IRQ resource absent!\n"); | 384 | dev_err(&pdev->dev, "Alarm IRQ resource absent!\n"); |
@@ -432,17 +402,16 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) | |||
432 | rtc_dd->rtc_dev = &pdev->dev; | 402 | rtc_dd->rtc_dev = &pdev->dev; |
433 | 403 | ||
434 | /* Check if the RTC is on, else turn it on */ | 404 | /* Check if the RTC is on, else turn it on */ |
435 | rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); | 405 | rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_base, &ctrl_reg); |
436 | if (rc < 0) { | 406 | if (rc) { |
437 | dev_err(&pdev->dev, "RTC control register read failed!\n"); | 407 | dev_err(&pdev->dev, "RTC control register read failed!\n"); |
438 | return rc; | 408 | return rc; |
439 | } | 409 | } |
440 | 410 | ||
441 | if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { | 411 | if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { |
442 | ctrl_reg |= PM8xxx_RTC_ENABLE; | 412 | ctrl_reg |= PM8xxx_RTC_ENABLE; |
443 | rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, | 413 | rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg); |
444 | 1); | 414 | if (rc) { |
445 | if (rc < 0) { | ||
446 | dev_err(&pdev->dev, | 415 | dev_err(&pdev->dev, |
447 | "Write to RTC control register failed\n"); | 416 | "Write to RTC control register failed\n"); |
448 | return rc; | 417 | return rc; |