diff options
Diffstat (limited to 'drivers/rtc/rtc-twl.c')
| -rw-r--r-- | drivers/rtc/rtc-twl.c | 610 | 
1 files changed, 610 insertions, 0 deletions
| diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c new file mode 100644 index 000000000000..ed1b86828124 --- /dev/null +++ b/drivers/rtc/rtc-twl.c | |||
| @@ -0,0 +1,610 @@ | |||
| 1 | /* | ||
| 2 | * rtc-twl.c -- TWL Real Time Clock interface | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 MontaVista Software, Inc | ||
| 5 | * Author: Alexandre Rusev <source@mvista.com> | ||
| 6 | * | ||
| 7 | * Based on original TI driver twl4030-rtc.c | ||
| 8 | * Copyright (C) 2006 Texas Instruments, Inc. | ||
| 9 | * | ||
| 10 | * Based on rtc-omap.c | ||
| 11 | * Copyright (C) 2003 MontaVista Software, Inc. | ||
| 12 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | ||
| 13 | * Copyright (C) 2006 David Brownell | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version | ||
| 18 | * 2 of the License, or (at your option) any later version. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/module.h> | ||
| 25 | #include <linux/types.h> | ||
| 26 | #include <linux/rtc.h> | ||
| 27 | #include <linux/bcd.h> | ||
| 28 | #include <linux/platform_device.h> | ||
| 29 | #include <linux/interrupt.h> | ||
| 30 | |||
| 31 | #include <linux/i2c/twl.h> | ||
| 32 | |||
| 33 | |||
| 34 | /* | ||
| 35 | * RTC block register offsets (use TWL_MODULE_RTC) | ||
| 36 | */ | ||
| 37 | enum { | ||
| 38 | REG_SECONDS_REG = 0, | ||
| 39 | REG_MINUTES_REG, | ||
| 40 | REG_HOURS_REG, | ||
| 41 | REG_DAYS_REG, | ||
| 42 | REG_MONTHS_REG, | ||
| 43 | REG_YEARS_REG, | ||
| 44 | REG_WEEKS_REG, | ||
| 45 | |||
| 46 | REG_ALARM_SECONDS_REG, | ||
| 47 | REG_ALARM_MINUTES_REG, | ||
| 48 | REG_ALARM_HOURS_REG, | ||
| 49 | REG_ALARM_DAYS_REG, | ||
| 50 | REG_ALARM_MONTHS_REG, | ||
| 51 | REG_ALARM_YEARS_REG, | ||
| 52 | |||
| 53 | REG_RTC_CTRL_REG, | ||
| 54 | REG_RTC_STATUS_REG, | ||
| 55 | REG_RTC_INTERRUPTS_REG, | ||
| 56 | |||
| 57 | REG_RTC_COMP_LSB_REG, | ||
| 58 | REG_RTC_COMP_MSB_REG, | ||
| 59 | }; | ||
| 60 | static const u8 twl4030_rtc_reg_map[] = { | ||
| 61 | [REG_SECONDS_REG] = 0x00, | ||
| 62 | [REG_MINUTES_REG] = 0x01, | ||
| 63 | [REG_HOURS_REG] = 0x02, | ||
| 64 | [REG_DAYS_REG] = 0x03, | ||
| 65 | [REG_MONTHS_REG] = 0x04, | ||
| 66 | [REG_YEARS_REG] = 0x05, | ||
| 67 | [REG_WEEKS_REG] = 0x06, | ||
| 68 | |||
| 69 | [REG_ALARM_SECONDS_REG] = 0x07, | ||
| 70 | [REG_ALARM_MINUTES_REG] = 0x08, | ||
| 71 | [REG_ALARM_HOURS_REG] = 0x09, | ||
| 72 | [REG_ALARM_DAYS_REG] = 0x0A, | ||
| 73 | [REG_ALARM_MONTHS_REG] = 0x0B, | ||
| 74 | [REG_ALARM_YEARS_REG] = 0x0C, | ||
| 75 | |||
| 76 | [REG_RTC_CTRL_REG] = 0x0D, | ||
| 77 | [REG_RTC_STATUS_REG] = 0x0E, | ||
| 78 | [REG_RTC_INTERRUPTS_REG] = 0x0F, | ||
| 79 | |||
| 80 | [REG_RTC_COMP_LSB_REG] = 0x10, | ||
| 81 | [REG_RTC_COMP_MSB_REG] = 0x11, | ||
| 82 | }; | ||
| 83 | static const u8 twl6030_rtc_reg_map[] = { | ||
| 84 | [REG_SECONDS_REG] = 0x00, | ||
| 85 | [REG_MINUTES_REG] = 0x01, | ||
| 86 | [REG_HOURS_REG] = 0x02, | ||
| 87 | [REG_DAYS_REG] = 0x03, | ||
| 88 | [REG_MONTHS_REG] = 0x04, | ||
| 89 | [REG_YEARS_REG] = 0x05, | ||
| 90 | [REG_WEEKS_REG] = 0x06, | ||
| 91 | |||
| 92 | [REG_ALARM_SECONDS_REG] = 0x08, | ||
| 93 | [REG_ALARM_MINUTES_REG] = 0x09, | ||
| 94 | [REG_ALARM_HOURS_REG] = 0x0A, | ||
| 95 | [REG_ALARM_DAYS_REG] = 0x0B, | ||
| 96 | [REG_ALARM_MONTHS_REG] = 0x0C, | ||
| 97 | [REG_ALARM_YEARS_REG] = 0x0D, | ||
| 98 | |||
| 99 | [REG_RTC_CTRL_REG] = 0x10, | ||
| 100 | [REG_RTC_STATUS_REG] = 0x11, | ||
| 101 | [REG_RTC_INTERRUPTS_REG] = 0x12, | ||
| 102 | |||
| 103 | [REG_RTC_COMP_LSB_REG] = 0x13, | ||
| 104 | [REG_RTC_COMP_MSB_REG] = 0x14, | ||
| 105 | }; | ||
| 106 | |||
| 107 | /* RTC_CTRL_REG bitfields */ | ||
| 108 | #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01 | ||
| 109 | #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02 | ||
| 110 | #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04 | ||
| 111 | #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08 | ||
| 112 | #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10 | ||
| 113 | #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20 | ||
| 114 | #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40 | ||
| 115 | |||
| 116 | /* RTC_STATUS_REG bitfields */ | ||
| 117 | #define BIT_RTC_STATUS_REG_RUN_M 0x02 | ||
| 118 | #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04 | ||
| 119 | #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08 | ||
| 120 | #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10 | ||
| 121 | #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20 | ||
| 122 | #define BIT_RTC_STATUS_REG_ALARM_M 0x40 | ||
| 123 | #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80 | ||
| 124 | |||
| 125 | /* RTC_INTERRUPTS_REG bitfields */ | ||
| 126 | #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03 | ||
| 127 | #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04 | ||
| 128 | #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08 | ||
| 129 | |||
| 130 | |||
| 131 | /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */ | ||
| 132 | #define ALL_TIME_REGS 6 | ||
| 133 | |||
| 134 | /*----------------------------------------------------------------------*/ | ||
| 135 | static u8 *rtc_reg_map; | ||
| 136 | |||
| 137 | /* | ||
| 138 | * Supports 1 byte read from TWL RTC register. | ||
| 139 | */ | ||
| 140 | static int twl_rtc_read_u8(u8 *data, u8 reg) | ||
| 141 | { | ||
| 142 | int ret; | ||
| 143 | |||
| 144 | ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg])); | ||
| 145 | if (ret < 0) | ||
| 146 | pr_err("twl_rtc: Could not read TWL" | ||
| 147 | "register %X - error %d\n", reg, ret); | ||
| 148 | return ret; | ||
| 149 | } | ||
| 150 | |||
| 151 | /* | ||
| 152 | * Supports 1 byte write to TWL RTC registers. | ||
| 153 | */ | ||
| 154 | static int twl_rtc_write_u8(u8 data, u8 reg) | ||
| 155 | { | ||
| 156 | int ret; | ||
| 157 | |||
| 158 | ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg])); | ||
| 159 | if (ret < 0) | ||
| 160 | pr_err("twl_rtc: Could not write TWL" | ||
| 161 | "register %X - error %d\n", reg, ret); | ||
| 162 | return ret; | ||
| 163 | } | ||
| 164 | |||
| 165 | /* | ||
| 166 | * Cache the value for timer/alarm interrupts register; this is | ||
| 167 | * only changed by callers holding rtc ops lock (or resume). | ||
| 168 | */ | ||
| 169 | static unsigned char rtc_irq_bits; | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Enable 1/second update and/or alarm interrupts. | ||
| 173 | */ | ||
| 174 | static int set_rtc_irq_bit(unsigned char bit) | ||
| 175 | { | ||
| 176 | unsigned char val; | ||
| 177 | int ret; | ||
| 178 | |||
| 179 | val = rtc_irq_bits | bit; | ||
| 180 | val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M; | ||
| 181 | ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG); | ||
| 182 | if (ret == 0) | ||
| 183 | rtc_irq_bits = val; | ||
| 184 | |||
| 185 | return ret; | ||
| 186 | } | ||
| 187 | |||
| 188 | /* | ||
| 189 | * Disable update and/or alarm interrupts. | ||
| 190 | */ | ||
| 191 | static int mask_rtc_irq_bit(unsigned char bit) | ||
| 192 | { | ||
| 193 | unsigned char val; | ||
| 194 | int ret; | ||
| 195 | |||
| 196 | val = rtc_irq_bits & ~bit; | ||
| 197 | ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG); | ||
| 198 | if (ret == 0) | ||
| 199 | rtc_irq_bits = val; | ||
| 200 | |||
| 201 | return ret; | ||
| 202 | } | ||
| 203 | |||
| 204 | static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled) | ||
| 205 | { | ||
| 206 | int ret; | ||
| 207 | |||
| 208 | if (enabled) | ||
| 209 | ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); | ||
| 210 | else | ||
| 211 | ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); | ||
| 212 | |||
| 213 | return ret; | ||
| 214 | } | ||
| 215 | |||
| 216 | static int twl_rtc_update_irq_enable(struct device *dev, unsigned enabled) | ||
| 217 | { | ||
| 218 | int ret; | ||
| 219 | |||
| 220 | if (enabled) | ||
| 221 | ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | ||
| 222 | else | ||
| 223 | ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | ||
| 224 | |||
| 225 | return ret; | ||
| 226 | } | ||
| 227 | |||
| 228 | /* | ||
| 229 | * Gets current TWL RTC time and date parameters. | ||
| 230 | * | ||
| 231 | * The RTC's time/alarm representation is not what gmtime(3) requires | ||
| 232 | * Linux to use: | ||
| 233 | * | ||
| 234 | * - Months are 1..12 vs Linux 0-11 | ||
| 235 | * - Years are 0..99 vs Linux 1900..N (we assume 21st century) | ||
| 236 | */ | ||
| 237 | static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm) | ||
| 238 | { | ||
| 239 | unsigned char rtc_data[ALL_TIME_REGS + 1]; | ||
| 240 | int ret; | ||
| 241 | u8 save_control; | ||
| 242 | |||
| 243 | ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG); | ||
| 244 | if (ret < 0) | ||
| 245 | return ret; | ||
| 246 | |||
| 247 | save_control |= BIT_RTC_CTRL_REG_GET_TIME_M; | ||
| 248 | |||
| 249 | ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); | ||
| 250 | if (ret < 0) | ||
| 251 | return ret; | ||
| 252 | |||
| 253 | ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data, | ||
| 254 | (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); | ||
| 255 | |||
| 256 | if (ret < 0) { | ||
| 257 | dev_err(dev, "rtc_read_time error %d\n", ret); | ||
| 258 | return ret; | ||
| 259 | } | ||
| 260 | |||
| 261 | tm->tm_sec = bcd2bin(rtc_data[0]); | ||
| 262 | tm->tm_min = bcd2bin(rtc_data[1]); | ||
| 263 | tm->tm_hour = bcd2bin(rtc_data[2]); | ||
| 264 | tm->tm_mday = bcd2bin(rtc_data[3]); | ||
| 265 | tm->tm_mon = bcd2bin(rtc_data[4]) - 1; | ||
| 266 | tm->tm_year = bcd2bin(rtc_data[5]) + 100; | ||
| 267 | |||
| 268 | return ret; | ||
| 269 | } | ||
| 270 | |||
| 271 | static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm) | ||
| 272 | { | ||
| 273 | unsigned char save_control; | ||
| 274 | unsigned char rtc_data[ALL_TIME_REGS + 1]; | ||
| 275 | int ret; | ||
| 276 | |||
| 277 | rtc_data[1] = bin2bcd(tm->tm_sec); | ||
| 278 | rtc_data[2] = bin2bcd(tm->tm_min); | ||
| 279 | rtc_data[3] = bin2bcd(tm->tm_hour); | ||
| 280 | rtc_data[4] = bin2bcd(tm->tm_mday); | ||
| 281 | rtc_data[5] = bin2bcd(tm->tm_mon + 1); | ||
| 282 | rtc_data[6] = bin2bcd(tm->tm_year - 100); | ||
| 283 | |||
| 284 | /* Stop RTC while updating the TC registers */ | ||
| 285 | ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG); | ||
| 286 | if (ret < 0) | ||
| 287 | goto out; | ||
| 288 | |||
| 289 | save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M; | ||
| 290 | twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); | ||
| 291 | if (ret < 0) | ||
| 292 | goto out; | ||
| 293 | |||
| 294 | /* update all the time registers in one shot */ | ||
| 295 | ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data, | ||
| 296 | (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); | ||
| 297 | if (ret < 0) { | ||
| 298 | dev_err(dev, "rtc_set_time error %d\n", ret); | ||
| 299 | goto out; | ||
| 300 | } | ||
| 301 | |||
| 302 | /* Start back RTC */ | ||
| 303 | save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M; | ||
| 304 | ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG); | ||
| 305 | |||
| 306 | out: | ||
| 307 | return ret; | ||
| 308 | } | ||
| 309 | |||
| 310 | /* | ||
| 311 | * Gets current TWL RTC alarm time. | ||
| 312 | */ | ||
| 313 | static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | ||
| 314 | { | ||
| 315 | unsigned char rtc_data[ALL_TIME_REGS + 1]; | ||
| 316 | int ret; | ||
| 317 | |||
| 318 | ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data, | ||
| 319 | (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS); | ||
| 320 | if (ret < 0) { | ||
| 321 | dev_err(dev, "rtc_read_alarm error %d\n", ret); | ||
| 322 | return ret; | ||
| 323 | } | ||
| 324 | |||
| 325 | /* some of these fields may be wildcard/"match all" */ | ||
| 326 | alm->time.tm_sec = bcd2bin(rtc_data[0]); | ||
| 327 | alm->time.tm_min = bcd2bin(rtc_data[1]); | ||
| 328 | alm->time.tm_hour = bcd2bin(rtc_data[2]); | ||
| 329 | alm->time.tm_mday = bcd2bin(rtc_data[3]); | ||
| 330 | alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1; | ||
| 331 | alm->time.tm_year = bcd2bin(rtc_data[5]) + 100; | ||
| 332 | |||
| 333 | /* report cached alarm enable state */ | ||
| 334 | if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M) | ||
| 335 | alm->enabled = 1; | ||
| 336 | |||
| 337 | return ret; | ||
| 338 | } | ||
| 339 | |||
| 340 | static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | ||
| 341 | { | ||
| 342 | unsigned char alarm_data[ALL_TIME_REGS + 1]; | ||
| 343 | int ret; | ||
| 344 | |||
| 345 | ret = twl_rtc_alarm_irq_enable(dev, 0); | ||
| 346 | if (ret) | ||
| 347 | goto out; | ||
| 348 | |||
| 349 | alarm_data[1] = bin2bcd(alm->time.tm_sec); | ||
| 350 | alarm_data[2] = bin2bcd(alm->time.tm_min); | ||
| 351 | alarm_data[3] = bin2bcd(alm->time.tm_hour); | ||
| 352 | alarm_data[4] = bin2bcd(alm->time.tm_mday); | ||
| 353 | alarm_data[5] = bin2bcd(alm->time.tm_mon + 1); | ||
| 354 | alarm_data[6] = bin2bcd(alm->time.tm_year - 100); | ||
| 355 | |||
| 356 | /* update all the alarm registers in one shot */ | ||
| 357 | ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data, | ||
| 358 | (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS); | ||
| 359 | if (ret) { | ||
| 360 | dev_err(dev, "rtc_set_alarm error %d\n", ret); | ||
| 361 | goto out; | ||
| 362 | } | ||
| 363 | |||
| 364 | if (alm->enabled) | ||
| 365 | ret = twl_rtc_alarm_irq_enable(dev, 1); | ||
| 366 | out: | ||
| 367 | return ret; | ||
| 368 | } | ||
| 369 | |||
| 370 | static irqreturn_t twl_rtc_interrupt(int irq, void *rtc) | ||
| 371 | { | ||
| 372 | unsigned long events = 0; | ||
| 373 | int ret = IRQ_NONE; | ||
| 374 | int res; | ||
| 375 | u8 rd_reg; | ||
| 376 | |||
| 377 | #ifdef CONFIG_LOCKDEP | ||
| 378 | /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which | ||
| 379 | * we don't want and can't tolerate. Although it might be | ||
| 380 | * friendlier not to borrow this thread context... | ||
| 381 | */ | ||
| 382 | local_irq_enable(); | ||
| 383 | #endif | ||
| 384 | |||
| 385 | res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG); | ||
| 386 | if (res) | ||
| 387 | goto out; | ||
| 388 | /* | ||
| 389 | * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG. | ||
| 390 | * only one (ALARM or RTC) interrupt source may be enabled | ||
| 391 | * at time, we also could check our results | ||
| 392 | * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM] | ||
| 393 | */ | ||
| 394 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) | ||
| 395 | events |= RTC_IRQF | RTC_AF; | ||
| 396 | else | ||
| 397 | events |= RTC_IRQF | RTC_UF; | ||
| 398 | |||
| 399 | res = twl_rtc_write_u8(rd_reg | BIT_RTC_STATUS_REG_ALARM_M, | ||
| 400 | REG_RTC_STATUS_REG); | ||
| 401 | if (res) | ||
| 402 | goto out; | ||
| 403 | |||
| 404 | if (twl_class_is_4030()) { | ||
| 405 | /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1 | ||
| 406 | * needs 2 reads to clear the interrupt. One read is done in | ||
| 407 | * do_twl_pwrirq(). Doing the second read, to clear | ||
| 408 | * the bit. | ||
| 409 | * | ||
| 410 | * FIXME the reason PWR_ISR1 needs an extra read is that | ||
| 411 | * RTC_IF retriggered until we cleared REG_ALARM_M above. | ||
| 412 | * But re-reading like this is a bad hack; by doing so we | ||
| 413 | * risk wrongly clearing status for some other IRQ (losing | ||
| 414 | * the interrupt). Be smarter about handling RTC_UF ... | ||
| 415 | */ | ||
| 416 | res = twl_i2c_read_u8(TWL4030_MODULE_INT, | ||
| 417 | &rd_reg, TWL4030_INT_PWR_ISR1); | ||
| 418 | if (res) | ||
| 419 | goto out; | ||
| 420 | } | ||
| 421 | |||
| 422 | /* Notify RTC core on event */ | ||
| 423 | rtc_update_irq(rtc, 1, events); | ||
| 424 | |||
| 425 | ret = IRQ_HANDLED; | ||
| 426 | out: | ||
| 427 | return ret; | ||
| 428 | } | ||
| 429 | |||
| 430 | static struct rtc_class_ops twl_rtc_ops = { | ||
| 431 | .read_time = twl_rtc_read_time, | ||
| 432 | .set_time = twl_rtc_set_time, | ||
| 433 | .read_alarm = twl_rtc_read_alarm, | ||
| 434 | .set_alarm = twl_rtc_set_alarm, | ||
| 435 | .alarm_irq_enable = twl_rtc_alarm_irq_enable, | ||
| 436 | .update_irq_enable = twl_rtc_update_irq_enable, | ||
| 437 | }; | ||
| 438 | |||
| 439 | /*----------------------------------------------------------------------*/ | ||
| 440 | |||
| 441 | static int __devinit twl_rtc_probe(struct platform_device *pdev) | ||
| 442 | { | ||
| 443 | struct rtc_device *rtc; | ||
| 444 | int ret = 0; | ||
| 445 | int irq = platform_get_irq(pdev, 0); | ||
| 446 | u8 rd_reg; | ||
| 447 | |||
| 448 | if (irq <= 0) | ||
| 449 | return -EINVAL; | ||
| 450 | |||
| 451 | rtc = rtc_device_register(pdev->name, | ||
| 452 | &pdev->dev, &twl_rtc_ops, THIS_MODULE); | ||
| 453 | if (IS_ERR(rtc)) { | ||
| 454 | ret = PTR_ERR(rtc); | ||
| 455 | dev_err(&pdev->dev, "can't register RTC device, err %ld\n", | ||
| 456 | PTR_ERR(rtc)); | ||
| 457 | goto out0; | ||
| 458 | |||
| 459 | } | ||
| 460 | |||
| 461 | platform_set_drvdata(pdev, rtc); | ||
| 462 | |||
| 463 | ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG); | ||
| 464 | if (ret < 0) | ||
| 465 | goto out1; | ||
| 466 | |||
| 467 | if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M) | ||
| 468 | dev_warn(&pdev->dev, "Power up reset detected.\n"); | ||
| 469 | |||
| 470 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) | ||
| 471 | dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n"); | ||
| 472 | |||
| 473 | /* Clear RTC Power up reset and pending alarm interrupts */ | ||
| 474 | ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG); | ||
| 475 | if (ret < 0) | ||
| 476 | goto out1; | ||
| 477 | |||
| 478 | ret = request_irq(irq, twl_rtc_interrupt, | ||
| 479 | IRQF_TRIGGER_RISING, | ||
| 480 | dev_name(&rtc->dev), rtc); | ||
| 481 | if (ret < 0) { | ||
| 482 | dev_err(&pdev->dev, "IRQ is not free.\n"); | ||
| 483 | goto out1; | ||
| 484 | } | ||
| 485 | |||
| 486 | if (twl_class_is_6030()) { | ||
| 487 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, | ||
| 488 | REG_INT_MSK_LINE_A); | ||
| 489 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, | ||
| 490 | REG_INT_MSK_STS_A); | ||
| 491 | } | ||
| 492 | |||
| 493 | /* Check RTC module status, Enable if it is off */ | ||
| 494 | ret = twl_rtc_read_u8(&rd_reg, REG_RTC_CTRL_REG); | ||
| 495 | if (ret < 0) | ||
| 496 | goto out2; | ||
| 497 | |||
| 498 | if (!(rd_reg & BIT_RTC_CTRL_REG_STOP_RTC_M)) { | ||
| 499 | dev_info(&pdev->dev, "Enabling TWL-RTC.\n"); | ||
| 500 | rd_reg = BIT_RTC_CTRL_REG_STOP_RTC_M; | ||
| 501 | ret = twl_rtc_write_u8(rd_reg, REG_RTC_CTRL_REG); | ||
| 502 | if (ret < 0) | ||
| 503 | goto out2; | ||
| 504 | } | ||
| 505 | |||
| 506 | /* init cached IRQ enable bits */ | ||
| 507 | ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG); | ||
| 508 | if (ret < 0) | ||
| 509 | goto out2; | ||
| 510 | |||
| 511 | return ret; | ||
| 512 | |||
| 513 | out2: | ||
| 514 | free_irq(irq, rtc); | ||
| 515 | out1: | ||
| 516 | rtc_device_unregister(rtc); | ||
| 517 | out0: | ||
| 518 | return ret; | ||
| 519 | } | ||
| 520 | |||
| 521 | /* | ||
| 522 | * Disable all TWL RTC module interrupts. | ||
| 523 | * Sets status flag to free. | ||
| 524 | */ | ||
| 525 | static int __devexit twl_rtc_remove(struct platform_device *pdev) | ||
| 526 | { | ||
| 527 | /* leave rtc running, but disable irqs */ | ||
| 528 | struct rtc_device *rtc = platform_get_drvdata(pdev); | ||
| 529 | int irq = platform_get_irq(pdev, 0); | ||
| 530 | |||
| 531 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); | ||
| 532 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | ||
| 533 | if (twl_class_is_6030()) { | ||
| 534 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, | ||
| 535 | REG_INT_MSK_LINE_A); | ||
| 536 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, | ||
| 537 | REG_INT_MSK_STS_A); | ||
| 538 | } | ||
| 539 | |||
| 540 | |||
| 541 | free_irq(irq, rtc); | ||
| 542 | |||
| 543 | rtc_device_unregister(rtc); | ||
| 544 | platform_set_drvdata(pdev, NULL); | ||
| 545 | return 0; | ||
| 546 | } | ||
| 547 | |||
| 548 | static void twl_rtc_shutdown(struct platform_device *pdev) | ||
| 549 | { | ||
| 550 | /* mask timer interrupts, but leave alarm interrupts on to enable | ||
| 551 | power-on when alarm is triggered */ | ||
| 552 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | ||
| 553 | } | ||
| 554 | |||
| 555 | #ifdef CONFIG_PM | ||
| 556 | |||
| 557 | static unsigned char irqstat; | ||
| 558 | |||
| 559 | static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state) | ||
| 560 | { | ||
| 561 | irqstat = rtc_irq_bits; | ||
| 562 | |||
| 563 | mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | ||
| 564 | return 0; | ||
| 565 | } | ||
| 566 | |||
| 567 | static int twl_rtc_resume(struct platform_device *pdev) | ||
| 568 | { | ||
| 569 | set_rtc_irq_bit(irqstat); | ||
| 570 | return 0; | ||
| 571 | } | ||
| 572 | |||
| 573 | #else | ||
| 574 | #define twl_rtc_suspend NULL | ||
| 575 | #define twl_rtc_resume NULL | ||
| 576 | #endif | ||
| 577 | |||
| 578 | MODULE_ALIAS("platform:twl_rtc"); | ||
| 579 | |||
| 580 | static struct platform_driver twl4030rtc_driver = { | ||
| 581 | .probe = twl_rtc_probe, | ||
| 582 | .remove = __devexit_p(twl_rtc_remove), | ||
| 583 | .shutdown = twl_rtc_shutdown, | ||
| 584 | .suspend = twl_rtc_suspend, | ||
| 585 | .resume = twl_rtc_resume, | ||
| 586 | .driver = { | ||
| 587 | .owner = THIS_MODULE, | ||
| 588 | .name = "twl_rtc", | ||
| 589 | }, | ||
| 590 | }; | ||
| 591 | |||
| 592 | static int __init twl_rtc_init(void) | ||
| 593 | { | ||
| 594 | if (twl_class_is_4030()) | ||
| 595 | rtc_reg_map = (u8 *) twl4030_rtc_reg_map; | ||
| 596 | else | ||
| 597 | rtc_reg_map = (u8 *) twl6030_rtc_reg_map; | ||
| 598 | |||
| 599 | return platform_driver_register(&twl4030rtc_driver); | ||
| 600 | } | ||
| 601 | module_init(twl_rtc_init); | ||
| 602 | |||
| 603 | static void __exit twl_rtc_exit(void) | ||
| 604 | { | ||
| 605 | platform_driver_unregister(&twl4030rtc_driver); | ||
| 606 | } | ||
| 607 | module_exit(twl_rtc_exit); | ||
| 608 | |||
| 609 | MODULE_AUTHOR("Texas Instruments, MontaVista Software"); | ||
| 610 | MODULE_LICENSE("GPL"); | ||
