diff options
Diffstat (limited to 'drivers/rtc/rtc-omap.c')
-rw-r--r-- | drivers/rtc/rtc-omap.c | 547 |
1 files changed, 349 insertions, 198 deletions
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c index 21142e6574a9..4f1c6ca97211 100644 --- a/drivers/rtc/rtc-omap.c +++ b/drivers/rtc/rtc-omap.c | |||
@@ -1,10 +1,11 @@ | |||
1 | /* | 1 | /* |
2 | * TI OMAP1 Real Time Clock interface for Linux | 2 | * TI OMAP Real Time Clock interface for Linux |
3 | * | 3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | 4 | * Copyright (C) 2003 MontaVista Software, Inc. |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | 5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> |
6 | * | 6 | * |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | 7 | * Copyright (C) 2006 David Brownell (new RTC framework) |
8 | * Copyright (C) 2014 Johan Hovold <johan@kernel.org> | ||
8 | * | 9 | * |
9 | * This program is free software; you can redistribute it and/or | 10 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License | 11 | * modify it under the terms of the GNU General Public License |
@@ -25,7 +26,8 @@ | |||
25 | #include <linux/pm_runtime.h> | 26 | #include <linux/pm_runtime.h> |
26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
27 | 28 | ||
28 | /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock | 29 | /* |
30 | * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock | ||
29 | * with century-range alarm matching, driven by the 32kHz clock. | 31 | * with century-range alarm matching, driven by the 32kHz clock. |
30 | * | 32 | * |
31 | * The main user-visible ways it differs from PC RTCs are by omitting | 33 | * The main user-visible ways it differs from PC RTCs are by omitting |
@@ -39,10 +41,6 @@ | |||
39 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | 41 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. |
40 | */ | 42 | */ |
41 | 43 | ||
42 | #define DRIVER_NAME "omap_rtc" | ||
43 | |||
44 | #define OMAP_RTC_BASE 0xfffb4800 | ||
45 | |||
46 | /* RTC registers */ | 44 | /* RTC registers */ |
47 | #define OMAP_RTC_SECONDS_REG 0x00 | 45 | #define OMAP_RTC_SECONDS_REG 0x00 |
48 | #define OMAP_RTC_MINUTES_REG 0x04 | 46 | #define OMAP_RTC_MINUTES_REG 0x04 |
@@ -72,6 +70,15 @@ | |||
72 | 70 | ||
73 | #define OMAP_RTC_IRQWAKEEN 0x7c | 71 | #define OMAP_RTC_IRQWAKEEN 0x7c |
74 | 72 | ||
73 | #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 | ||
74 | #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 | ||
75 | #define OMAP_RTC_ALARM2_HOURS_REG 0x88 | ||
76 | #define OMAP_RTC_ALARM2_DAYS_REG 0x8c | ||
77 | #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 | ||
78 | #define OMAP_RTC_ALARM2_YEARS_REG 0x94 | ||
79 | |||
80 | #define OMAP_RTC_PMIC_REG 0x98 | ||
81 | |||
75 | /* OMAP_RTC_CTRL_REG bit fields: */ | 82 | /* OMAP_RTC_CTRL_REG bit fields: */ |
76 | #define OMAP_RTC_CTRL_SPLIT BIT(7) | 83 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
77 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | 84 | #define OMAP_RTC_CTRL_DISABLE BIT(6) |
@@ -84,6 +91,7 @@ | |||
84 | 91 | ||
85 | /* OMAP_RTC_STATUS_REG bit fields: */ | 92 | /* OMAP_RTC_STATUS_REG bit fields: */ |
86 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) | 93 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
94 | #define OMAP_RTC_STATUS_ALARM2 BIT(7) | ||
87 | #define OMAP_RTC_STATUS_ALARM BIT(6) | 95 | #define OMAP_RTC_STATUS_ALARM BIT(6) |
88 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | 96 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) |
89 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | 97 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) |
@@ -93,6 +101,7 @@ | |||
93 | #define OMAP_RTC_STATUS_BUSY BIT(0) | 101 | #define OMAP_RTC_STATUS_BUSY BIT(0) |
94 | 102 | ||
95 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | 103 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ |
104 | #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) | ||
96 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) | 105 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
97 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | 106 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) |
98 | 107 | ||
@@ -102,61 +111,82 @@ | |||
102 | /* OMAP_RTC_IRQWAKEEN bit fields: */ | 111 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
103 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) | 112 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
104 | 113 | ||
114 | /* OMAP_RTC_PMIC bit fields: */ | ||
115 | #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) | ||
116 | |||
105 | /* OMAP_RTC_KICKER values */ | 117 | /* OMAP_RTC_KICKER values */ |
106 | #define KICK0_VALUE 0x83e70b13 | 118 | #define KICK0_VALUE 0x83e70b13 |
107 | #define KICK1_VALUE 0x95a4f1e0 | 119 | #define KICK1_VALUE 0x95a4f1e0 |
108 | 120 | ||
109 | #define OMAP_RTC_HAS_KICKER BIT(0) | 121 | struct omap_rtc_device_type { |
110 | 122 | bool has_32kclk_en; | |
111 | /* | 123 | bool has_kicker; |
112 | * Few RTC IP revisions has special WAKE-EN Register to enable Wakeup | 124 | bool has_irqwakeen; |
113 | * generation for event Alarm. | 125 | bool has_pmic_mode; |
114 | */ | 126 | bool has_power_up_reset; |
115 | #define OMAP_RTC_HAS_IRQWAKEEN BIT(1) | 127 | }; |
116 | 128 | ||
117 | /* | 129 | struct omap_rtc { |
118 | * Some RTC IP revisions (like those in AM335x and DRA7x) need | 130 | struct rtc_device *rtc; |
119 | * the 32KHz clock to be explicitly enabled. | 131 | void __iomem *base; |
120 | */ | 132 | int irq_alarm; |
121 | #define OMAP_RTC_HAS_32KCLK_EN BIT(2) | 133 | int irq_timer; |
134 | u8 interrupts_reg; | ||
135 | bool is_pmic_controller; | ||
136 | const struct omap_rtc_device_type *type; | ||
137 | }; | ||
122 | 138 | ||
123 | static void __iomem *rtc_base; | 139 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
140 | { | ||
141 | return readb(rtc->base + reg); | ||
142 | } | ||
124 | 143 | ||
125 | #define rtc_read(addr) readb(rtc_base + (addr)) | 144 | static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) |
126 | #define rtc_write(val, addr) writeb(val, rtc_base + (addr)) | 145 | { |
146 | return readl(rtc->base + reg); | ||
147 | } | ||
127 | 148 | ||
128 | #define rtc_writel(val, addr) writel(val, rtc_base + (addr)) | 149 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
150 | { | ||
151 | writeb(val, rtc->base + reg); | ||
152 | } | ||
129 | 153 | ||
154 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) | ||
155 | { | ||
156 | writel(val, rtc->base + reg); | ||
157 | } | ||
130 | 158 | ||
131 | /* we rely on the rtc framework to handle locking (rtc->ops_lock), | 159 | /* |
160 | * We rely on the rtc framework to handle locking (rtc->ops_lock), | ||
132 | * so the only other requirement is that register accesses which | 161 | * so the only other requirement is that register accesses which |
133 | * require BUSY to be clear are made with IRQs locally disabled | 162 | * require BUSY to be clear are made with IRQs locally disabled |
134 | */ | 163 | */ |
135 | static void rtc_wait_not_busy(void) | 164 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
136 | { | 165 | { |
137 | int count = 0; | 166 | int count; |
138 | u8 status; | 167 | u8 status; |
139 | 168 | ||
140 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | 169 | /* BUSY may stay active for 1/32768 second (~30 usec) */ |
141 | for (count = 0; count < 50; count++) { | 170 | for (count = 0; count < 50; count++) { |
142 | status = rtc_read(OMAP_RTC_STATUS_REG); | 171 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
143 | if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0) | 172 | if (!(status & OMAP_RTC_STATUS_BUSY)) |
144 | break; | 173 | break; |
145 | udelay(1); | 174 | udelay(1); |
146 | } | 175 | } |
147 | /* now we have ~15 usec to read/write various registers */ | 176 | /* now we have ~15 usec to read/write various registers */ |
148 | } | 177 | } |
149 | 178 | ||
150 | static irqreturn_t rtc_irq(int irq, void *rtc) | 179 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
151 | { | 180 | { |
152 | unsigned long events = 0; | 181 | struct omap_rtc *rtc = dev_id; |
153 | u8 irq_data; | 182 | unsigned long events = 0; |
183 | u8 irq_data; | ||
154 | 184 | ||
155 | irq_data = rtc_read(OMAP_RTC_STATUS_REG); | 185 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
156 | 186 | ||
157 | /* alarm irq? */ | 187 | /* alarm irq? */ |
158 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | 188 | if (irq_data & OMAP_RTC_STATUS_ALARM) { |
159 | rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG); | 189 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
160 | events |= RTC_IRQF | RTC_AF; | 190 | events |= RTC_IRQF | RTC_AF; |
161 | } | 191 | } |
162 | 192 | ||
@@ -164,23 +194,21 @@ static irqreturn_t rtc_irq(int irq, void *rtc) | |||
164 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | 194 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) |
165 | events |= RTC_IRQF | RTC_UF; | 195 | events |= RTC_IRQF | RTC_UF; |
166 | 196 | ||
167 | rtc_update_irq(rtc, 1, events); | 197 | rtc_update_irq(rtc->rtc, 1, events); |
168 | 198 | ||
169 | return IRQ_HANDLED; | 199 | return IRQ_HANDLED; |
170 | } | 200 | } |
171 | 201 | ||
172 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | 202 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
173 | { | 203 | { |
204 | struct omap_rtc *rtc = dev_get_drvdata(dev); | ||
174 | u8 reg, irqwake_reg = 0; | 205 | u8 reg, irqwake_reg = 0; |
175 | struct platform_device *pdev = to_platform_device(dev); | ||
176 | const struct platform_device_id *id_entry = | ||
177 | platform_get_device_id(pdev); | ||
178 | 206 | ||
179 | local_irq_disable(); | 207 | local_irq_disable(); |
180 | rtc_wait_not_busy(); | 208 | rtc_wait_not_busy(rtc); |
181 | reg = rtc_read(OMAP_RTC_INTERRUPTS_REG); | 209 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
182 | if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) | 210 | if (rtc->type->has_irqwakeen) |
183 | irqwake_reg = rtc_read(OMAP_RTC_IRQWAKEEN); | 211 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
184 | 212 | ||
185 | if (enabled) { | 213 | if (enabled) { |
186 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; | 214 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
@@ -189,10 +217,10 @@ static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |||
189 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; | 217 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
190 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; | 218 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
191 | } | 219 | } |
192 | rtc_wait_not_busy(); | 220 | rtc_wait_not_busy(rtc); |
193 | rtc_write(reg, OMAP_RTC_INTERRUPTS_REG); | 221 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
194 | if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) | 222 | if (rtc->type->has_irqwakeen) |
195 | rtc_write(irqwake_reg, OMAP_RTC_IRQWAKEEN); | 223 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
196 | local_irq_enable(); | 224 | local_irq_enable(); |
197 | 225 | ||
198 | return 0; | 226 | return 0; |
@@ -230,39 +258,47 @@ static void bcd2tm(struct rtc_time *tm) | |||
230 | tm->tm_year = bcd2bin(tm->tm_year) + 100; | 258 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
231 | } | 259 | } |
232 | 260 | ||
261 | static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) | ||
262 | { | ||
263 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); | ||
264 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | ||
265 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | ||
266 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | ||
267 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | ||
268 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | ||
269 | } | ||
233 | 270 | ||
234 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | 271 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) |
235 | { | 272 | { |
273 | struct omap_rtc *rtc = dev_get_drvdata(dev); | ||
274 | |||
236 | /* we don't report wday/yday/isdst ... */ | 275 | /* we don't report wday/yday/isdst ... */ |
237 | local_irq_disable(); | 276 | local_irq_disable(); |
238 | rtc_wait_not_busy(); | 277 | rtc_wait_not_busy(rtc); |
239 | 278 | omap_rtc_read_time_raw(rtc, tm); | |
240 | tm->tm_sec = rtc_read(OMAP_RTC_SECONDS_REG); | ||
241 | tm->tm_min = rtc_read(OMAP_RTC_MINUTES_REG); | ||
242 | tm->tm_hour = rtc_read(OMAP_RTC_HOURS_REG); | ||
243 | tm->tm_mday = rtc_read(OMAP_RTC_DAYS_REG); | ||
244 | tm->tm_mon = rtc_read(OMAP_RTC_MONTHS_REG); | ||
245 | tm->tm_year = rtc_read(OMAP_RTC_YEARS_REG); | ||
246 | |||
247 | local_irq_enable(); | 279 | local_irq_enable(); |
248 | 280 | ||
249 | bcd2tm(tm); | 281 | bcd2tm(tm); |
282 | |||
250 | return 0; | 283 | return 0; |
251 | } | 284 | } |
252 | 285 | ||
253 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | 286 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) |
254 | { | 287 | { |
288 | struct omap_rtc *rtc = dev_get_drvdata(dev); | ||
289 | |||
255 | if (tm2bcd(tm) < 0) | 290 | if (tm2bcd(tm) < 0) |
256 | return -EINVAL; | 291 | return -EINVAL; |
292 | |||
257 | local_irq_disable(); | 293 | local_irq_disable(); |
258 | rtc_wait_not_busy(); | 294 | rtc_wait_not_busy(rtc); |
259 | 295 | ||
260 | rtc_write(tm->tm_year, OMAP_RTC_YEARS_REG); | 296 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
261 | rtc_write(tm->tm_mon, OMAP_RTC_MONTHS_REG); | 297 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); |
262 | rtc_write(tm->tm_mday, OMAP_RTC_DAYS_REG); | 298 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); |
263 | rtc_write(tm->tm_hour, OMAP_RTC_HOURS_REG); | 299 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); |
264 | rtc_write(tm->tm_min, OMAP_RTC_MINUTES_REG); | 300 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); |
265 | rtc_write(tm->tm_sec, OMAP_RTC_SECONDS_REG); | 301 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); |
266 | 302 | ||
267 | local_irq_enable(); | 303 | local_irq_enable(); |
268 | 304 | ||
@@ -271,48 +307,50 @@ static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |||
271 | 307 | ||
272 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | 308 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) |
273 | { | 309 | { |
310 | struct omap_rtc *rtc = dev_get_drvdata(dev); | ||
311 | u8 interrupts; | ||
312 | |||
274 | local_irq_disable(); | 313 | local_irq_disable(); |
275 | rtc_wait_not_busy(); | 314 | rtc_wait_not_busy(rtc); |
276 | 315 | ||
277 | alm->time.tm_sec = rtc_read(OMAP_RTC_ALARM_SECONDS_REG); | 316 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
278 | alm->time.tm_min = rtc_read(OMAP_RTC_ALARM_MINUTES_REG); | 317 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); |
279 | alm->time.tm_hour = rtc_read(OMAP_RTC_ALARM_HOURS_REG); | 318 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); |
280 | alm->time.tm_mday = rtc_read(OMAP_RTC_ALARM_DAYS_REG); | 319 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); |
281 | alm->time.tm_mon = rtc_read(OMAP_RTC_ALARM_MONTHS_REG); | 320 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); |
282 | alm->time.tm_year = rtc_read(OMAP_RTC_ALARM_YEARS_REG); | 321 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); |
283 | 322 | ||
284 | local_irq_enable(); | 323 | local_irq_enable(); |
285 | 324 | ||
286 | bcd2tm(&alm->time); | 325 | bcd2tm(&alm->time); |
287 | alm->enabled = !!(rtc_read(OMAP_RTC_INTERRUPTS_REG) | 326 | |
288 | & OMAP_RTC_INTERRUPTS_IT_ALARM); | 327 | interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
328 | alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); | ||
289 | 329 | ||
290 | return 0; | 330 | return 0; |
291 | } | 331 | } |
292 | 332 | ||
293 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | 333 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
294 | { | 334 | { |
335 | struct omap_rtc *rtc = dev_get_drvdata(dev); | ||
295 | u8 reg, irqwake_reg = 0; | 336 | u8 reg, irqwake_reg = 0; |
296 | struct platform_device *pdev = to_platform_device(dev); | ||
297 | const struct platform_device_id *id_entry = | ||
298 | platform_get_device_id(pdev); | ||
299 | 337 | ||
300 | if (tm2bcd(&alm->time) < 0) | 338 | if (tm2bcd(&alm->time) < 0) |
301 | return -EINVAL; | 339 | return -EINVAL; |
302 | 340 | ||
303 | local_irq_disable(); | 341 | local_irq_disable(); |
304 | rtc_wait_not_busy(); | 342 | rtc_wait_not_busy(rtc); |
305 | 343 | ||
306 | rtc_write(alm->time.tm_year, OMAP_RTC_ALARM_YEARS_REG); | 344 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
307 | rtc_write(alm->time.tm_mon, OMAP_RTC_ALARM_MONTHS_REG); | 345 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); |
308 | rtc_write(alm->time.tm_mday, OMAP_RTC_ALARM_DAYS_REG); | 346 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); |
309 | rtc_write(alm->time.tm_hour, OMAP_RTC_ALARM_HOURS_REG); | 347 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); |
310 | rtc_write(alm->time.tm_min, OMAP_RTC_ALARM_MINUTES_REG); | 348 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); |
311 | rtc_write(alm->time.tm_sec, OMAP_RTC_ALARM_SECONDS_REG); | 349 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); |
312 | 350 | ||
313 | reg = rtc_read(OMAP_RTC_INTERRUPTS_REG); | 351 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
314 | if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) | 352 | if (rtc->type->has_irqwakeen) |
315 | irqwake_reg = rtc_read(OMAP_RTC_IRQWAKEEN); | 353 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
316 | 354 | ||
317 | if (alm->enabled) { | 355 | if (alm->enabled) { |
318 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; | 356 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
@@ -321,15 +359,79 @@ static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |||
321 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; | 359 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
322 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; | 360 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
323 | } | 361 | } |
324 | rtc_write(reg, OMAP_RTC_INTERRUPTS_REG); | 362 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
325 | if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) | 363 | if (rtc->type->has_irqwakeen) |
326 | rtc_write(irqwake_reg, OMAP_RTC_IRQWAKEEN); | 364 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
327 | 365 | ||
328 | local_irq_enable(); | 366 | local_irq_enable(); |
329 | 367 | ||
330 | return 0; | 368 | return 0; |
331 | } | 369 | } |
332 | 370 | ||
371 | static struct omap_rtc *omap_rtc_power_off_rtc; | ||
372 | |||
373 | /* | ||
374 | * omap_rtc_poweroff: RTC-controlled power off | ||
375 | * | ||
376 | * The RTC can be used to control an external PMIC via the pmic_power_en pin, | ||
377 | * which can be configured to transition to OFF on ALARM2 events. | ||
378 | * | ||
379 | * Notes: | ||
380 | * The two-second alarm offset is the shortest offset possible as the alarm | ||
381 | * registers must be set before the next timer update and the offset | ||
382 | * calculation is too heavy for everything to be done within a single access | ||
383 | * period (~15 us). | ||
384 | * | ||
385 | * Called with local interrupts disabled. | ||
386 | */ | ||
387 | static void omap_rtc_power_off(void) | ||
388 | { | ||
389 | struct omap_rtc *rtc = omap_rtc_power_off_rtc; | ||
390 | struct rtc_time tm; | ||
391 | unsigned long now; | ||
392 | u32 val; | ||
393 | |||
394 | /* enable pmic_power_en control */ | ||
395 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | ||
396 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); | ||
397 | |||
398 | /* set alarm two seconds from now */ | ||
399 | omap_rtc_read_time_raw(rtc, &tm); | ||
400 | bcd2tm(&tm); | ||
401 | rtc_tm_to_time(&tm, &now); | ||
402 | rtc_time_to_tm(now + 2, &tm); | ||
403 | |||
404 | if (tm2bcd(&tm) < 0) { | ||
405 | dev_err(&rtc->rtc->dev, "power off failed\n"); | ||
406 | return; | ||
407 | } | ||
408 | |||
409 | rtc_wait_not_busy(rtc); | ||
410 | |||
411 | rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); | ||
412 | rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); | ||
413 | rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); | ||
414 | rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); | ||
415 | rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); | ||
416 | rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); | ||
417 | |||
418 | /* | ||
419 | * enable ALARM2 interrupt | ||
420 | * | ||
421 | * NOTE: this fails on AM3352 if rtc_write (writeb) is used | ||
422 | */ | ||
423 | val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | ||
424 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, | ||
425 | val | OMAP_RTC_INTERRUPTS_IT_ALARM2); | ||
426 | |||
427 | /* | ||
428 | * Wait for alarm to trigger (within two seconds) and external PMIC to | ||
429 | * power off the system. Add a 500 ms margin for external latencies | ||
430 | * (e.g. debounce circuits). | ||
431 | */ | ||
432 | mdelay(2500); | ||
433 | } | ||
434 | |||
333 | static struct rtc_class_ops omap_rtc_ops = { | 435 | static struct rtc_class_ops omap_rtc_ops = { |
334 | .read_time = omap_rtc_read_time, | 436 | .read_time = omap_rtc_read_time, |
335 | .set_time = omap_rtc_set_time, | 437 | .set_time = omap_rtc_set_time, |
@@ -338,137 +440,140 @@ static struct rtc_class_ops omap_rtc_ops = { | |||
338 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, | 440 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
339 | }; | 441 | }; |
340 | 442 | ||
341 | static int omap_rtc_alarm; | 443 | static const struct omap_rtc_device_type omap_rtc_default_type = { |
342 | static int omap_rtc_timer; | 444 | .has_power_up_reset = true, |
445 | }; | ||
343 | 446 | ||
344 | #define OMAP_RTC_DATA_AM3352_IDX 1 | 447 | static const struct omap_rtc_device_type omap_rtc_am3352_type = { |
345 | #define OMAP_RTC_DATA_DA830_IDX 2 | 448 | .has_32kclk_en = true, |
449 | .has_kicker = true, | ||
450 | .has_irqwakeen = true, | ||
451 | .has_pmic_mode = true, | ||
452 | }; | ||
346 | 453 | ||
347 | static struct platform_device_id omap_rtc_devtype[] = { | 454 | static const struct omap_rtc_device_type omap_rtc_da830_type = { |
455 | .has_kicker = true, | ||
456 | }; | ||
457 | |||
458 | static const struct platform_device_id omap_rtc_id_table[] = { | ||
348 | { | 459 | { |
349 | .name = DRIVER_NAME, | 460 | .name = "omap_rtc", |
350 | }, | 461 | .driver_data = (kernel_ulong_t)&omap_rtc_default_type, |
351 | [OMAP_RTC_DATA_AM3352_IDX] = { | 462 | }, { |
352 | .name = "am3352-rtc", | 463 | .name = "am3352-rtc", |
353 | .driver_data = OMAP_RTC_HAS_KICKER | OMAP_RTC_HAS_IRQWAKEEN | | 464 | .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, |
354 | OMAP_RTC_HAS_32KCLK_EN, | 465 | }, { |
355 | }, | ||
356 | [OMAP_RTC_DATA_DA830_IDX] = { | ||
357 | .name = "da830-rtc", | 466 | .name = "da830-rtc", |
358 | .driver_data = OMAP_RTC_HAS_KICKER, | 467 | .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, |
359 | }, | 468 | }, { |
360 | {}, | 469 | /* sentinel */ |
470 | } | ||
361 | }; | 471 | }; |
362 | MODULE_DEVICE_TABLE(platform, omap_rtc_devtype); | 472 | MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); |
363 | 473 | ||
364 | static const struct of_device_id omap_rtc_of_match[] = { | 474 | static const struct of_device_id omap_rtc_of_match[] = { |
365 | { .compatible = "ti,da830-rtc", | 475 | { |
366 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX], | 476 | .compatible = "ti,am3352-rtc", |
367 | }, | 477 | .data = &omap_rtc_am3352_type, |
368 | { .compatible = "ti,am3352-rtc", | 478 | }, { |
369 | .data = &omap_rtc_devtype[OMAP_RTC_DATA_AM3352_IDX], | 479 | .compatible = "ti,da830-rtc", |
370 | }, | 480 | .data = &omap_rtc_da830_type, |
371 | {}, | 481 | }, { |
482 | /* sentinel */ | ||
483 | } | ||
372 | }; | 484 | }; |
373 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | 485 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); |
374 | 486 | ||
375 | static int __init omap_rtc_probe(struct platform_device *pdev) | 487 | static int __init omap_rtc_probe(struct platform_device *pdev) |
376 | { | 488 | { |
377 | struct resource *res; | 489 | struct omap_rtc *rtc; |
378 | struct rtc_device *rtc; | 490 | struct resource *res; |
379 | u8 reg, new_ctrl; | 491 | u8 reg, mask, new_ctrl; |
380 | const struct platform_device_id *id_entry; | 492 | const struct platform_device_id *id_entry; |
381 | const struct of_device_id *of_id; | 493 | const struct of_device_id *of_id; |
494 | int ret; | ||
382 | 495 | ||
383 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); | 496 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
384 | if (of_id) | 497 | if (!rtc) |
385 | pdev->id_entry = of_id->data; | 498 | return -ENOMEM; |
386 | 499 | ||
387 | id_entry = platform_get_device_id(pdev); | 500 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
388 | if (!id_entry) { | 501 | if (of_id) { |
389 | dev_err(&pdev->dev, "no matching device entry\n"); | 502 | rtc->type = of_id->data; |
390 | return -ENODEV; | 503 | rtc->is_pmic_controller = rtc->type->has_pmic_mode && |
504 | of_property_read_bool(pdev->dev.of_node, | ||
505 | "system-power-controller"); | ||
506 | } else { | ||
507 | id_entry = platform_get_device_id(pdev); | ||
508 | rtc->type = (void *)id_entry->driver_data; | ||
391 | } | 509 | } |
392 | 510 | ||
393 | omap_rtc_timer = platform_get_irq(pdev, 0); | 511 | rtc->irq_timer = platform_get_irq(pdev, 0); |
394 | if (omap_rtc_timer <= 0) { | 512 | if (rtc->irq_timer <= 0) |
395 | pr_debug("%s: no update irq?\n", pdev->name); | ||
396 | return -ENOENT; | 513 | return -ENOENT; |
397 | } | ||
398 | 514 | ||
399 | omap_rtc_alarm = platform_get_irq(pdev, 1); | 515 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
400 | if (omap_rtc_alarm <= 0) { | 516 | if (rtc->irq_alarm <= 0) |
401 | pr_debug("%s: no alarm irq?\n", pdev->name); | ||
402 | return -ENOENT; | 517 | return -ENOENT; |
403 | } | ||
404 | 518 | ||
405 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 519 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
406 | rtc_base = devm_ioremap_resource(&pdev->dev, res); | 520 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
407 | if (IS_ERR(rtc_base)) | 521 | if (IS_ERR(rtc->base)) |
408 | return PTR_ERR(rtc_base); | 522 | return PTR_ERR(rtc->base); |
523 | |||
524 | platform_set_drvdata(pdev, rtc); | ||
409 | 525 | ||
410 | /* Enable the clock/module so that we can access the registers */ | 526 | /* Enable the clock/module so that we can access the registers */ |
411 | pm_runtime_enable(&pdev->dev); | 527 | pm_runtime_enable(&pdev->dev); |
412 | pm_runtime_get_sync(&pdev->dev); | 528 | pm_runtime_get_sync(&pdev->dev); |
413 | 529 | ||
414 | if (id_entry->driver_data & OMAP_RTC_HAS_KICKER) { | 530 | if (rtc->type->has_kicker) { |
415 | rtc_writel(KICK0_VALUE, OMAP_RTC_KICK0_REG); | 531 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); |
416 | rtc_writel(KICK1_VALUE, OMAP_RTC_KICK1_REG); | 532 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); |
417 | } | ||
418 | |||
419 | rtc = devm_rtc_device_register(&pdev->dev, pdev->name, | ||
420 | &omap_rtc_ops, THIS_MODULE); | ||
421 | if (IS_ERR(rtc)) { | ||
422 | pr_debug("%s: can't register RTC device, err %ld\n", | ||
423 | pdev->name, PTR_ERR(rtc)); | ||
424 | goto fail0; | ||
425 | } | 533 | } |
426 | platform_set_drvdata(pdev, rtc); | ||
427 | 534 | ||
428 | /* clear pending irqs, and set 1/second periodic, | 535 | /* |
429 | * which we'll use instead of update irqs | 536 | * disable interrupts |
537 | * | ||
538 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | ||
430 | */ | 539 | */ |
431 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); | 540 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
432 | 541 | ||
433 | /* enable RTC functional clock */ | 542 | /* enable RTC functional clock */ |
434 | if (id_entry->driver_data & OMAP_RTC_HAS_32KCLK_EN) | 543 | if (rtc->type->has_32kclk_en) { |
435 | rtc_writel(OMAP_RTC_OSC_32KCLK_EN, OMAP_RTC_OSC_REG); | 544 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); |
545 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | ||
546 | reg | OMAP_RTC_OSC_32KCLK_EN); | ||
547 | } | ||
436 | 548 | ||
437 | /* clear old status */ | 549 | /* clear old status */ |
438 | reg = rtc_read(OMAP_RTC_STATUS_REG); | 550 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
439 | if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) { | ||
440 | pr_info("%s: RTC power up reset detected\n", | ||
441 | pdev->name); | ||
442 | rtc_write(OMAP_RTC_STATUS_POWER_UP, OMAP_RTC_STATUS_REG); | ||
443 | } | ||
444 | if (reg & (u8) OMAP_RTC_STATUS_ALARM) | ||
445 | rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG); | ||
446 | 551 | ||
447 | /* handle periodic and alarm irqs */ | 552 | mask = OMAP_RTC_STATUS_ALARM; |
448 | if (devm_request_irq(&pdev->dev, omap_rtc_timer, rtc_irq, 0, | 553 | |
449 | dev_name(&rtc->dev), rtc)) { | 554 | if (rtc->type->has_pmic_mode) |
450 | pr_debug("%s: RTC timer interrupt IRQ%d already claimed\n", | 555 | mask |= OMAP_RTC_STATUS_ALARM2; |
451 | pdev->name, omap_rtc_timer); | 556 | |
452 | goto fail0; | 557 | if (rtc->type->has_power_up_reset) { |
453 | } | 558 | mask |= OMAP_RTC_STATUS_POWER_UP; |
454 | if ((omap_rtc_timer != omap_rtc_alarm) && | 559 | if (reg & OMAP_RTC_STATUS_POWER_UP) |
455 | (devm_request_irq(&pdev->dev, omap_rtc_alarm, rtc_irq, 0, | 560 | dev_info(&pdev->dev, "RTC power up reset detected\n"); |
456 | dev_name(&rtc->dev), rtc))) { | ||
457 | pr_debug("%s: RTC alarm interrupt IRQ%d already claimed\n", | ||
458 | pdev->name, omap_rtc_alarm); | ||
459 | goto fail0; | ||
460 | } | 561 | } |
461 | 562 | ||
563 | if (reg & mask) | ||
564 | rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); | ||
565 | |||
462 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ | 566 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
463 | reg = rtc_read(OMAP_RTC_CTRL_REG); | 567 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
464 | if (reg & (u8) OMAP_RTC_CTRL_STOP) | 568 | if (reg & OMAP_RTC_CTRL_STOP) |
465 | pr_info("%s: already running\n", pdev->name); | 569 | dev_info(&pdev->dev, "already running\n"); |
466 | 570 | ||
467 | /* force to 24 hour mode */ | 571 | /* force to 24 hour mode */ |
468 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT|OMAP_RTC_CTRL_AUTO_COMP); | 572 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); |
469 | new_ctrl |= OMAP_RTC_CTRL_STOP; | 573 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
470 | 574 | ||
471 | /* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | 575 | /* |
576 | * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | ||
472 | * | 577 | * |
473 | * - Device wake-up capability setting should come through chip | 578 | * - Device wake-up capability setting should come through chip |
474 | * init logic. OMAP1 boards should initialize the "wakeup capable" | 579 | * init logic. OMAP1 boards should initialize the "wakeup capable" |
@@ -482,36 +587,70 @@ static int __init omap_rtc_probe(struct platform_device *pdev) | |||
482 | * is write-only, and always reads as zero...) | 587 | * is write-only, and always reads as zero...) |
483 | */ | 588 | */ |
484 | 589 | ||
590 | if (new_ctrl & OMAP_RTC_CTRL_SPLIT) | ||
591 | dev_info(&pdev->dev, "split power mode\n"); | ||
592 | |||
593 | if (reg != new_ctrl) | ||
594 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); | ||
595 | |||
485 | device_init_wakeup(&pdev->dev, true); | 596 | device_init_wakeup(&pdev->dev, true); |
486 | 597 | ||
487 | if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT) | 598 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
488 | pr_info("%s: split power mode\n", pdev->name); | 599 | &omap_rtc_ops, THIS_MODULE); |
600 | if (IS_ERR(rtc->rtc)) { | ||
601 | ret = PTR_ERR(rtc->rtc); | ||
602 | goto err; | ||
603 | } | ||
489 | 604 | ||
490 | if (reg != new_ctrl) | 605 | /* handle periodic and alarm irqs */ |
491 | rtc_write(new_ctrl, OMAP_RTC_CTRL_REG); | 606 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
607 | dev_name(&rtc->rtc->dev), rtc); | ||
608 | if (ret) | ||
609 | goto err; | ||
610 | |||
611 | if (rtc->irq_timer != rtc->irq_alarm) { | ||
612 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | ||
613 | dev_name(&rtc->rtc->dev), rtc); | ||
614 | if (ret) | ||
615 | goto err; | ||
616 | } | ||
617 | |||
618 | if (rtc->is_pmic_controller) { | ||
619 | if (!pm_power_off) { | ||
620 | omap_rtc_power_off_rtc = rtc; | ||
621 | pm_power_off = omap_rtc_power_off; | ||
622 | } | ||
623 | } | ||
492 | 624 | ||
493 | return 0; | 625 | return 0; |
494 | 626 | ||
495 | fail0: | 627 | err: |
496 | if (id_entry->driver_data & OMAP_RTC_HAS_KICKER) | 628 | device_init_wakeup(&pdev->dev, false); |
497 | rtc_writel(0, OMAP_RTC_KICK0_REG); | 629 | if (rtc->type->has_kicker) |
630 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | ||
498 | pm_runtime_put_sync(&pdev->dev); | 631 | pm_runtime_put_sync(&pdev->dev); |
499 | pm_runtime_disable(&pdev->dev); | 632 | pm_runtime_disable(&pdev->dev); |
500 | return -EIO; | 633 | |
634 | return ret; | ||
501 | } | 635 | } |
502 | 636 | ||
503 | static int __exit omap_rtc_remove(struct platform_device *pdev) | 637 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
504 | { | 638 | { |
505 | const struct platform_device_id *id_entry = | 639 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
506 | platform_get_device_id(pdev); | 640 | |
641 | if (pm_power_off == omap_rtc_power_off && | ||
642 | omap_rtc_power_off_rtc == rtc) { | ||
643 | pm_power_off = NULL; | ||
644 | omap_rtc_power_off_rtc = NULL; | ||
645 | } | ||
507 | 646 | ||
508 | device_init_wakeup(&pdev->dev, 0); | 647 | device_init_wakeup(&pdev->dev, 0); |
509 | 648 | ||
510 | /* leave rtc running, but disable irqs */ | 649 | /* leave rtc running, but disable irqs */ |
511 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); | 650 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
512 | 651 | ||
513 | if (id_entry->driver_data & OMAP_RTC_HAS_KICKER) | 652 | if (rtc->type->has_kicker) |
514 | rtc_writel(0, OMAP_RTC_KICK0_REG); | 653 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); |
515 | 654 | ||
516 | /* Disable the clock/module */ | 655 | /* Disable the clock/module */ |
517 | pm_runtime_put_sync(&pdev->dev); | 656 | pm_runtime_put_sync(&pdev->dev); |
@@ -521,20 +660,21 @@ static int __exit omap_rtc_remove(struct platform_device *pdev) | |||
521 | } | 660 | } |
522 | 661 | ||
523 | #ifdef CONFIG_PM_SLEEP | 662 | #ifdef CONFIG_PM_SLEEP |
524 | static u8 irqstat; | ||
525 | |||
526 | static int omap_rtc_suspend(struct device *dev) | 663 | static int omap_rtc_suspend(struct device *dev) |
527 | { | 664 | { |
528 | irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG); | 665 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
529 | 666 | ||
530 | /* FIXME the RTC alarm is not currently acting as a wakeup event | 667 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
668 | |||
669 | /* | ||
670 | * FIXME: the RTC alarm is not currently acting as a wakeup event | ||
531 | * source on some platforms, and in fact this enable() call is just | 671 | * source on some platforms, and in fact this enable() call is just |
532 | * saving a flag that's never used... | 672 | * saving a flag that's never used... |
533 | */ | 673 | */ |
534 | if (device_may_wakeup(dev)) | 674 | if (device_may_wakeup(dev)) |
535 | enable_irq_wake(omap_rtc_alarm); | 675 | enable_irq_wake(rtc->irq_alarm); |
536 | else | 676 | else |
537 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); | 677 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
538 | 678 | ||
539 | /* Disable the clock/module */ | 679 | /* Disable the clock/module */ |
540 | pm_runtime_put_sync(dev); | 680 | pm_runtime_put_sync(dev); |
@@ -544,13 +684,15 @@ static int omap_rtc_suspend(struct device *dev) | |||
544 | 684 | ||
545 | static int omap_rtc_resume(struct device *dev) | 685 | static int omap_rtc_resume(struct device *dev) |
546 | { | 686 | { |
687 | struct omap_rtc *rtc = dev_get_drvdata(dev); | ||
688 | |||
547 | /* Enable the clock/module so that we can access the registers */ | 689 | /* Enable the clock/module so that we can access the registers */ |
548 | pm_runtime_get_sync(dev); | 690 | pm_runtime_get_sync(dev); |
549 | 691 | ||
550 | if (device_may_wakeup(dev)) | 692 | if (device_may_wakeup(dev)) |
551 | disable_irq_wake(omap_rtc_alarm); | 693 | disable_irq_wake(rtc->irq_alarm); |
552 | else | 694 | else |
553 | rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG); | 695 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
554 | 696 | ||
555 | return 0; | 697 | return 0; |
556 | } | 698 | } |
@@ -560,23 +702,32 @@ static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); | |||
560 | 702 | ||
561 | static void omap_rtc_shutdown(struct platform_device *pdev) | 703 | static void omap_rtc_shutdown(struct platform_device *pdev) |
562 | { | 704 | { |
563 | rtc_write(0, OMAP_RTC_INTERRUPTS_REG); | 705 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
706 | u8 mask; | ||
707 | |||
708 | /* | ||
709 | * Keep the ALARM interrupt enabled to allow the system to power up on | ||
710 | * alarm events. | ||
711 | */ | ||
712 | mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | ||
713 | mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; | ||
714 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); | ||
564 | } | 715 | } |
565 | 716 | ||
566 | MODULE_ALIAS("platform:omap_rtc"); | ||
567 | static struct platform_driver omap_rtc_driver = { | 717 | static struct platform_driver omap_rtc_driver = { |
568 | .remove = __exit_p(omap_rtc_remove), | 718 | .remove = __exit_p(omap_rtc_remove), |
569 | .shutdown = omap_rtc_shutdown, | 719 | .shutdown = omap_rtc_shutdown, |
570 | .driver = { | 720 | .driver = { |
571 | .name = DRIVER_NAME, | 721 | .name = "omap_rtc", |
572 | .owner = THIS_MODULE, | 722 | .owner = THIS_MODULE, |
573 | .pm = &omap_rtc_pm_ops, | 723 | .pm = &omap_rtc_pm_ops, |
574 | .of_match_table = omap_rtc_of_match, | 724 | .of_match_table = omap_rtc_of_match, |
575 | }, | 725 | }, |
576 | .id_table = omap_rtc_devtype, | 726 | .id_table = omap_rtc_id_table, |
577 | }; | 727 | }; |
578 | 728 | ||
579 | module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe); | 729 | module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe); |
580 | 730 | ||
731 | MODULE_ALIAS("platform:omap_rtc"); | ||
581 | MODULE_AUTHOR("George G. Davis (and others)"); | 732 | MODULE_AUTHOR("George G. Davis (and others)"); |
582 | MODULE_LICENSE("GPL"); | 733 | MODULE_LICENSE("GPL"); |