diff options
Diffstat (limited to 'drivers/rtc/rtc-cmos.c')
-rw-r--r-- | drivers/rtc/rtc-cmos.c | 294 |
1 files changed, 176 insertions, 118 deletions
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index d7bb9bac71df..6ea349aba3ba 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c | |||
@@ -36,25 +36,9 @@ | |||
36 | #include <linux/platform_device.h> | 36 | #include <linux/platform_device.h> |
37 | #include <linux/mod_devicetable.h> | 37 | #include <linux/mod_devicetable.h> |
38 | 38 | ||
39 | #ifdef CONFIG_HPET_EMULATE_RTC | ||
40 | #include <asm/hpet.h> | ||
41 | #endif | ||
42 | |||
43 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | 39 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ |
44 | #include <asm-generic/rtc.h> | 40 | #include <asm-generic/rtc.h> |
45 | 41 | ||
46 | #ifndef CONFIG_HPET_EMULATE_RTC | ||
47 | #define is_hpet_enabled() 0 | ||
48 | #define hpet_set_alarm_time(hrs, min, sec) do { } while (0) | ||
49 | #define hpet_set_periodic_freq(arg) 0 | ||
50 | #define hpet_mask_rtc_irq_bit(arg) do { } while (0) | ||
51 | #define hpet_set_rtc_irq_bit(arg) do { } while (0) | ||
52 | #define hpet_rtc_timer_init() do { } while (0) | ||
53 | #define hpet_register_irq_handler(h) 0 | ||
54 | #define hpet_unregister_irq_handler(h) do { } while (0) | ||
55 | extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); | ||
56 | #endif | ||
57 | |||
58 | struct cmos_rtc { | 42 | struct cmos_rtc { |
59 | struct rtc_device *rtc; | 43 | struct rtc_device *rtc; |
60 | struct device *dev; | 44 | struct device *dev; |
@@ -93,6 +77,72 @@ static inline int is_intr(u8 rtc_intr) | |||
93 | 77 | ||
94 | /*----------------------------------------------------------------*/ | 78 | /*----------------------------------------------------------------*/ |
95 | 79 | ||
80 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because | ||
81 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | ||
82 | * used in a broken "legacy replacement" mode. The breakage includes | ||
83 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | ||
84 | * other (better) use. | ||
85 | * | ||
86 | * When that broken mode is in use, platform glue provides a partial | ||
87 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | ||
88 | * want to use HPET for anything except those IRQs though... | ||
89 | */ | ||
90 | #ifdef CONFIG_HPET_EMULATE_RTC | ||
91 | #include <asm/hpet.h> | ||
92 | #else | ||
93 | |||
94 | static inline int is_hpet_enabled(void) | ||
95 | { | ||
96 | return 0; | ||
97 | } | ||
98 | |||
99 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | ||
100 | { | ||
101 | return 0; | ||
102 | } | ||
103 | |||
104 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | ||
105 | { | ||
106 | return 0; | ||
107 | } | ||
108 | |||
109 | static inline int | ||
110 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | ||
111 | { | ||
112 | return 0; | ||
113 | } | ||
114 | |||
115 | static inline int hpet_set_periodic_freq(unsigned long freq) | ||
116 | { | ||
117 | return 0; | ||
118 | } | ||
119 | |||
120 | static inline int hpet_rtc_dropped_irq(void) | ||
121 | { | ||
122 | return 0; | ||
123 | } | ||
124 | |||
125 | static inline int hpet_rtc_timer_init(void) | ||
126 | { | ||
127 | return 0; | ||
128 | } | ||
129 | |||
130 | extern irq_handler_t hpet_rtc_interrupt; | ||
131 | |||
132 | static inline int hpet_register_irq_handler(irq_handler_t handler) | ||
133 | { | ||
134 | return 0; | ||
135 | } | ||
136 | |||
137 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | ||
138 | { | ||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | #endif | ||
143 | |||
144 | /*----------------------------------------------------------------*/ | ||
145 | |||
96 | static int cmos_read_time(struct device *dev, struct rtc_time *t) | 146 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
97 | { | 147 | { |
98 | /* REVISIT: if the clock has a "century" register, use | 148 | /* REVISIT: if the clock has a "century" register, use |
@@ -185,11 +235,56 @@ static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |||
185 | return 0; | 235 | return 0; |
186 | } | 236 | } |
187 | 237 | ||
238 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) | ||
239 | { | ||
240 | unsigned char rtc_intr; | ||
241 | |||
242 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | ||
243 | * allegedly some older rtcs need that to handle irqs properly | ||
244 | */ | ||
245 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | ||
246 | |||
247 | if (is_hpet_enabled()) | ||
248 | return; | ||
249 | |||
250 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | ||
251 | if (is_intr(rtc_intr)) | ||
252 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | ||
253 | } | ||
254 | |||
255 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | ||
256 | { | ||
257 | unsigned char rtc_control; | ||
258 | |||
259 | /* flush any pending IRQ status, notably for update irqs, | ||
260 | * before we enable new IRQs | ||
261 | */ | ||
262 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
263 | cmos_checkintr(cmos, rtc_control); | ||
264 | |||
265 | rtc_control |= mask; | ||
266 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
267 | hpet_set_rtc_irq_bit(mask); | ||
268 | |||
269 | cmos_checkintr(cmos, rtc_control); | ||
270 | } | ||
271 | |||
272 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | ||
273 | { | ||
274 | unsigned char rtc_control; | ||
275 | |||
276 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
277 | rtc_control &= ~mask; | ||
278 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
279 | hpet_mask_rtc_irq_bit(mask); | ||
280 | |||
281 | cmos_checkintr(cmos, rtc_control); | ||
282 | } | ||
283 | |||
188 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) | 284 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
189 | { | 285 | { |
190 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | 286 | struct cmos_rtc *cmos = dev_get_drvdata(dev); |
191 | unsigned char mon, mday, hrs, min, sec; | 287 | unsigned char mon, mday, hrs, min, sec; |
192 | unsigned char rtc_control, rtc_intr; | ||
193 | 288 | ||
194 | if (!is_valid_irq(cmos->irq)) | 289 | if (!is_valid_irq(cmos->irq)) |
195 | return -EIO; | 290 | return -EIO; |
@@ -213,17 +308,10 @@ static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |||
213 | sec = t->time.tm_sec; | 308 | sec = t->time.tm_sec; |
214 | sec = (sec < 60) ? BIN2BCD(sec) : 0xff; | 309 | sec = (sec < 60) ? BIN2BCD(sec) : 0xff; |
215 | 310 | ||
216 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | ||
217 | spin_lock_irq(&rtc_lock); | 311 | spin_lock_irq(&rtc_lock); |
218 | 312 | ||
219 | /* next rtc irq must not be from previous alarm setting */ | 313 | /* next rtc irq must not be from previous alarm setting */ |
220 | rtc_control = CMOS_READ(RTC_CONTROL); | 314 | cmos_irq_disable(cmos, RTC_AIE); |
221 | rtc_control &= ~RTC_AIE; | ||
222 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
223 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | ||
224 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | ||
225 | if (is_intr(rtc_intr)) | ||
226 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | ||
227 | 315 | ||
228 | /* update alarm */ | 316 | /* update alarm */ |
229 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | 317 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); |
@@ -237,14 +325,13 @@ static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |||
237 | CMOS_WRITE(mon, cmos->mon_alrm); | 325 | CMOS_WRITE(mon, cmos->mon_alrm); |
238 | } | 326 | } |
239 | 327 | ||
240 | if (t->enabled) { | 328 | /* FIXME the HPET alarm glue currently ignores day_alrm |
241 | rtc_control |= RTC_AIE; | 329 | * and mon_alrm ... |
242 | CMOS_WRITE(rtc_control, RTC_CONTROL); | 330 | */ |
243 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | 331 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); |
244 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | 332 | |
245 | if (is_intr(rtc_intr)) | 333 | if (t->enabled) |
246 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | 334 | cmos_irq_enable(cmos, RTC_AIE); |
247 | } | ||
248 | 335 | ||
249 | spin_unlock_irq(&rtc_lock); | 336 | spin_unlock_irq(&rtc_lock); |
250 | 337 | ||
@@ -267,8 +354,8 @@ static int cmos_irq_set_freq(struct device *dev, int freq) | |||
267 | f = 16 - f; | 354 | f = 16 - f; |
268 | 355 | ||
269 | spin_lock_irqsave(&rtc_lock, flags); | 356 | spin_lock_irqsave(&rtc_lock, flags); |
270 | if (!hpet_set_periodic_freq(freq)) | 357 | hpet_set_periodic_freq(freq); |
271 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | 358 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); |
272 | spin_unlock_irqrestore(&rtc_lock, flags); | 359 | spin_unlock_irqrestore(&rtc_lock, flags); |
273 | 360 | ||
274 | return 0; | 361 | return 0; |
@@ -277,26 +364,17 @@ static int cmos_irq_set_freq(struct device *dev, int freq) | |||
277 | static int cmos_irq_set_state(struct device *dev, int enabled) | 364 | static int cmos_irq_set_state(struct device *dev, int enabled) |
278 | { | 365 | { |
279 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | 366 | struct cmos_rtc *cmos = dev_get_drvdata(dev); |
280 | unsigned char rtc_control, rtc_intr; | ||
281 | unsigned long flags; | 367 | unsigned long flags; |
282 | 368 | ||
283 | if (!is_valid_irq(cmos->irq)) | 369 | if (!is_valid_irq(cmos->irq)) |
284 | return -ENXIO; | 370 | return -ENXIO; |
285 | 371 | ||
286 | spin_lock_irqsave(&rtc_lock, flags); | 372 | spin_lock_irqsave(&rtc_lock, flags); |
287 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
288 | 373 | ||
289 | if (enabled) | 374 | if (enabled) |
290 | rtc_control |= RTC_PIE; | 375 | cmos_irq_enable(cmos, RTC_PIE); |
291 | else | 376 | else |
292 | rtc_control &= ~RTC_PIE; | 377 | cmos_irq_disable(cmos, RTC_PIE); |
293 | |||
294 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
295 | |||
296 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | ||
297 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | ||
298 | if (is_intr(rtc_intr)) | ||
299 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | ||
300 | 378 | ||
301 | spin_unlock_irqrestore(&rtc_lock, flags); | 379 | spin_unlock_irqrestore(&rtc_lock, flags); |
302 | return 0; | 380 | return 0; |
@@ -308,7 +386,6 @@ static int | |||
308 | cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | 386 | cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) |
309 | { | 387 | { |
310 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | 388 | struct cmos_rtc *cmos = dev_get_drvdata(dev); |
311 | unsigned char rtc_control, rtc_intr; | ||
312 | unsigned long flags; | 389 | unsigned long flags; |
313 | 390 | ||
314 | switch (cmd) { | 391 | switch (cmd) { |
@@ -316,51 +393,29 @@ cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |||
316 | case RTC_AIE_ON: | 393 | case RTC_AIE_ON: |
317 | case RTC_UIE_OFF: | 394 | case RTC_UIE_OFF: |
318 | case RTC_UIE_ON: | 395 | case RTC_UIE_ON: |
319 | case RTC_PIE_OFF: | ||
320 | case RTC_PIE_ON: | ||
321 | if (!is_valid_irq(cmos->irq)) | 396 | if (!is_valid_irq(cmos->irq)) |
322 | return -EINVAL; | 397 | return -EINVAL; |
323 | break; | 398 | break; |
399 | /* PIE ON/OFF is handled by cmos_irq_set_state() */ | ||
324 | default: | 400 | default: |
325 | return -ENOIOCTLCMD; | 401 | return -ENOIOCTLCMD; |
326 | } | 402 | } |
327 | 403 | ||
328 | spin_lock_irqsave(&rtc_lock, flags); | 404 | spin_lock_irqsave(&rtc_lock, flags); |
329 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
330 | switch (cmd) { | 405 | switch (cmd) { |
331 | case RTC_AIE_OFF: /* alarm off */ | 406 | case RTC_AIE_OFF: /* alarm off */ |
332 | rtc_control &= ~RTC_AIE; | 407 | cmos_irq_disable(cmos, RTC_AIE); |
333 | hpet_mask_rtc_irq_bit(RTC_AIE); | ||
334 | break; | 408 | break; |
335 | case RTC_AIE_ON: /* alarm on */ | 409 | case RTC_AIE_ON: /* alarm on */ |
336 | rtc_control |= RTC_AIE; | 410 | cmos_irq_enable(cmos, RTC_AIE); |
337 | hpet_set_rtc_irq_bit(RTC_AIE); | ||
338 | break; | 411 | break; |
339 | case RTC_UIE_OFF: /* update off */ | 412 | case RTC_UIE_OFF: /* update off */ |
340 | rtc_control &= ~RTC_UIE; | 413 | cmos_irq_disable(cmos, RTC_UIE); |
341 | hpet_mask_rtc_irq_bit(RTC_UIE); | ||
342 | break; | 414 | break; |
343 | case RTC_UIE_ON: /* update on */ | 415 | case RTC_UIE_ON: /* update on */ |
344 | rtc_control |= RTC_UIE; | 416 | cmos_irq_enable(cmos, RTC_UIE); |
345 | hpet_set_rtc_irq_bit(RTC_UIE); | ||
346 | break; | ||
347 | case RTC_PIE_OFF: /* periodic off */ | ||
348 | rtc_control &= ~RTC_PIE; | ||
349 | hpet_mask_rtc_irq_bit(RTC_PIE); | ||
350 | break; | ||
351 | case RTC_PIE_ON: /* periodic on */ | ||
352 | rtc_control |= RTC_PIE; | ||
353 | hpet_set_rtc_irq_bit(RTC_PIE); | ||
354 | break; | 417 | break; |
355 | } | 418 | } |
356 | if (!is_hpet_enabled()) | ||
357 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
358 | |||
359 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | ||
360 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | ||
361 | if (is_intr(rtc_intr)) | ||
362 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | ||
363 | |||
364 | spin_unlock_irqrestore(&rtc_lock, flags); | 419 | spin_unlock_irqrestore(&rtc_lock, flags); |
365 | return 0; | 420 | return 0; |
366 | } | 421 | } |
@@ -502,27 +557,29 @@ static irqreturn_t cmos_interrupt(int irq, void *p) | |||
502 | u8 rtc_control; | 557 | u8 rtc_control; |
503 | 558 | ||
504 | spin_lock(&rtc_lock); | 559 | spin_lock(&rtc_lock); |
505 | /* | 560 | |
506 | * In this case it is HPET RTC interrupt handler | 561 | /* When the HPET interrupt handler calls us, the interrupt |
507 | * calling us, with the interrupt information | 562 | * status is passed as arg1 instead of the irq number. But |
508 | * passed as arg1, instead of irq. | 563 | * always clear irq status, even when HPET is in the way. |
564 | * | ||
565 | * Note that HPET and RTC are almost certainly out of phase, | ||
566 | * giving different IRQ status ... | ||
509 | */ | 567 | */ |
568 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | ||
569 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
510 | if (is_hpet_enabled()) | 570 | if (is_hpet_enabled()) |
511 | irqstat = (unsigned long)irq & 0xF0; | 571 | irqstat = (unsigned long)irq & 0xF0; |
512 | else { | 572 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
513 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | ||
514 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
515 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | ||
516 | } | ||
517 | 573 | ||
518 | /* All Linux RTC alarms should be treated as if they were oneshot. | 574 | /* All Linux RTC alarms should be treated as if they were oneshot. |
519 | * Similar code may be needed in system wakeup paths, in case the | 575 | * Similar code may be needed in system wakeup paths, in case the |
520 | * alarm woke the system. | 576 | * alarm woke the system. |
521 | */ | 577 | */ |
522 | if (irqstat & RTC_AIE) { | 578 | if (irqstat & RTC_AIE) { |
523 | rtc_control = CMOS_READ(RTC_CONTROL); | ||
524 | rtc_control &= ~RTC_AIE; | 579 | rtc_control &= ~RTC_AIE; |
525 | CMOS_WRITE(rtc_control, RTC_CONTROL); | 580 | CMOS_WRITE(rtc_control, RTC_CONTROL); |
581 | hpet_mask_rtc_irq_bit(RTC_AIE); | ||
582 | |||
526 | CMOS_READ(RTC_INTR_FLAGS); | 583 | CMOS_READ(RTC_INTR_FLAGS); |
527 | } | 584 | } |
528 | spin_unlock(&rtc_lock); | 585 | spin_unlock(&rtc_lock); |
@@ -629,18 +686,13 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |||
629 | * do something about other clock frequencies. | 686 | * do something about other clock frequencies. |
630 | */ | 687 | */ |
631 | cmos_rtc.rtc->irq_freq = 1024; | 688 | cmos_rtc.rtc->irq_freq = 1024; |
632 | if (!hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq)) | 689 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); |
633 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | 690 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); |
691 | |||
692 | /* disable irqs */ | ||
693 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | ||
634 | 694 | ||
635 | /* disable irqs. | ||
636 | * | ||
637 | * NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | ||
638 | * allegedly some older rtcs need that to handle irqs properly | ||
639 | */ | ||
640 | rtc_control = CMOS_READ(RTC_CONTROL); | 695 | rtc_control = CMOS_READ(RTC_CONTROL); |
641 | rtc_control &= ~(RTC_PIE | RTC_AIE | RTC_UIE); | ||
642 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
643 | CMOS_READ(RTC_INTR_FLAGS); | ||
644 | 696 | ||
645 | spin_unlock_irq(&rtc_lock); | 697 | spin_unlock_irq(&rtc_lock); |
646 | 698 | ||
@@ -687,7 +739,7 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |||
687 | goto cleanup2; | 739 | goto cleanup2; |
688 | } | 740 | } |
689 | 741 | ||
690 | pr_info("%s: alarms up to one %s%s\n", | 742 | pr_info("%s: alarms up to one %s%s%s\n", |
691 | cmos_rtc.rtc->dev.bus_id, | 743 | cmos_rtc.rtc->dev.bus_id, |
692 | is_valid_irq(rtc_irq) | 744 | is_valid_irq(rtc_irq) |
693 | ? (cmos_rtc.mon_alrm | 745 | ? (cmos_rtc.mon_alrm |
@@ -695,8 +747,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |||
695 | : (cmos_rtc.day_alrm | 747 | : (cmos_rtc.day_alrm |
696 | ? "month" : "day")) | 748 | ? "month" : "day")) |
697 | : "no", | 749 | : "no", |
698 | cmos_rtc.century ? ", y3k" : "" | 750 | cmos_rtc.century ? ", y3k" : "", |
699 | ); | 751 | is_hpet_enabled() ? ", hpet irqs" : ""); |
700 | 752 | ||
701 | return 0; | 753 | return 0; |
702 | 754 | ||
@@ -713,13 +765,8 @@ cleanup0: | |||
713 | 765 | ||
714 | static void cmos_do_shutdown(void) | 766 | static void cmos_do_shutdown(void) |
715 | { | 767 | { |
716 | unsigned char rtc_control; | ||
717 | |||
718 | spin_lock_irq(&rtc_lock); | 768 | spin_lock_irq(&rtc_lock); |
719 | rtc_control = CMOS_READ(RTC_CONTROL); | 769 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); |
720 | rtc_control &= ~(RTC_PIE|RTC_AIE|RTC_UIE); | ||
721 | CMOS_WRITE(rtc_control, RTC_CONTROL); | ||
722 | CMOS_READ(RTC_INTR_FLAGS); | ||
723 | spin_unlock_irq(&rtc_lock); | 770 | spin_unlock_irq(&rtc_lock); |
724 | } | 771 | } |
725 | 772 | ||
@@ -760,17 +807,17 @@ static int cmos_suspend(struct device *dev, pm_message_t mesg) | |||
760 | spin_lock_irq(&rtc_lock); | 807 | spin_lock_irq(&rtc_lock); |
761 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | 808 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); |
762 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | 809 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { |
763 | unsigned char irqstat; | 810 | unsigned char mask; |
764 | 811 | ||
765 | if (do_wake) | 812 | if (do_wake) |
766 | tmp &= ~(RTC_PIE|RTC_UIE); | 813 | mask = RTC_IRQMASK & ~RTC_AIE; |
767 | else | 814 | else |
768 | tmp &= ~(RTC_PIE|RTC_AIE|RTC_UIE); | 815 | mask = RTC_IRQMASK; |
816 | tmp &= ~mask; | ||
769 | CMOS_WRITE(tmp, RTC_CONTROL); | 817 | CMOS_WRITE(tmp, RTC_CONTROL); |
770 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | 818 | hpet_mask_rtc_irq_bit(mask); |
771 | irqstat &= (tmp & RTC_IRQMASK) | RTC_IRQF; | 819 | |
772 | if (is_intr(irqstat)) | 820 | cmos_checkintr(cmos, tmp); |
773 | rtc_update_irq(cmos->rtc, 1, irqstat); | ||
774 | } | 821 | } |
775 | spin_unlock_irq(&rtc_lock); | 822 | spin_unlock_irq(&rtc_lock); |
776 | 823 | ||
@@ -796,7 +843,8 @@ static int cmos_resume(struct device *dev) | |||
796 | unsigned char tmp = cmos->suspend_ctrl; | 843 | unsigned char tmp = cmos->suspend_ctrl; |
797 | 844 | ||
798 | /* re-enable any irqs previously active */ | 845 | /* re-enable any irqs previously active */ |
799 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | 846 | if (tmp & RTC_IRQMASK) { |
847 | unsigned char mask; | ||
800 | 848 | ||
801 | if (cmos->enabled_wake) { | 849 | if (cmos->enabled_wake) { |
802 | if (cmos->wake_off) | 850 | if (cmos->wake_off) |
@@ -807,18 +855,28 @@ static int cmos_resume(struct device *dev) | |||
807 | } | 855 | } |
808 | 856 | ||
809 | spin_lock_irq(&rtc_lock); | 857 | spin_lock_irq(&rtc_lock); |
810 | CMOS_WRITE(tmp, RTC_CONTROL); | 858 | do { |
811 | tmp = CMOS_READ(RTC_INTR_FLAGS); | 859 | CMOS_WRITE(tmp, RTC_CONTROL); |
812 | tmp &= (cmos->suspend_ctrl & RTC_IRQMASK) | RTC_IRQF; | 860 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); |
813 | if (is_intr(tmp)) | 861 | |
814 | rtc_update_irq(cmos->rtc, 1, tmp); | 862 | mask = CMOS_READ(RTC_INTR_FLAGS); |
863 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | ||
864 | if (!is_hpet_enabled() || !is_intr(mask)) | ||
865 | break; | ||
866 | |||
867 | /* force one-shot behavior if HPET blocked | ||
868 | * the wake alarm's irq | ||
869 | */ | ||
870 | rtc_update_irq(cmos->rtc, 1, mask); | ||
871 | tmp &= ~RTC_AIE; | ||
872 | hpet_mask_rtc_irq_bit(RTC_AIE); | ||
873 | } while (mask & RTC_AIE); | ||
815 | spin_unlock_irq(&rtc_lock); | 874 | spin_unlock_irq(&rtc_lock); |
816 | } | 875 | } |
817 | 876 | ||
818 | pr_debug("%s: resume, ctrl %02x\n", | 877 | pr_debug("%s: resume, ctrl %02x\n", |
819 | cmos_rtc.rtc->dev.bus_id, | 878 | cmos_rtc.rtc->dev.bus_id, |
820 | cmos->suspend_ctrl); | 879 | tmp); |
821 | |||
822 | 880 | ||
823 | return 0; | 881 | return 0; |
824 | } | 882 | } |