diff options
Diffstat (limited to 'drivers/regulator')
-rw-r--r-- | drivers/regulator/anatop-regulator.c | 18 | ||||
-rw-r--r-- | drivers/regulator/tps65910-regulator.c | 82 | ||||
-rw-r--r-- | drivers/regulator/wm831x-dcdc.c | 24 | ||||
-rw-r--r-- | drivers/regulator/wm831x-isink.c | 4 | ||||
-rw-r--r-- | drivers/regulator/wm831x-ldo.c | 10 |
5 files changed, 70 insertions, 68 deletions
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c index 49b2112b0486..3660bace123c 100644 --- a/drivers/regulator/anatop-regulator.c +++ b/drivers/regulator/anatop-regulator.c | |||
@@ -47,7 +47,7 @@ static int anatop_set_voltage(struct regulator_dev *reg, int min_uV, | |||
47 | int max_uV, unsigned *selector) | 47 | int max_uV, unsigned *selector) |
48 | { | 48 | { |
49 | struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); | 49 | struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); |
50 | u32 val, sel; | 50 | u32 val, sel, mask; |
51 | int uv; | 51 | int uv; |
52 | 52 | ||
53 | uv = min_uV; | 53 | uv = min_uV; |
@@ -71,11 +71,10 @@ static int anatop_set_voltage(struct regulator_dev *reg, int min_uV, | |||
71 | val = anatop_reg->min_bit_val + sel; | 71 | val = anatop_reg->min_bit_val + sel; |
72 | *selector = sel; | 72 | *selector = sel; |
73 | dev_dbg(®->dev, "%s: calculated val %d\n", __func__, val); | 73 | dev_dbg(®->dev, "%s: calculated val %d\n", __func__, val); |
74 | anatop_set_bits(anatop_reg->mfd, | 74 | mask = ((1 << anatop_reg->vol_bit_width) - 1) << |
75 | anatop_reg->control_reg, | 75 | anatop_reg->vol_bit_shift; |
76 | anatop_reg->vol_bit_shift, | 76 | val <<= anatop_reg->vol_bit_shift; |
77 | anatop_reg->vol_bit_width, | 77 | anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask); |
78 | val); | ||
79 | 78 | ||
80 | return 0; | 79 | return 0; |
81 | } | 80 | } |
@@ -88,10 +87,9 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg) | |||
88 | if (!anatop_reg->control_reg) | 87 | if (!anatop_reg->control_reg) |
89 | return -ENOTSUPP; | 88 | return -ENOTSUPP; |
90 | 89 | ||
91 | val = anatop_get_bits(anatop_reg->mfd, | 90 | val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg); |
92 | anatop_reg->control_reg, | 91 | val = (val & ((1 << anatop_reg->vol_bit_width) - 1)) >> |
93 | anatop_reg->vol_bit_shift, | 92 | anatop_reg->vol_bit_shift; |
94 | anatop_reg->vol_bit_width); | ||
95 | 93 | ||
96 | return val - anatop_reg->min_bit_val; | 94 | return val - anatop_reg->min_bit_val; |
97 | } | 95 | } |
diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c index 4e01a423471b..6bf864b4bdf6 100644 --- a/drivers/regulator/tps65910-regulator.c +++ b/drivers/regulator/tps65910-regulator.c | |||
@@ -331,21 +331,16 @@ struct tps65910_reg { | |||
331 | 331 | ||
332 | static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) | 332 | static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) |
333 | { | 333 | { |
334 | u8 val; | 334 | unsigned int val; |
335 | int err; | 335 | int err; |
336 | 336 | ||
337 | err = pmic->mfd->read(pmic->mfd, reg, 1, &val); | 337 | err = tps65910_reg_read(pmic->mfd, reg, &val); |
338 | if (err) | 338 | if (err) |
339 | return err; | 339 | return err; |
340 | 340 | ||
341 | return val; | 341 | return val; |
342 | } | 342 | } |
343 | 343 | ||
344 | static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val) | ||
345 | { | ||
346 | return pmic->mfd->write(pmic->mfd, reg, 1, &val); | ||
347 | } | ||
348 | |||
349 | static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, | 344 | static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, |
350 | u8 set_mask, u8 clear_mask) | 345 | u8 set_mask, u8 clear_mask) |
351 | { | 346 | { |
@@ -362,7 +357,7 @@ static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, | |||
362 | 357 | ||
363 | data &= ~clear_mask; | 358 | data &= ~clear_mask; |
364 | data |= set_mask; | 359 | data |= set_mask; |
365 | err = tps65910_write(pmic, reg, data); | 360 | err = tps65910_reg_write(pmic->mfd, reg, data); |
366 | if (err) | 361 | if (err) |
367 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | 362 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); |
368 | 363 | ||
@@ -371,7 +366,7 @@ out: | |||
371 | return err; | 366 | return err; |
372 | } | 367 | } |
373 | 368 | ||
374 | static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg) | 369 | static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg) |
375 | { | 370 | { |
376 | int data; | 371 | int data; |
377 | 372 | ||
@@ -385,13 +380,13 @@ static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg) | |||
385 | return data; | 380 | return data; |
386 | } | 381 | } |
387 | 382 | ||
388 | static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val) | 383 | static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val) |
389 | { | 384 | { |
390 | int err; | 385 | int err; |
391 | 386 | ||
392 | mutex_lock(&pmic->mutex); | 387 | mutex_lock(&pmic->mutex); |
393 | 388 | ||
394 | err = tps65910_write(pmic, reg, val); | 389 | err = tps65910_reg_write(pmic->mfd, reg, val); |
395 | if (err < 0) | 390 | if (err < 0) |
396 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | 391 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); |
397 | 392 | ||
@@ -490,9 +485,9 @@ static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) | |||
490 | LDO_ST_MODE_BIT); | 485 | LDO_ST_MODE_BIT); |
491 | case REGULATOR_MODE_IDLE: | 486 | case REGULATOR_MODE_IDLE: |
492 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | 487 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; |
493 | return tps65910_set_bits(mfd, reg, value); | 488 | return tps65910_reg_set_bits(mfd, reg, value); |
494 | case REGULATOR_MODE_STANDBY: | 489 | case REGULATOR_MODE_STANDBY: |
495 | return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT); | 490 | return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
496 | } | 491 | } |
497 | 492 | ||
498 | return -EINVAL; | 493 | return -EINVAL; |
@@ -507,7 +502,7 @@ static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |||
507 | if (reg < 0) | 502 | if (reg < 0) |
508 | return reg; | 503 | return reg; |
509 | 504 | ||
510 | value = tps65910_reg_read(pmic, reg); | 505 | value = tps65910_reg_read_locked(pmic, reg); |
511 | if (value < 0) | 506 | if (value < 0) |
512 | return value; | 507 | return value; |
513 | 508 | ||
@@ -527,28 +522,28 @@ static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) | |||
527 | 522 | ||
528 | switch (id) { | 523 | switch (id) { |
529 | case TPS65910_REG_VDD1: | 524 | case TPS65910_REG_VDD1: |
530 | opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP); | 525 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP); |
531 | mult = tps65910_reg_read(pmic, TPS65910_VDD1); | 526 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1); |
532 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; | 527 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
533 | srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR); | 528 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR); |
534 | sr = opvsel & VDD1_OP_CMD_MASK; | 529 | sr = opvsel & VDD1_OP_CMD_MASK; |
535 | opvsel &= VDD1_OP_SEL_MASK; | 530 | opvsel &= VDD1_OP_SEL_MASK; |
536 | srvsel &= VDD1_SR_SEL_MASK; | 531 | srvsel &= VDD1_SR_SEL_MASK; |
537 | vselmax = 75; | 532 | vselmax = 75; |
538 | break; | 533 | break; |
539 | case TPS65910_REG_VDD2: | 534 | case TPS65910_REG_VDD2: |
540 | opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP); | 535 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP); |
541 | mult = tps65910_reg_read(pmic, TPS65910_VDD2); | 536 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2); |
542 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; | 537 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
543 | srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR); | 538 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR); |
544 | sr = opvsel & VDD2_OP_CMD_MASK; | 539 | sr = opvsel & VDD2_OP_CMD_MASK; |
545 | opvsel &= VDD2_OP_SEL_MASK; | 540 | opvsel &= VDD2_OP_SEL_MASK; |
546 | srvsel &= VDD2_SR_SEL_MASK; | 541 | srvsel &= VDD2_SR_SEL_MASK; |
547 | vselmax = 75; | 542 | vselmax = 75; |
548 | break; | 543 | break; |
549 | case TPS65911_REG_VDDCTRL: | 544 | case TPS65911_REG_VDDCTRL: |
550 | opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP); | 545 | opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP); |
551 | srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR); | 546 | srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR); |
552 | sr = opvsel & VDDCTRL_OP_CMD_MASK; | 547 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
553 | opvsel &= VDDCTRL_OP_SEL_MASK; | 548 | opvsel &= VDDCTRL_OP_SEL_MASK; |
554 | srvsel &= VDDCTRL_SR_SEL_MASK; | 549 | srvsel &= VDDCTRL_SR_SEL_MASK; |
@@ -588,7 +583,7 @@ static int tps65910_get_voltage_sel(struct regulator_dev *dev) | |||
588 | if (reg < 0) | 583 | if (reg < 0) |
589 | return reg; | 584 | return reg; |
590 | 585 | ||
591 | value = tps65910_reg_read(pmic, reg); | 586 | value = tps65910_reg_read_locked(pmic, reg); |
592 | if (value < 0) | 587 | if (value < 0) |
593 | return value; | 588 | return value; |
594 | 589 | ||
@@ -625,7 +620,7 @@ static int tps65911_get_voltage_sel(struct regulator_dev *dev) | |||
625 | 620 | ||
626 | reg = pmic->get_ctrl_reg(id); | 621 | reg = pmic->get_ctrl_reg(id); |
627 | 622 | ||
628 | value = tps65910_reg_read(pmic, reg); | 623 | value = tps65910_reg_read_locked(pmic, reg); |
629 | 624 | ||
630 | switch (id) { | 625 | switch (id) { |
631 | case TPS65911_REG_LDO1: | 626 | case TPS65911_REG_LDO1: |
@@ -670,7 +665,7 @@ static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, | |||
670 | tps65910_modify_bits(pmic, TPS65910_VDD1, | 665 | tps65910_modify_bits(pmic, TPS65910_VDD1, |
671 | (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), | 666 | (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), |
672 | VDD1_VGAIN_SEL_MASK); | 667 | VDD1_VGAIN_SEL_MASK); |
673 | tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel); | 668 | tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel); |
674 | break; | 669 | break; |
675 | case TPS65910_REG_VDD2: | 670 | case TPS65910_REG_VDD2: |
676 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; | 671 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
@@ -681,11 +676,11 @@ static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, | |||
681 | tps65910_modify_bits(pmic, TPS65910_VDD2, | 676 | tps65910_modify_bits(pmic, TPS65910_VDD2, |
682 | (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), | 677 | (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), |
683 | VDD1_VGAIN_SEL_MASK); | 678 | VDD1_VGAIN_SEL_MASK); |
684 | tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel); | 679 | tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel); |
685 | break; | 680 | break; |
686 | case TPS65911_REG_VDDCTRL: | 681 | case TPS65911_REG_VDDCTRL: |
687 | vsel = selector + 3; | 682 | vsel = selector + 3; |
688 | tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel); | 683 | tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel); |
689 | } | 684 | } |
690 | 685 | ||
691 | return 0; | 686 | return 0; |
@@ -936,10 +931,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, | |||
936 | 931 | ||
937 | /* External EN1 control */ | 932 | /* External EN1 control */ |
938 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | 933 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) |
939 | ret = tps65910_set_bits(mfd, | 934 | ret = tps65910_reg_set_bits(mfd, |
940 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); | 935 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
941 | else | 936 | else |
942 | ret = tps65910_clear_bits(mfd, | 937 | ret = tps65910_reg_clear_bits(mfd, |
943 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); | 938 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
944 | if (ret < 0) { | 939 | if (ret < 0) { |
945 | dev_err(mfd->dev, | 940 | dev_err(mfd->dev, |
@@ -949,10 +944,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, | |||
949 | 944 | ||
950 | /* External EN2 control */ | 945 | /* External EN2 control */ |
951 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | 946 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) |
952 | ret = tps65910_set_bits(mfd, | 947 | ret = tps65910_reg_set_bits(mfd, |
953 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); | 948 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
954 | else | 949 | else |
955 | ret = tps65910_clear_bits(mfd, | 950 | ret = tps65910_reg_clear_bits(mfd, |
956 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); | 951 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
957 | if (ret < 0) { | 952 | if (ret < 0) { |
958 | dev_err(mfd->dev, | 953 | dev_err(mfd->dev, |
@@ -964,10 +959,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, | |||
964 | if ((tps65910_chip_id(mfd) == TPS65910) && | 959 | if ((tps65910_chip_id(mfd) == TPS65910) && |
965 | (id >= TPS65910_REG_VDIG1)) { | 960 | (id >= TPS65910_REG_VDIG1)) { |
966 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | 961 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) |
967 | ret = tps65910_set_bits(mfd, | 962 | ret = tps65910_reg_set_bits(mfd, |
968 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); | 963 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
969 | else | 964 | else |
970 | ret = tps65910_clear_bits(mfd, | 965 | ret = tps65910_reg_clear_bits(mfd, |
971 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); | 966 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
972 | if (ret < 0) { | 967 | if (ret < 0) { |
973 | dev_err(mfd->dev, | 968 | dev_err(mfd->dev, |
@@ -979,10 +974,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, | |||
979 | /* Return if no external control is selected */ | 974 | /* Return if no external control is selected */ |
980 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | 975 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { |
981 | /* Clear all sleep controls */ | 976 | /* Clear all sleep controls */ |
982 | ret = tps65910_clear_bits(mfd, | 977 | ret = tps65910_reg_clear_bits(mfd, |
983 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); | 978 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
984 | if (!ret) | 979 | if (!ret) |
985 | ret = tps65910_clear_bits(mfd, | 980 | ret = tps65910_reg_clear_bits(mfd, |
986 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); | 981 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
987 | if (ret < 0) | 982 | if (ret < 0) |
988 | dev_err(mfd->dev, | 983 | dev_err(mfd->dev, |
@@ -1001,32 +996,33 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, | |||
1001 | (tps65910_chip_id(mfd) == TPS65911))) { | 996 | (tps65910_chip_id(mfd) == TPS65911))) { |
1002 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | 997 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; |
1003 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | 998 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; |
1004 | int opvsel = tps65910_reg_read(pmic, op_reg_add); | 999 | int opvsel = tps65910_reg_read_locked(pmic, op_reg_add); |
1005 | int srvsel = tps65910_reg_read(pmic, sr_reg_add); | 1000 | int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add); |
1006 | if (opvsel & VDD1_OP_CMD_MASK) { | 1001 | if (opvsel & VDD1_OP_CMD_MASK) { |
1007 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | 1002 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; |
1008 | ret = tps65910_reg_write(pmic, op_reg_add, reg_val); | 1003 | ret = tps65910_reg_write_locked(pmic, op_reg_add, |
1004 | reg_val); | ||
1009 | if (ret < 0) { | 1005 | if (ret < 0) { |
1010 | dev_err(mfd->dev, | 1006 | dev_err(mfd->dev, |
1011 | "Error in configuring op register\n"); | 1007 | "Error in configuring op register\n"); |
1012 | return ret; | 1008 | return ret; |
1013 | } | 1009 | } |
1014 | } | 1010 | } |
1015 | ret = tps65910_reg_write(pmic, sr_reg_add, 0); | 1011 | ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0); |
1016 | if (ret < 0) { | 1012 | if (ret < 0) { |
1017 | dev_err(mfd->dev, "Error in settting sr register\n"); | 1013 | dev_err(mfd->dev, "Error in settting sr register\n"); |
1018 | return ret; | 1014 | return ret; |
1019 | } | 1015 | } |
1020 | } | 1016 | } |
1021 | 1017 | ||
1022 | ret = tps65910_clear_bits(mfd, | 1018 | ret = tps65910_reg_clear_bits(mfd, |
1023 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); | 1019 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
1024 | if (!ret) { | 1020 | if (!ret) { |
1025 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | 1021 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) |
1026 | ret = tps65910_set_bits(mfd, | 1022 | ret = tps65910_reg_set_bits(mfd, |
1027 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); | 1023 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
1028 | else | 1024 | else |
1029 | ret = tps65910_clear_bits(mfd, | 1025 | ret = tps65910_reg_clear_bits(mfd, |
1030 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); | 1026 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
1031 | } | 1027 | } |
1032 | if (ret < 0) | 1028 | if (ret < 0) |
@@ -1177,7 +1173,7 @@ static __devinit int tps65910_probe(struct platform_device *pdev) | |||
1177 | platform_set_drvdata(pdev, pmic); | 1173 | platform_set_drvdata(pdev, pmic); |
1178 | 1174 | ||
1179 | /* Give control of all register to control port */ | 1175 | /* Give control of all register to control port */ |
1180 | tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL, | 1176 | tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
1181 | DEVCTRL_SR_CTL_I2C_SEL_MASK); | 1177 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
1182 | 1178 | ||
1183 | switch(tps65910_chip_id(tps65910)) { | 1179 | switch(tps65910_chip_id(tps65910)) { |
diff --git a/drivers/regulator/wm831x-dcdc.c b/drivers/regulator/wm831x-dcdc.c index a885911bb5fc..099da11e989f 100644 --- a/drivers/regulator/wm831x-dcdc.c +++ b/drivers/regulator/wm831x-dcdc.c | |||
@@ -535,7 +535,7 @@ static __devinit int wm831x_buckv_probe(struct platform_device *pdev) | |||
535 | goto err; | 535 | goto err; |
536 | } | 536 | } |
537 | 537 | ||
538 | irq = platform_get_irq_byname(pdev, "UV"); | 538 | irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")); |
539 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq, | 539 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq, |
540 | IRQF_TRIGGER_RISING, dcdc->name, dcdc); | 540 | IRQF_TRIGGER_RISING, dcdc->name, dcdc); |
541 | if (ret != 0) { | 541 | if (ret != 0) { |
@@ -544,7 +544,7 @@ static __devinit int wm831x_buckv_probe(struct platform_device *pdev) | |||
544 | goto err_regulator; | 544 | goto err_regulator; |
545 | } | 545 | } |
546 | 546 | ||
547 | irq = platform_get_irq_byname(pdev, "HC"); | 547 | irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "HC")); |
548 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_oc_irq, | 548 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_oc_irq, |
549 | IRQF_TRIGGER_RISING, dcdc->name, dcdc); | 549 | IRQF_TRIGGER_RISING, dcdc->name, dcdc); |
550 | if (ret != 0) { | 550 | if (ret != 0) { |
@@ -558,7 +558,8 @@ static __devinit int wm831x_buckv_probe(struct platform_device *pdev) | |||
558 | return 0; | 558 | return 0; |
559 | 559 | ||
560 | err_uv: | 560 | err_uv: |
561 | free_irq(platform_get_irq_byname(pdev, "UV"), dcdc); | 561 | free_irq(wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")), |
562 | dcdc); | ||
562 | err_regulator: | 563 | err_regulator: |
563 | regulator_unregister(dcdc->regulator); | 564 | regulator_unregister(dcdc->regulator); |
564 | err: | 565 | err: |
@@ -570,11 +571,14 @@ err: | |||
570 | static __devexit int wm831x_buckv_remove(struct platform_device *pdev) | 571 | static __devexit int wm831x_buckv_remove(struct platform_device *pdev) |
571 | { | 572 | { |
572 | struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev); | 573 | struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev); |
574 | struct wm831x *wm831x = dcdc->wm831x; | ||
573 | 575 | ||
574 | platform_set_drvdata(pdev, NULL); | 576 | platform_set_drvdata(pdev, NULL); |
575 | 577 | ||
576 | free_irq(platform_get_irq_byname(pdev, "HC"), dcdc); | 578 | free_irq(wm831x_irq(wm831x, platform_get_irq_byname(pdev, "HC")), |
577 | free_irq(platform_get_irq_byname(pdev, "UV"), dcdc); | 579 | dcdc); |
580 | free_irq(wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")), | ||
581 | dcdc); | ||
578 | regulator_unregister(dcdc->regulator); | 582 | regulator_unregister(dcdc->regulator); |
579 | if (dcdc->dvs_gpio) | 583 | if (dcdc->dvs_gpio) |
580 | gpio_free(dcdc->dvs_gpio); | 584 | gpio_free(dcdc->dvs_gpio); |
@@ -726,7 +730,7 @@ static __devinit int wm831x_buckp_probe(struct platform_device *pdev) | |||
726 | goto err; | 730 | goto err; |
727 | } | 731 | } |
728 | 732 | ||
729 | irq = platform_get_irq_byname(pdev, "UV"); | 733 | irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")); |
730 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq, | 734 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq, |
731 | IRQF_TRIGGER_RISING, dcdc->name, dcdc); | 735 | IRQF_TRIGGER_RISING, dcdc->name, dcdc); |
732 | if (ret != 0) { | 736 | if (ret != 0) { |
@@ -751,7 +755,8 @@ static __devexit int wm831x_buckp_remove(struct platform_device *pdev) | |||
751 | 755 | ||
752 | platform_set_drvdata(pdev, NULL); | 756 | platform_set_drvdata(pdev, NULL); |
753 | 757 | ||
754 | free_irq(platform_get_irq_byname(pdev, "UV"), dcdc); | 758 | free_irq(wm831x_irq(dcdc->wm831x, platform_get_irq_byname(pdev, "UV")), |
759 | dcdc); | ||
755 | regulator_unregister(dcdc->regulator); | 760 | regulator_unregister(dcdc->regulator); |
756 | 761 | ||
757 | return 0; | 762 | return 0; |
@@ -859,7 +864,7 @@ static __devinit int wm831x_boostp_probe(struct platform_device *pdev) | |||
859 | goto err; | 864 | goto err; |
860 | } | 865 | } |
861 | 866 | ||
862 | irq = platform_get_irq_byname(pdev, "UV"); | 867 | irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")); |
863 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq, | 868 | ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq, |
864 | IRQF_TRIGGER_RISING, dcdc->name, | 869 | IRQF_TRIGGER_RISING, dcdc->name, |
865 | dcdc); | 870 | dcdc); |
@@ -885,7 +890,8 @@ static __devexit int wm831x_boostp_remove(struct platform_device *pdev) | |||
885 | 890 | ||
886 | platform_set_drvdata(pdev, NULL); | 891 | platform_set_drvdata(pdev, NULL); |
887 | 892 | ||
888 | free_irq(platform_get_irq_byname(pdev, "UV"), dcdc); | 893 | free_irq(wm831x_irq(dcdc->wm831x, platform_get_irq_byname(pdev, "UV")), |
894 | dcdc); | ||
889 | regulator_unregister(dcdc->regulator); | 895 | regulator_unregister(dcdc->regulator); |
890 | 896 | ||
891 | return 0; | 897 | return 0; |
diff --git a/drivers/regulator/wm831x-isink.c b/drivers/regulator/wm831x-isink.c index b50ab778b098..0d207c297714 100644 --- a/drivers/regulator/wm831x-isink.c +++ b/drivers/regulator/wm831x-isink.c | |||
@@ -202,7 +202,7 @@ static __devinit int wm831x_isink_probe(struct platform_device *pdev) | |||
202 | goto err; | 202 | goto err; |
203 | } | 203 | } |
204 | 204 | ||
205 | irq = platform_get_irq(pdev, 0); | 205 | irq = wm831x_irq(wm831x, platform_get_irq(pdev, 0)); |
206 | ret = request_threaded_irq(irq, NULL, wm831x_isink_irq, | 206 | ret = request_threaded_irq(irq, NULL, wm831x_isink_irq, |
207 | IRQF_TRIGGER_RISING, isink->name, isink); | 207 | IRQF_TRIGGER_RISING, isink->name, isink); |
208 | if (ret != 0) { | 208 | if (ret != 0) { |
@@ -227,7 +227,7 @@ static __devexit int wm831x_isink_remove(struct platform_device *pdev) | |||
227 | 227 | ||
228 | platform_set_drvdata(pdev, NULL); | 228 | platform_set_drvdata(pdev, NULL); |
229 | 229 | ||
230 | free_irq(platform_get_irq(pdev, 0), isink); | 230 | free_irq(wm831x_irq(isink->wm831x, platform_get_irq(pdev, 0)), isink); |
231 | 231 | ||
232 | regulator_unregister(isink->regulator); | 232 | regulator_unregister(isink->regulator); |
233 | 233 | ||
diff --git a/drivers/regulator/wm831x-ldo.c b/drivers/regulator/wm831x-ldo.c index aa1f8b3fbe16..a9a28d8ac185 100644 --- a/drivers/regulator/wm831x-ldo.c +++ b/drivers/regulator/wm831x-ldo.c | |||
@@ -321,7 +321,7 @@ static __devinit int wm831x_gp_ldo_probe(struct platform_device *pdev) | |||
321 | goto err; | 321 | goto err; |
322 | } | 322 | } |
323 | 323 | ||
324 | irq = platform_get_irq_byname(pdev, "UV"); | 324 | irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")); |
325 | ret = request_threaded_irq(irq, NULL, wm831x_ldo_uv_irq, | 325 | ret = request_threaded_irq(irq, NULL, wm831x_ldo_uv_irq, |
326 | IRQF_TRIGGER_RISING, ldo->name, | 326 | IRQF_TRIGGER_RISING, ldo->name, |
327 | ldo); | 327 | ldo); |
@@ -347,7 +347,8 @@ static __devexit int wm831x_gp_ldo_remove(struct platform_device *pdev) | |||
347 | 347 | ||
348 | platform_set_drvdata(pdev, NULL); | 348 | platform_set_drvdata(pdev, NULL); |
349 | 349 | ||
350 | free_irq(platform_get_irq_byname(pdev, "UV"), ldo); | 350 | free_irq(wm831x_irq(ldo->wm831x, |
351 | platform_get_irq_byname(pdev, "UV")), ldo); | ||
351 | regulator_unregister(ldo->regulator); | 352 | regulator_unregister(ldo->regulator); |
352 | 353 | ||
353 | return 0; | 354 | return 0; |
@@ -582,7 +583,7 @@ static __devinit int wm831x_aldo_probe(struct platform_device *pdev) | |||
582 | goto err; | 583 | goto err; |
583 | } | 584 | } |
584 | 585 | ||
585 | irq = platform_get_irq_byname(pdev, "UV"); | 586 | irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")); |
586 | ret = request_threaded_irq(irq, NULL, wm831x_ldo_uv_irq, | 587 | ret = request_threaded_irq(irq, NULL, wm831x_ldo_uv_irq, |
587 | IRQF_TRIGGER_RISING, ldo->name, ldo); | 588 | IRQF_TRIGGER_RISING, ldo->name, ldo); |
588 | if (ret != 0) { | 589 | if (ret != 0) { |
@@ -605,7 +606,8 @@ static __devexit int wm831x_aldo_remove(struct platform_device *pdev) | |||
605 | { | 606 | { |
606 | struct wm831x_ldo *ldo = platform_get_drvdata(pdev); | 607 | struct wm831x_ldo *ldo = platform_get_drvdata(pdev); |
607 | 608 | ||
608 | free_irq(platform_get_irq_byname(pdev, "UV"), ldo); | 609 | free_irq(wm831x_irq(ldo->wm831x, platform_get_irq_byname(pdev, "UV")), |
610 | ldo); | ||
609 | regulator_unregister(ldo->regulator); | 611 | regulator_unregister(ldo->regulator); |
610 | 612 | ||
611 | return 0; | 613 | return 0; |