aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/rapidio/switches
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/rapidio/switches')
-rw-r--r--drivers/rapidio/switches/idt_gen2.c95
-rw-r--r--drivers/rapidio/switches/idtcps.c6
-rw-r--r--drivers/rapidio/switches/tsi568.c13
-rw-r--r--drivers/rapidio/switches/tsi57x.c56
4 files changed, 63 insertions, 107 deletions
diff --git a/drivers/rapidio/switches/idt_gen2.c b/drivers/rapidio/switches/idt_gen2.c
index 0bb871cb5c40..095016a9dec1 100644
--- a/drivers/rapidio/switches/idt_gen2.c
+++ b/drivers/rapidio/switches/idt_gen2.c
@@ -209,9 +209,6 @@ idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
209static int 209static int
210idtg2_em_init(struct rio_dev *rdev) 210idtg2_em_init(struct rio_dev *rdev)
211{ 211{
212 struct rio_mport *mport = rdev->net->hport;
213 u16 destid = rdev->rswitch->destid;
214 u8 hopcount = rdev->rswitch->hopcount;
215 u32 regval; 212 u32 regval;
216 int i, tmp; 213 int i, tmp;
217 214
@@ -220,29 +217,25 @@ idtg2_em_init(struct rio_dev *rdev)
220 * All standard EM configuration should be performed at upper level. 217 * All standard EM configuration should be performed at upper level.
221 */ 218 */
222 219
223 pr_debug("RIO: %s [%d:%d]\n", __func__, destid, hopcount); 220 pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
224 221
225 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */ 222 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */
226 rio_mport_write_config_32(mport, destid, hopcount, 223 rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
227 IDT_PW_INFO_CSR, 0x0000e000);
228 224
229 /* 225 /*
230 * Configure LT LAYER error reporting. 226 * Configure LT LAYER error reporting.
231 */ 227 */
232 228
233 /* Enable standard (RIO.p8) error reporting */ 229 /* Enable standard (RIO.p8) error reporting */
234 rio_mport_write_config_32(mport, destid, hopcount, 230 rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
235 IDT_LT_ERR_REPORT_EN,
236 REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR | 231 REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR |
237 REM_LTL_ERR_UNSUPTR); 232 REM_LTL_ERR_UNSUPTR);
238 233
239 /* Use Port-Writes for LT layer error reporting. 234 /* Use Port-Writes for LT layer error reporting.
240 * Enable per-port reset 235 * Enable per-port reset
241 */ 236 */
242 rio_mport_read_config_32(mport, destid, hopcount, 237 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);
243 IDT_DEV_CTRL_1, &regval); 238 rio_write_config_32(rdev, IDT_DEV_CTRL_1,
244 rio_mport_write_config_32(mport, destid, hopcount,
245 IDT_DEV_CTRL_1,
246 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); 239 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);
247 240
248 /* 241 /*
@@ -250,45 +243,40 @@ idtg2_em_init(struct rio_dev *rdev)
250 */ 243 */
251 244
252 /* Report all RIO.p8 errors supported by device */ 245 /* Report all RIO.p8 errors supported by device */
253 rio_mport_write_config_32(mport, destid, hopcount, 246 rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
254 IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
255 247
256 /* Configure reporting of implementation specific errors/events */ 248 /* Configure reporting of implementation specific errors/events */
257 rio_mport_write_config_32(mport, destid, hopcount, 249 rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
258 IDT_PORT_ISERR_REPORT_EN_BC, IDT_PORT_INIT_TX_ACQUIRED); 250 IDT_PORT_INIT_TX_ACQUIRED);
259 251
260 /* Use Port-Writes for port error reporting and enable error logging */ 252 /* Use Port-Writes for port error reporting and enable error logging */
261 tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); 253 tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
262 for (i = 0; i < tmp; i++) { 254 for (i = 0; i < tmp; i++) {
263 rio_mport_read_config_32(mport, destid, hopcount, 255 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);
264 IDT_PORT_OPS(i), &regval); 256 rio_write_config_32(rdev,
265 rio_mport_write_config_32(mport, destid, hopcount,
266 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | 257 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
267 IDT_PORT_OPS_PL_ELOG | 258 IDT_PORT_OPS_PL_ELOG |
268 IDT_PORT_OPS_LL_ELOG | 259 IDT_PORT_OPS_LL_ELOG |
269 IDT_PORT_OPS_LT_ELOG); 260 IDT_PORT_OPS_LT_ELOG);
270 } 261 }
271 /* Overwrite error log if full */ 262 /* Overwrite error log if full */
272 rio_mport_write_config_32(mport, destid, hopcount, 263 rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
273 IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
274 264
275 /* 265 /*
276 * Configure LANE error reporting. 266 * Configure LANE error reporting.
277 */ 267 */
278 268
279 /* Disable line error reporting */ 269 /* Disable line error reporting */
280 rio_mport_write_config_32(mport, destid, hopcount, 270 rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
281 IDT_LANE_ERR_REPORT_EN_BC, 0);
282 271
283 /* Use Port-Writes for lane error reporting (when enabled) 272 /* Use Port-Writes for lane error reporting (when enabled)
284 * (do per-lane update because lanes may have different configuration) 273 * (do per-lane update because lanes may have different configuration)
285 */ 274 */
286 tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; 275 tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
287 for (i = 0; i < tmp; i++) { 276 for (i = 0; i < tmp; i++) {
288 rio_mport_read_config_32(mport, destid, hopcount, 277 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);
289 IDT_LANE_CTRL(i), &regval); 278 rio_write_config_32(rdev, IDT_LANE_CTRL(i),
290 rio_mport_write_config_32(mport, destid, hopcount, 279 regval | IDT_LANE_CTRL_GENPW);
291 IDT_LANE_CTRL(i), regval | IDT_LANE_CTRL_GENPW);
292 } 280 }
293 281
294 /* 282 /*
@@ -296,41 +284,32 @@ idtg2_em_init(struct rio_dev *rdev)
296 */ 284 */
297 285
298 /* Disable JTAG and I2C Error capture */ 286 /* Disable JTAG and I2C Error capture */
299 rio_mport_write_config_32(mport, destid, hopcount, 287 rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
300 IDT_AUX_PORT_ERR_CAP_EN, 0);
301 288
302 /* Disable JTAG and I2C Error reporting/logging */ 289 /* Disable JTAG and I2C Error reporting/logging */
303 rio_mport_write_config_32(mport, destid, hopcount, 290 rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
304 IDT_AUX_ERR_REPORT_EN, 0);
305 291
306 /* Disable Port-Write notification from JTAG */ 292 /* Disable Port-Write notification from JTAG */
307 rio_mport_write_config_32(mport, destid, hopcount, 293 rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
308 IDT_JTAG_CTRL, 0);
309 294
310 /* Disable Port-Write notification from I2C */ 295 /* Disable Port-Write notification from I2C */
311 rio_mport_read_config_32(mport, destid, hopcount, 296 rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval);
312 IDT_I2C_MCTRL, &regval); 297 rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
313 rio_mport_write_config_32(mport, destid, hopcount,
314 IDT_I2C_MCTRL,
315 regval & ~IDT_I2C_MCTRL_GENPW);
316 298
317 /* 299 /*
318 * Configure CFG_BLK error reporting. 300 * Configure CFG_BLK error reporting.
319 */ 301 */
320 302
321 /* Disable Configuration Block error capture */ 303 /* Disable Configuration Block error capture */
322 rio_mport_write_config_32(mport, destid, hopcount, 304 rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
323 IDT_CFGBLK_ERR_CAPTURE_EN, 0);
324 305
325 /* Disable Port-Writes for Configuration Block error reporting */ 306 /* Disable Port-Writes for Configuration Block error reporting */
326 rio_mport_read_config_32(mport, destid, hopcount, 307 rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval);
327 IDT_CFGBLK_ERR_REPORT, &regval); 308 rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
328 rio_mport_write_config_32(mport, destid, hopcount, 309 regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
329 IDT_CFGBLK_ERR_REPORT,
330 regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
331 310
332 /* set TVAL = ~50us */ 311 /* set TVAL = ~50us */
333 rio_mport_write_config_32(mport, destid, hopcount, 312 rio_write_config_32(rdev,
334 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); 313 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
335 314
336 return 0; 315 return 0;
@@ -339,18 +318,15 @@ idtg2_em_init(struct rio_dev *rdev)
339static int 318static int
340idtg2_em_handler(struct rio_dev *rdev, u8 portnum) 319idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
341{ 320{
342 struct rio_mport *mport = rdev->net->hport;
343 u16 destid = rdev->rswitch->destid;
344 u8 hopcount = rdev->rswitch->hopcount;
345 u32 regval, em_perrdet, em_ltlerrdet; 321 u32 regval, em_perrdet, em_ltlerrdet;
346 322
347 rio_mport_read_config_32(mport, destid, hopcount, 323 rio_read_config_32(rdev,
348 rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); 324 rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
349 if (em_ltlerrdet) { 325 if (em_ltlerrdet) {
350 /* Service Logical/Transport Layer Error(s) */ 326 /* Service Logical/Transport Layer Error(s) */
351 if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { 327 if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
352 /* Implementation specific error reported */ 328 /* Implementation specific error reported */
353 rio_mport_read_config_32(mport, destid, hopcount, 329 rio_read_config_32(rdev,
354 IDT_ISLTL_ADDRESS_CAP, &regval); 330 IDT_ISLTL_ADDRESS_CAP, &regval);
355 331
356 pr_debug("RIO: %s Implementation Specific LTL errors" \ 332 pr_debug("RIO: %s Implementation Specific LTL errors" \
@@ -358,13 +334,12 @@ idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
358 rio_name(rdev), em_ltlerrdet, regval); 334 rio_name(rdev), em_ltlerrdet, regval);
359 335
360 /* Clear implementation specific address capture CSR */ 336 /* Clear implementation specific address capture CSR */
361 rio_mport_write_config_32(mport, destid, hopcount, 337 rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
362 IDT_ISLTL_ADDRESS_CAP, 0);
363 338
364 } 339 }
365 } 340 }
366 341
367 rio_mport_read_config_32(mport, destid, hopcount, 342 rio_read_config_32(rdev,
368 rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); 343 rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
369 if (em_perrdet) { 344 if (em_perrdet) {
370 /* Service Port-Level Error(s) */ 345 /* Service Port-Level Error(s) */
@@ -372,14 +347,14 @@ idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
372 /* Implementation Specific port error reported */ 347 /* Implementation Specific port error reported */
373 348
374 /* Get IS errors reported */ 349 /* Get IS errors reported */
375 rio_mport_read_config_32(mport, destid, hopcount, 350 rio_read_config_32(rdev,
376 IDT_PORT_ISERR_DET(portnum), &regval); 351 IDT_PORT_ISERR_DET(portnum), &regval);
377 352
378 pr_debug("RIO: %s Implementation Specific Port" \ 353 pr_debug("RIO: %s Implementation Specific Port" \
379 " errors 0x%x\n", rio_name(rdev), regval); 354 " errors 0x%x\n", rio_name(rdev), regval);
380 355
381 /* Clear all implementation specific events */ 356 /* Clear all implementation specific events */
382 rio_mport_write_config_32(mport, destid, hopcount, 357 rio_write_config_32(rdev,
383 IDT_PORT_ISERR_DET(portnum), 0); 358 IDT_PORT_ISERR_DET(portnum), 0);
384 } 359 }
385 } 360 }
@@ -391,14 +366,10 @@ static ssize_t
391idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf) 366idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf)
392{ 367{
393 struct rio_dev *rdev = to_rio_dev(dev); 368 struct rio_dev *rdev = to_rio_dev(dev);
394 struct rio_mport *mport = rdev->net->hport;
395 u16 destid = rdev->rswitch->destid;
396 u8 hopcount = rdev->rswitch->hopcount;
397 ssize_t len = 0; 369 ssize_t len = 0;
398 u32 regval; 370 u32 regval;
399 371
400 while (!rio_mport_read_config_32(mport, destid, hopcount, 372 while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) {
401 IDT_ERR_RD, &regval)) {
402 if (!regval) /* 0 = end of log */ 373 if (!regval) /* 0 = end of log */
403 break; 374 break;
404 len += snprintf(buf + len, PAGE_SIZE - len, 375 len += snprintf(buf + len, PAGE_SIZE - len,
@@ -445,3 +416,5 @@ static int idtg2_switch_init(struct rio_dev *rdev, int do_enum)
445 416
446DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init); 417DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init);
447DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init); 418DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init);
419DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTVPS1616, idtg2_switch_init);
420DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTSPS1616, idtg2_switch_init);
diff --git a/drivers/rapidio/switches/idtcps.c b/drivers/rapidio/switches/idtcps.c
index fc9f6374f759..3a971077e7bf 100644
--- a/drivers/rapidio/switches/idtcps.c
+++ b/drivers/rapidio/switches/idtcps.c
@@ -117,10 +117,6 @@ idtcps_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
117 117
118static int idtcps_switch_init(struct rio_dev *rdev, int do_enum) 118static int idtcps_switch_init(struct rio_dev *rdev, int do_enum)
119{ 119{
120 struct rio_mport *mport = rdev->net->hport;
121 u16 destid = rdev->rswitch->destid;
122 u8 hopcount = rdev->rswitch->hopcount;
123
124 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); 120 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
125 rdev->rswitch->add_entry = idtcps_route_add_entry; 121 rdev->rswitch->add_entry = idtcps_route_add_entry;
126 rdev->rswitch->get_entry = idtcps_route_get_entry; 122 rdev->rswitch->get_entry = idtcps_route_get_entry;
@@ -132,7 +128,7 @@ static int idtcps_switch_init(struct rio_dev *rdev, int do_enum)
132 128
133 if (do_enum) { 129 if (do_enum) {
134 /* set TVAL = ~50us */ 130 /* set TVAL = ~50us */
135 rio_mport_write_config_32(mport, destid, hopcount, 131 rio_write_config_32(rdev,
136 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); 132 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
137 } 133 }
138 134
diff --git a/drivers/rapidio/switches/tsi568.c b/drivers/rapidio/switches/tsi568.c
index b9a389b9f812..3994c00aa01f 100644
--- a/drivers/rapidio/switches/tsi568.c
+++ b/drivers/rapidio/switches/tsi568.c
@@ -113,22 +113,17 @@ tsi568_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
113static int 113static int
114tsi568_em_init(struct rio_dev *rdev) 114tsi568_em_init(struct rio_dev *rdev)
115{ 115{
116 struct rio_mport *mport = rdev->net->hport;
117 u16 destid = rdev->rswitch->destid;
118 u8 hopcount = rdev->rswitch->hopcount;
119 u32 regval; 116 u32 regval;
120 int portnum; 117 int portnum;
121 118
122 pr_debug("TSI568 %s [%d:%d]\n", __func__, destid, hopcount); 119 pr_debug("TSI568 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
123 120
124 /* Make sure that Port-Writes are disabled (for all ports) */ 121 /* Make sure that Port-Writes are disabled (for all ports) */
125 for (portnum = 0; 122 for (portnum = 0;
126 portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) { 123 portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
127 rio_mport_read_config_32(mport, destid, hopcount, 124 rio_read_config_32(rdev, TSI568_SP_MODE(portnum), &regval);
128 TSI568_SP_MODE(portnum), &regval); 125 rio_write_config_32(rdev, TSI568_SP_MODE(portnum),
129 rio_mport_write_config_32(mport, destid, hopcount, 126 regval | TSI568_SP_MODE_PW_DIS);
130 TSI568_SP_MODE(portnum),
131 regval | TSI568_SP_MODE_PW_DIS);
132 } 127 }
133 128
134 return 0; 129 return 0;
diff --git a/drivers/rapidio/switches/tsi57x.c b/drivers/rapidio/switches/tsi57x.c
index 2003fb63c404..1a62934bfebc 100644
--- a/drivers/rapidio/switches/tsi57x.c
+++ b/drivers/rapidio/switches/tsi57x.c
@@ -158,48 +158,45 @@ tsi57x_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
158static int 158static int
159tsi57x_em_init(struct rio_dev *rdev) 159tsi57x_em_init(struct rio_dev *rdev)
160{ 160{
161 struct rio_mport *mport = rdev->net->hport;
162 u16 destid = rdev->rswitch->destid;
163 u8 hopcount = rdev->rswitch->hopcount;
164 u32 regval; 161 u32 regval;
165 int portnum; 162 int portnum;
166 163
167 pr_debug("TSI578 %s [%d:%d]\n", __func__, destid, hopcount); 164 pr_debug("TSI578 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
168 165
169 for (portnum = 0; 166 for (portnum = 0;
170 portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) { 167 portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
171 /* Make sure that Port-Writes are enabled (for all ports) */ 168 /* Make sure that Port-Writes are enabled (for all ports) */
172 rio_mport_read_config_32(mport, destid, hopcount, 169 rio_read_config_32(rdev,
173 TSI578_SP_MODE(portnum), &regval); 170 TSI578_SP_MODE(portnum), &regval);
174 rio_mport_write_config_32(mport, destid, hopcount, 171 rio_write_config_32(rdev,
175 TSI578_SP_MODE(portnum), 172 TSI578_SP_MODE(portnum),
176 regval & ~TSI578_SP_MODE_PW_DIS); 173 regval & ~TSI578_SP_MODE_PW_DIS);
177 174
178 /* Clear all pending interrupts */ 175 /* Clear all pending interrupts */
179 rio_mport_read_config_32(mport, destid, hopcount, 176 rio_read_config_32(rdev,
180 rdev->phys_efptr + 177 rdev->phys_efptr +
181 RIO_PORT_N_ERR_STS_CSR(portnum), 178 RIO_PORT_N_ERR_STS_CSR(portnum),
182 &regval); 179 &regval);
183 rio_mport_write_config_32(mport, destid, hopcount, 180 rio_write_config_32(rdev,
184 rdev->phys_efptr + 181 rdev->phys_efptr +
185 RIO_PORT_N_ERR_STS_CSR(portnum), 182 RIO_PORT_N_ERR_STS_CSR(portnum),
186 regval & 0x07120214); 183 regval & 0x07120214);
187 184
188 rio_mport_read_config_32(mport, destid, hopcount, 185 rio_read_config_32(rdev,
189 TSI578_SP_INT_STATUS(portnum), &regval); 186 TSI578_SP_INT_STATUS(portnum), &regval);
190 rio_mport_write_config_32(mport, destid, hopcount, 187 rio_write_config_32(rdev,
191 TSI578_SP_INT_STATUS(portnum), 188 TSI578_SP_INT_STATUS(portnum),
192 regval & 0x000700bd); 189 regval & 0x000700bd);
193 190
194 /* Enable all interrupts to allow ports to send a port-write */ 191 /* Enable all interrupts to allow ports to send a port-write */
195 rio_mport_read_config_32(mport, destid, hopcount, 192 rio_read_config_32(rdev,
196 TSI578_SP_CTL_INDEP(portnum), &regval); 193 TSI578_SP_CTL_INDEP(portnum), &regval);
197 rio_mport_write_config_32(mport, destid, hopcount, 194 rio_write_config_32(rdev,
198 TSI578_SP_CTL_INDEP(portnum), 195 TSI578_SP_CTL_INDEP(portnum),
199 regval | 0x000b0000); 196 regval | 0x000b0000);
200 197
201 /* Skip next (odd) port if the current port is in x4 mode */ 198 /* Skip next (odd) port if the current port is in x4 mode */
202 rio_mport_read_config_32(mport, destid, hopcount, 199 rio_read_config_32(rdev,
203 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 200 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
204 &regval); 201 &regval);
205 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4) 202 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
@@ -207,7 +204,7 @@ tsi57x_em_init(struct rio_dev *rdev)
207 } 204 }
208 205
209 /* set TVAL = ~50us */ 206 /* set TVAL = ~50us */
210 rio_mport_write_config_32(mport, destid, hopcount, 207 rio_write_config_32(rdev,
211 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x9a << 8); 208 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x9a << 8);
212 209
213 return 0; 210 return 0;
@@ -217,14 +214,12 @@ static int
217tsi57x_em_handler(struct rio_dev *rdev, u8 portnum) 214tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
218{ 215{
219 struct rio_mport *mport = rdev->net->hport; 216 struct rio_mport *mport = rdev->net->hport;
220 u16 destid = rdev->rswitch->destid;
221 u8 hopcount = rdev->rswitch->hopcount;
222 u32 intstat, err_status; 217 u32 intstat, err_status;
223 int sendcount, checkcount; 218 int sendcount, checkcount;
224 u8 route_port; 219 u8 route_port;
225 u32 regval; 220 u32 regval;
226 221
227 rio_mport_read_config_32(mport, destid, hopcount, 222 rio_read_config_32(rdev,
228 rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum), 223 rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
229 &err_status); 224 &err_status);
230 225
@@ -232,15 +227,15 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
232 (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES | 227 (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
233 RIO_PORT_N_ERR_STS_PW_INP_ES))) { 228 RIO_PORT_N_ERR_STS_PW_INP_ES))) {
234 /* Remove any queued packets by locking/unlocking port */ 229 /* Remove any queued packets by locking/unlocking port */
235 rio_mport_read_config_32(mport, destid, hopcount, 230 rio_read_config_32(rdev,
236 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 231 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
237 &regval); 232 &regval);
238 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) { 233 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
239 rio_mport_write_config_32(mport, destid, hopcount, 234 rio_write_config_32(rdev,
240 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 235 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
241 regval | RIO_PORT_N_CTL_LOCKOUT); 236 regval | RIO_PORT_N_CTL_LOCKOUT);
242 udelay(50); 237 udelay(50);
243 rio_mport_write_config_32(mport, destid, hopcount, 238 rio_write_config_32(rdev,
244 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 239 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
245 regval); 240 regval);
246 } 241 }
@@ -248,7 +243,7 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
248 /* Read from link maintenance response register to clear 243 /* Read from link maintenance response register to clear
249 * valid bit 244 * valid bit
250 */ 245 */
251 rio_mport_read_config_32(mport, destid, hopcount, 246 rio_read_config_32(rdev,
252 rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum), 247 rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
253 &regval); 248 &regval);
254 249
@@ -257,13 +252,12 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
257 */ 252 */
258 sendcount = 3; 253 sendcount = 3;
259 while (sendcount) { 254 while (sendcount) {
260 rio_mport_write_config_32(mport, destid, hopcount, 255 rio_write_config_32(rdev,
261 TSI578_SP_CS_TX(portnum), 0x40fc8000); 256 TSI578_SP_CS_TX(portnum), 0x40fc8000);
262 checkcount = 3; 257 checkcount = 3;
263 while (checkcount--) { 258 while (checkcount--) {
264 udelay(50); 259 udelay(50);
265 rio_mport_read_config_32( 260 rio_read_config_32(rdev,
266 mport, destid, hopcount,
267 rdev->phys_efptr + 261 rdev->phys_efptr +
268 RIO_PORT_N_MNT_RSP_CSR(portnum), 262 RIO_PORT_N_MNT_RSP_CSR(portnum),
269 &regval); 263 &regval);
@@ -277,25 +271,23 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
277 271
278exit_es: 272exit_es:
279 /* Clear implementation specific error status bits */ 273 /* Clear implementation specific error status bits */
280 rio_mport_read_config_32(mport, destid, hopcount, 274 rio_read_config_32(rdev, TSI578_SP_INT_STATUS(portnum), &intstat);
281 TSI578_SP_INT_STATUS(portnum), &intstat);
282 pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n", 275 pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
283 destid, hopcount, portnum, intstat); 276 rdev->destid, rdev->hopcount, portnum, intstat);
284 277
285 if (intstat & 0x10000) { 278 if (intstat & 0x10000) {
286 rio_mport_read_config_32(mport, destid, hopcount, 279 rio_read_config_32(rdev,
287 TSI578_SP_LUT_PEINF(portnum), &regval); 280 TSI578_SP_LUT_PEINF(portnum), &regval);
288 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24); 281 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
289 route_port = rdev->rswitch->route_table[regval]; 282 route_port = rdev->rswitch->route_table[regval];
290 pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n", 283 pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
291 rio_name(rdev), portnum, regval); 284 rio_name(rdev), portnum, regval);
292 tsi57x_route_add_entry(mport, destid, hopcount, 285 tsi57x_route_add_entry(mport, rdev->destid, rdev->hopcount,
293 RIO_GLOBAL_TABLE, regval, route_port); 286 RIO_GLOBAL_TABLE, regval, route_port);
294 } 287 }
295 288
296 rio_mport_write_config_32(mport, destid, hopcount, 289 rio_write_config_32(rdev, TSI578_SP_INT_STATUS(portnum),
297 TSI578_SP_INT_STATUS(portnum), 290 intstat & 0x000700bd);
298 intstat & 0x000700bd);
299 291
300 return 0; 292 return 0;
301} 293}