diff options
Diffstat (limited to 'drivers/rapidio/devices/tsi721.h')
-rw-r--r-- | drivers/rapidio/devices/tsi721.h | 105 |
1 files changed, 90 insertions, 15 deletions
diff --git a/drivers/rapidio/devices/tsi721.h b/drivers/rapidio/devices/tsi721.h index 1c226b31af13..59de9d7be346 100644 --- a/drivers/rapidio/devices/tsi721.h +++ b/drivers/rapidio/devices/tsi721.h | |||
@@ -167,6 +167,8 @@ | |||
167 | #define TSI721_DEV_INTE 0x29840 | 167 | #define TSI721_DEV_INTE 0x29840 |
168 | #define TSI721_DEV_INT 0x29844 | 168 | #define TSI721_DEV_INT 0x29844 |
169 | #define TSI721_DEV_INTSET 0x29848 | 169 | #define TSI721_DEV_INTSET 0x29848 |
170 | #define TSI721_DEV_INT_BDMA_CH 0x00002000 | ||
171 | #define TSI721_DEV_INT_BDMA_NCH 0x00001000 | ||
170 | #define TSI721_DEV_INT_SMSG_CH 0x00000800 | 172 | #define TSI721_DEV_INT_SMSG_CH 0x00000800 |
171 | #define TSI721_DEV_INT_SMSG_NCH 0x00000400 | 173 | #define TSI721_DEV_INT_SMSG_NCH 0x00000400 |
172 | #define TSI721_DEV_INT_SR2PC_CH 0x00000200 | 174 | #define TSI721_DEV_INT_SR2PC_CH 0x00000200 |
@@ -181,6 +183,8 @@ | |||
181 | #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x))) | 183 | #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x))) |
182 | #define TSI721_INT_OMSG_CHAN_M 0x0000ff00 | 184 | #define TSI721_INT_OMSG_CHAN_M 0x0000ff00 |
183 | #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x))) | 185 | #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x))) |
186 | #define TSI721_INT_BDMA_CHAN_M 0x000000ff | ||
187 | #define TSI721_INT_BDMA_CHAN(x) (1 << (x)) | ||
184 | 188 | ||
185 | /* | 189 | /* |
186 | * PC2SR block registers | 190 | * PC2SR block registers |
@@ -235,14 +239,16 @@ | |||
235 | * x = 0..7 | 239 | * x = 0..7 |
236 | */ | 240 | */ |
237 | 241 | ||
238 | #define TSI721_DMAC_DWRCNT(x) (0x51000 + (x) * 0x1000) | 242 | #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000) |
239 | #define TSI721_DMAC_DRDCNT(x) (0x51004 + (x) * 0x1000) | ||
240 | 243 | ||
241 | #define TSI721_DMAC_CTL(x) (0x51008 + (x) * 0x1000) | 244 | #define TSI721_DMAC_DWRCNT 0x000 |
245 | #define TSI721_DMAC_DRDCNT 0x004 | ||
246 | |||
247 | #define TSI721_DMAC_CTL 0x008 | ||
242 | #define TSI721_DMAC_CTL_SUSP 0x00000002 | 248 | #define TSI721_DMAC_CTL_SUSP 0x00000002 |
243 | #define TSI721_DMAC_CTL_INIT 0x00000001 | 249 | #define TSI721_DMAC_CTL_INIT 0x00000001 |
244 | 250 | ||
245 | #define TSI721_DMAC_INT(x) (0x5100c + (x) * 0x1000) | 251 | #define TSI721_DMAC_INT 0x00c |
246 | #define TSI721_DMAC_INT_STFULL 0x00000010 | 252 | #define TSI721_DMAC_INT_STFULL 0x00000010 |
247 | #define TSI721_DMAC_INT_DONE 0x00000008 | 253 | #define TSI721_DMAC_INT_DONE 0x00000008 |
248 | #define TSI721_DMAC_INT_SUSP 0x00000004 | 254 | #define TSI721_DMAC_INT_SUSP 0x00000004 |
@@ -250,34 +256,33 @@ | |||
250 | #define TSI721_DMAC_INT_IOFDONE 0x00000001 | 256 | #define TSI721_DMAC_INT_IOFDONE 0x00000001 |
251 | #define TSI721_DMAC_INT_ALL 0x0000001f | 257 | #define TSI721_DMAC_INT_ALL 0x0000001f |
252 | 258 | ||
253 | #define TSI721_DMAC_INTSET(x) (0x51010 + (x) * 0x1000) | 259 | #define TSI721_DMAC_INTSET 0x010 |
254 | 260 | ||
255 | #define TSI721_DMAC_STS(x) (0x51014 + (x) * 0x1000) | 261 | #define TSI721_DMAC_STS 0x014 |
256 | #define TSI721_DMAC_STS_ABORT 0x00400000 | 262 | #define TSI721_DMAC_STS_ABORT 0x00400000 |
257 | #define TSI721_DMAC_STS_RUN 0x00200000 | 263 | #define TSI721_DMAC_STS_RUN 0x00200000 |
258 | #define TSI721_DMAC_STS_CS 0x001f0000 | 264 | #define TSI721_DMAC_STS_CS 0x001f0000 |
259 | 265 | ||
260 | #define TSI721_DMAC_INTE(x) (0x51018 + (x) * 0x1000) | 266 | #define TSI721_DMAC_INTE 0x018 |
261 | 267 | ||
262 | #define TSI721_DMAC_DPTRL(x) (0x51024 + (x) * 0x1000) | 268 | #define TSI721_DMAC_DPTRL 0x024 |
263 | #define TSI721_DMAC_DPTRL_MASK 0xffffffe0 | 269 | #define TSI721_DMAC_DPTRL_MASK 0xffffffe0 |
264 | 270 | ||
265 | #define TSI721_DMAC_DPTRH(x) (0x51028 + (x) * 0x1000) | 271 | #define TSI721_DMAC_DPTRH 0x028 |
266 | 272 | ||
267 | #define TSI721_DMAC_DSBL(x) (0x5102c + (x) * 0x1000) | 273 | #define TSI721_DMAC_DSBL 0x02c |
268 | #define TSI721_DMAC_DSBL_MASK 0xffffffc0 | 274 | #define TSI721_DMAC_DSBL_MASK 0xffffffc0 |
269 | 275 | ||
270 | #define TSI721_DMAC_DSBH(x) (0x51030 + (x) * 0x1000) | 276 | #define TSI721_DMAC_DSBH 0x030 |
271 | 277 | ||
272 | #define TSI721_DMAC_DSSZ(x) (0x51034 + (x) * 0x1000) | 278 | #define TSI721_DMAC_DSSZ 0x034 |
273 | #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f | 279 | #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f |
274 | #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4) | 280 | #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4) |
275 | 281 | ||
276 | 282 | #define TSI721_DMAC_DSRP 0x038 | |
277 | #define TSI721_DMAC_DSRP(x) (0x51038 + (x) * 0x1000) | ||
278 | #define TSI721_DMAC_DSRP_MASK 0x0007ffff | 283 | #define TSI721_DMAC_DSRP_MASK 0x0007ffff |
279 | 284 | ||
280 | #define TSI721_DMAC_DSWP(x) (0x5103c + (x) * 0x1000) | 285 | #define TSI721_DMAC_DSWP 0x03c |
281 | #define TSI721_DMAC_DSWP_MASK 0x0007ffff | 286 | #define TSI721_DMAC_DSWP_MASK 0x0007ffff |
282 | 287 | ||
283 | #define TSI721_BDMA_INTE 0x5f000 | 288 | #define TSI721_BDMA_INTE 0x5f000 |
@@ -612,6 +617,8 @@ enum dma_rtype { | |||
612 | #define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */ | 617 | #define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */ |
613 | #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */ | 618 | #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */ |
614 | 619 | ||
620 | #define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */ | ||
621 | |||
615 | #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0) | 622 | #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0) |
616 | 623 | ||
617 | enum tsi721_smsg_int_flag { | 624 | enum tsi721_smsg_int_flag { |
@@ -626,7 +633,48 @@ enum tsi721_smsg_int_flag { | |||
626 | 633 | ||
627 | /* Structures */ | 634 | /* Structures */ |
628 | 635 | ||
636 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE | ||
637 | |||
638 | struct tsi721_tx_desc { | ||
639 | struct dma_async_tx_descriptor txd; | ||
640 | struct tsi721_dma_desc *hw_desc; | ||
641 | u16 destid; | ||
642 | /* low 64-bits of 66-bit RIO address */ | ||
643 | u64 rio_addr; | ||
644 | /* upper 2-bits of 66-bit RIO address */ | ||
645 | u8 rio_addr_u; | ||
646 | bool interrupt; | ||
647 | struct list_head desc_node; | ||
648 | struct list_head tx_list; | ||
649 | }; | ||
650 | |||
629 | struct tsi721_bdma_chan { | 651 | struct tsi721_bdma_chan { |
652 | int id; | ||
653 | void __iomem *regs; | ||
654 | int bd_num; /* number of buffer descriptors */ | ||
655 | void *bd_base; /* start of DMA descriptors */ | ||
656 | dma_addr_t bd_phys; | ||
657 | void *sts_base; /* start of DMA BD status FIFO */ | ||
658 | dma_addr_t sts_phys; | ||
659 | int sts_size; | ||
660 | u32 sts_rdptr; | ||
661 | u32 wr_count; | ||
662 | u32 wr_count_next; | ||
663 | |||
664 | struct dma_chan dchan; | ||
665 | struct tsi721_tx_desc *tx_desc; | ||
666 | spinlock_t lock; | ||
667 | struct list_head active_list; | ||
668 | struct list_head queue; | ||
669 | struct list_head free_list; | ||
670 | dma_cookie_t completed_cookie; | ||
671 | struct tasklet_struct tasklet; | ||
672 | }; | ||
673 | |||
674 | #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ | ||
675 | |||
676 | struct tsi721_bdma_maint { | ||
677 | int ch_id; /* BDMA channel number */ | ||
630 | int bd_num; /* number of buffer descriptors */ | 678 | int bd_num; /* number of buffer descriptors */ |
631 | void *bd_base; /* start of DMA descriptors */ | 679 | void *bd_base; /* start of DMA descriptors */ |
632 | dma_addr_t bd_phys; | 680 | dma_addr_t bd_phys; |
@@ -721,6 +769,24 @@ enum tsi721_msix_vect { | |||
721 | TSI721_VECT_IMB1_INT, | 769 | TSI721_VECT_IMB1_INT, |
722 | TSI721_VECT_IMB2_INT, | 770 | TSI721_VECT_IMB2_INT, |
723 | TSI721_VECT_IMB3_INT, | 771 | TSI721_VECT_IMB3_INT, |
772 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE | ||
773 | TSI721_VECT_DMA0_DONE, | ||
774 | TSI721_VECT_DMA1_DONE, | ||
775 | TSI721_VECT_DMA2_DONE, | ||
776 | TSI721_VECT_DMA3_DONE, | ||
777 | TSI721_VECT_DMA4_DONE, | ||
778 | TSI721_VECT_DMA5_DONE, | ||
779 | TSI721_VECT_DMA6_DONE, | ||
780 | TSI721_VECT_DMA7_DONE, | ||
781 | TSI721_VECT_DMA0_INT, | ||
782 | TSI721_VECT_DMA1_INT, | ||
783 | TSI721_VECT_DMA2_INT, | ||
784 | TSI721_VECT_DMA3_INT, | ||
785 | TSI721_VECT_DMA4_INT, | ||
786 | TSI721_VECT_DMA5_INT, | ||
787 | TSI721_VECT_DMA6_INT, | ||
788 | TSI721_VECT_DMA7_INT, | ||
789 | #endif /* CONFIG_RAPIDIO_DMA_ENGINE */ | ||
724 | TSI721_VECT_MAX | 790 | TSI721_VECT_MAX |
725 | }; | 791 | }; |
726 | 792 | ||
@@ -754,7 +820,11 @@ struct tsi721_device { | |||
754 | u32 pw_discard_count; | 820 | u32 pw_discard_count; |
755 | 821 | ||
756 | /* BDMA Engine */ | 822 | /* BDMA Engine */ |
823 | struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */ | ||
824 | |||
825 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE | ||
757 | struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM]; | 826 | struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM]; |
827 | #endif | ||
758 | 828 | ||
759 | /* Inbound Messaging */ | 829 | /* Inbound Messaging */ |
760 | int imsg_init[TSI721_IMSG_CHNUM]; | 830 | int imsg_init[TSI721_IMSG_CHNUM]; |
@@ -765,4 +835,9 @@ struct tsi721_device { | |||
765 | struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM]; | 835 | struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM]; |
766 | }; | 836 | }; |
767 | 837 | ||
838 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE | ||
839 | extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan); | ||
840 | extern int __devinit tsi721_register_dma(struct tsi721_device *priv); | ||
841 | #endif | ||
842 | |||
768 | #endif | 843 | #endif |