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path: root/drivers/rapidio/devices/tsi721.c
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Diffstat (limited to 'drivers/rapidio/devices/tsi721.c')
-rw-r--r--drivers/rapidio/devices/tsi721.c41
1 files changed, 21 insertions, 20 deletions
diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c
index 5225930a10cd..691b1ab1a3d0 100644
--- a/drivers/rapidio/devices/tsi721.c
+++ b/drivers/rapidio/devices/tsi721.c
@@ -851,14 +851,12 @@ static int tsi721_doorbell_init(struct tsi721_device *priv)
851 INIT_WORK(&priv->idb_work, tsi721_db_dpc); 851 INIT_WORK(&priv->idb_work, tsi721_db_dpc);
852 852
853 /* Allocate buffer for inbound doorbells queue */ 853 /* Allocate buffer for inbound doorbells queue */
854 priv->idb_base = dma_alloc_coherent(&priv->pdev->dev, 854 priv->idb_base = dma_zalloc_coherent(&priv->pdev->dev,
855 IDB_QSIZE * TSI721_IDB_ENTRY_SIZE, 855 IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
856 &priv->idb_dma, GFP_KERNEL); 856 &priv->idb_dma, GFP_KERNEL);
857 if (!priv->idb_base) 857 if (!priv->idb_base)
858 return -ENOMEM; 858 return -ENOMEM;
859 859
860 memset(priv->idb_base, 0, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE);
861
862 dev_dbg(&priv->pdev->dev, "Allocated IDB buffer @ %p (phys = %llx)\n", 860 dev_dbg(&priv->pdev->dev, "Allocated IDB buffer @ %p (phys = %llx)\n",
863 priv->idb_base, (unsigned long long)priv->idb_dma); 861 priv->idb_base, (unsigned long long)priv->idb_dma);
864 862
@@ -904,7 +902,7 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
904 */ 902 */
905 903
906 /* Allocate space for DMA descriptors */ 904 /* Allocate space for DMA descriptors */
907 bd_ptr = dma_alloc_coherent(&priv->pdev->dev, 905 bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
908 bd_num * sizeof(struct tsi721_dma_desc), 906 bd_num * sizeof(struct tsi721_dma_desc),
909 &bd_phys, GFP_KERNEL); 907 &bd_phys, GFP_KERNEL);
910 if (!bd_ptr) 908 if (!bd_ptr)
@@ -913,8 +911,6 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
913 priv->bdma[chnum].bd_phys = bd_phys; 911 priv->bdma[chnum].bd_phys = bd_phys;
914 priv->bdma[chnum].bd_base = bd_ptr; 912 priv->bdma[chnum].bd_base = bd_ptr;
915 913
916 memset(bd_ptr, 0, bd_num * sizeof(struct tsi721_dma_desc));
917
918 dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n", 914 dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
919 bd_ptr, (unsigned long long)bd_phys); 915 bd_ptr, (unsigned long long)bd_phys);
920 916
@@ -922,7 +918,7 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
922 sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ? 918 sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
923 bd_num : TSI721_DMA_MINSTSSZ; 919 bd_num : TSI721_DMA_MINSTSSZ;
924 sts_size = roundup_pow_of_two(sts_size); 920 sts_size = roundup_pow_of_two(sts_size);
925 sts_ptr = dma_alloc_coherent(&priv->pdev->dev, 921 sts_ptr = dma_zalloc_coherent(&priv->pdev->dev,
926 sts_size * sizeof(struct tsi721_dma_sts), 922 sts_size * sizeof(struct tsi721_dma_sts),
927 &sts_phys, GFP_KERNEL); 923 &sts_phys, GFP_KERNEL);
928 if (!sts_ptr) { 924 if (!sts_ptr) {
@@ -938,8 +934,6 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
938 priv->bdma[chnum].sts_base = sts_ptr; 934 priv->bdma[chnum].sts_base = sts_ptr;
939 priv->bdma[chnum].sts_size = sts_size; 935 priv->bdma[chnum].sts_size = sts_size;
940 936
941 memset(sts_ptr, 0, sts_size);
942
943 dev_dbg(&priv->pdev->dev, 937 dev_dbg(&priv->pdev->dev,
944 "desc status FIFO @ %p (phys = %llx) size=0x%x\n", 938 "desc status FIFO @ %p (phys = %llx) size=0x%x\n",
945 sts_ptr, (unsigned long long)sts_phys, sts_size); 939 sts_ptr, (unsigned long long)sts_phys, sts_size);
@@ -1400,7 +1394,7 @@ static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id,
1400 1394
1401 /* Outbound message descriptor status FIFO allocation */ 1395 /* Outbound message descriptor status FIFO allocation */
1402 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1); 1396 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1);
1403 priv->omsg_ring[mbox].sts_base = dma_alloc_coherent(&priv->pdev->dev, 1397 priv->omsg_ring[mbox].sts_base = dma_zalloc_coherent(&priv->pdev->dev,
1404 priv->omsg_ring[mbox].sts_size * 1398 priv->omsg_ring[mbox].sts_size *
1405 sizeof(struct tsi721_dma_sts), 1399 sizeof(struct tsi721_dma_sts),
1406 &priv->omsg_ring[mbox].sts_phys, GFP_KERNEL); 1400 &priv->omsg_ring[mbox].sts_phys, GFP_KERNEL);
@@ -1412,9 +1406,6 @@ static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id,
1412 goto out_desc; 1406 goto out_desc;
1413 } 1407 }
1414 1408
1415 memset(priv->omsg_ring[mbox].sts_base, 0,
1416 entries * sizeof(struct tsi721_dma_sts));
1417
1418 /* 1409 /*
1419 * Configure Outbound Messaging Engine 1410 * Configure Outbound Messaging Engine
1420 */ 1411 */
@@ -2116,8 +2107,8 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
2116 INIT_LIST_HEAD(&mport->dbells); 2107 INIT_LIST_HEAD(&mport->dbells);
2117 2108
2118 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 2109 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
2119 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 2110 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3);
2120 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 2111 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3);
2121 strcpy(mport->name, "Tsi721 mport"); 2112 strcpy(mport->name, "Tsi721 mport");
2122 2113
2123 /* Hook up interrupt handler */ 2114 /* Hook up interrupt handler */
@@ -2163,7 +2154,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
2163 const struct pci_device_id *id) 2154 const struct pci_device_id *id)
2164{ 2155{
2165 struct tsi721_device *priv; 2156 struct tsi721_device *priv;
2166 int i; 2157 int i, cap;
2167 int err; 2158 int err;
2168 u32 regval; 2159 u32 regval;
2169 2160
@@ -2271,10 +2262,20 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
2271 dev_info(&pdev->dev, "Unable to set consistent DMA mask\n"); 2262 dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2272 } 2263 }
2273 2264
2274 /* Clear "no snoop" and "relaxed ordering" bits. */ 2265 cap = pci_pcie_cap(pdev);
2275 pci_read_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, &regval); 2266 BUG_ON(cap == 0);
2276 regval &= ~(PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN); 2267
2277 pci_write_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, regval); 2268 /* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
2269 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &regval);
2270 regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
2271 PCI_EXP_DEVCTL_NOSNOOP_EN);
2272 regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
2273 pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
2274
2275 /* Adjust PCIe completion timeout. */
2276 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, &regval);
2277 regval &= ~(0x0f);
2278 pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
2278 2279
2279 /* 2280 /*
2280 * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block 2281 * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block