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-rw-r--r--drivers/pinctrl/Kconfig5
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-s3c24xx.c651
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c10
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c198
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c227
8 files changed, 1074 insertions, 26 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a1c6dd32e14b..901a388dbea7 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -217,6 +217,11 @@ config PINCTRL_EXYNOS5440
217 select PINMUX 217 select PINMUX
218 select PINCONF 218 select PINCONF
219 219
220config PINCTRL_S3C24XX
221 bool "Samsung S3C24XX SoC pinctrl driver"
222 depends on ARCH_S3C24XX
223 select PINCTRL_SAMSUNG
224
220config PINCTRL_S3C64XX 225config PINCTRL_S3C64XX
221 bool "Samsung S3C64XX SoC pinctrl driver" 226 bool "Samsung S3C64XX SoC pinctrl driver"
222 depends on ARCH_S3C64XX 227 depends on ARCH_S3C64XX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 9bdaeb8785ce..f90b645fb601 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
42obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o 42obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
43obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o 43obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
44obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o 44obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
45obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
45obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o 46obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
46obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 47obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
47obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 48obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/pinctrl-s3c24xx.c
new file mode 100644
index 000000000000..24446daaad7d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-s3c24xx.c
@@ -0,0 +1,651 @@
1/*
2 * S3C24XX specific support for Samsung pinctrl/gpiolib driver.
3 *
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This file contains the SamsungS3C24XX specific information required by the
12 * Samsung pinctrl/gpiolib driver. It also includes the implementation of
13 * external gpio and wakeup interrupt support.
14 */
15
16#include <linux/module.h>
17#include <linux/device.h>
18#include <linux/interrupt.h>
19#include <linux/irqdomain.h>
20#include <linux/irq.h>
21#include <linux/of_irq.h>
22#include <linux/irqchip/chained_irq.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/err.h>
26
27#include "pinctrl-samsung.h"
28
29#define NUM_EINT 24
30#define NUM_EINT_IRQ 6
31#define EINT_MAX_PER_GROUP 8
32
33#define EINTPEND_REG 0xa8
34#define EINTMASK_REG 0xa4
35
36#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
37#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
38#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
39
40#define EINT_LEVEL_LOW 0
41#define EINT_LEVEL_HIGH 1
42#define EINT_EDGE_FALLING 2
43#define EINT_EDGE_RISING 4
44#define EINT_EDGE_BOTH 6
45#define EINT_MASK 0xf
46
47static struct samsung_pin_bank_type bank_type_1bit = {
48 .fld_width = { 1, 1, },
49 .reg_offset = { 0x00, 0x04, },
50};
51
52static struct samsung_pin_bank_type bank_type_2bit = {
53 .fld_width = { 2, 1, 2, },
54 .reg_offset = { 0x00, 0x04, 0x08, },
55};
56
57#define PIN_BANK_A(pins, reg, id) \
58 { \
59 .type = &bank_type_1bit, \
60 .pctl_offset = reg, \
61 .nr_pins = pins, \
62 .eint_type = EINT_TYPE_NONE, \
63 .name = id \
64 }
65
66#define PIN_BANK_2BIT(pins, reg, id) \
67 { \
68 .type = &bank_type_2bit, \
69 .pctl_offset = reg, \
70 .nr_pins = pins, \
71 .eint_type = EINT_TYPE_NONE, \
72 .name = id \
73 }
74
75#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
76 { \
77 .type = &bank_type_2bit, \
78 .pctl_offset = reg, \
79 .nr_pins = pins, \
80 .eint_type = EINT_TYPE_WKUP, \
81 .eint_func = 2, \
82 .eint_mask = emask, \
83 .eint_offset = eoffs, \
84 .name = id \
85 }
86
87/**
88 * struct s3c24xx_eint_data: EINT common data
89 * @drvdata: pin controller driver data
90 * @domains: IRQ domains of particular EINT interrupts
91 * @parents: mapped parent irqs in the main interrupt controller
92 */
93struct s3c24xx_eint_data {
94 struct samsung_pinctrl_drv_data *drvdata;
95 struct irq_domain *domains[NUM_EINT];
96 int parents[NUM_EINT_IRQ];
97};
98
99/**
100 * struct s3c24xx_eint_domain_data: per irq-domain data
101 * @bank: pin bank related to the domain
102 * @eint_data: common data
103 * eint0_3_parent_only: live eints 0-3 only in the main intc
104 */
105struct s3c24xx_eint_domain_data {
106 struct samsung_pin_bank *bank;
107 struct s3c24xx_eint_data *eint_data;
108 bool eint0_3_parent_only;
109};
110
111static int s3c24xx_eint_get_trigger(unsigned int type)
112{
113 switch (type) {
114 case IRQ_TYPE_EDGE_RISING:
115 return EINT_EDGE_RISING;
116 break;
117 case IRQ_TYPE_EDGE_FALLING:
118 return EINT_EDGE_FALLING;
119 break;
120 case IRQ_TYPE_EDGE_BOTH:
121 return EINT_EDGE_BOTH;
122 break;
123 case IRQ_TYPE_LEVEL_HIGH:
124 return EINT_LEVEL_HIGH;
125 break;
126 case IRQ_TYPE_LEVEL_LOW:
127 return EINT_LEVEL_LOW;
128 break;
129 default:
130 return -EINVAL;
131 }
132}
133
134static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type)
135{
136 /* Edge- and level-triggered interrupts need different handlers */
137 if (type & IRQ_TYPE_EDGE_BOTH)
138 __irq_set_handler_locked(irq, handle_edge_irq);
139 else
140 __irq_set_handler_locked(irq, handle_level_irq);
141}
142
143static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
144 struct samsung_pin_bank *bank, int pin)
145{
146 struct samsung_pin_bank_type *bank_type = bank->type;
147 unsigned long flags;
148 void __iomem *reg;
149 u8 shift;
150 u32 mask;
151 u32 val;
152
153 /* Make sure that pin is configured as interrupt */
154 reg = d->virt_base + bank->pctl_offset;
155 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
156 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
157
158 spin_lock_irqsave(&bank->slock, flags);
159
160 val = readl(reg);
161 val &= ~(mask << shift);
162 val |= bank->eint_func << shift;
163 writel(val, reg);
164
165 spin_unlock_irqrestore(&bank->slock, flags);
166}
167
168static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
169{
170 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
171 struct samsung_pinctrl_drv_data *d = bank->drvdata;
172 int index = bank->eint_offset + data->hwirq;
173 void __iomem *reg;
174 int trigger;
175 u8 shift;
176 u32 val;
177
178 trigger = s3c24xx_eint_get_trigger(type);
179 if (trigger < 0) {
180 dev_err(d->dev, "unsupported external interrupt type\n");
181 return -EINVAL;
182 }
183
184 s3c24xx_eint_set_handler(data->irq, type);
185
186 /* Set up interrupt trigger */
187 reg = d->virt_base + EINT_REG(index);
188 shift = EINT_OFFS(index);
189
190 val = readl(reg);
191 val &= ~(EINT_MASK << shift);
192 val |= trigger << shift;
193 writel(val, reg);
194
195 s3c24xx_eint_set_function(d, bank, data->hwirq);
196
197 return 0;
198}
199
200/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
201
202static void s3c2410_eint0_3_ack(struct irq_data *data)
203{
204 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
205 struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
206 struct s3c24xx_eint_data *eint_data = ddata->eint_data;
207 int parent_irq = eint_data->parents[data->hwirq];
208 struct irq_chip *parent_chip = irq_get_chip(parent_irq);
209
210 parent_chip->irq_ack(irq_get_irq_data(parent_irq));
211}
212
213static void s3c2410_eint0_3_mask(struct irq_data *data)
214{
215 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
216 struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
217 struct s3c24xx_eint_data *eint_data = ddata->eint_data;
218 int parent_irq = eint_data->parents[data->hwirq];
219 struct irq_chip *parent_chip = irq_get_chip(parent_irq);
220
221 parent_chip->irq_mask(irq_get_irq_data(parent_irq));
222}
223
224static void s3c2410_eint0_3_unmask(struct irq_data *data)
225{
226 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
227 struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
228 struct s3c24xx_eint_data *eint_data = ddata->eint_data;
229 int parent_irq = eint_data->parents[data->hwirq];
230 struct irq_chip *parent_chip = irq_get_chip(parent_irq);
231
232 parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
233}
234
235static struct irq_chip s3c2410_eint0_3_chip = {
236 .name = "s3c2410-eint0_3",
237 .irq_ack = s3c2410_eint0_3_ack,
238 .irq_mask = s3c2410_eint0_3_mask,
239 .irq_unmask = s3c2410_eint0_3_unmask,
240 .irq_set_type = s3c24xx_eint_type,
241};
242
243static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
244{
245 struct irq_data *data = irq_desc_get_irq_data(desc);
246 struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
247 unsigned int virq;
248
249 /* the first 4 eints have a simple 1 to 1 mapping */
250 virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
251 /* Something must be really wrong if an unmapped EINT is unmasked */
252 BUG_ON(!virq);
253
254 generic_handle_irq(virq);
255}
256
257/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
258
259static void s3c2412_eint0_3_ack(struct irq_data *data)
260{
261 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
262 struct samsung_pinctrl_drv_data *d = bank->drvdata;
263
264 unsigned long bitval = 1UL << data->hwirq;
265 writel(bitval, d->virt_base + EINTPEND_REG);
266}
267
268static void s3c2412_eint0_3_mask(struct irq_data *data)
269{
270 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
271 struct samsung_pinctrl_drv_data *d = bank->drvdata;
272 unsigned long mask;
273
274 mask = readl(d->virt_base + EINTMASK_REG);
275 mask |= (1UL << data->hwirq);
276 writel(mask, d->virt_base + EINTMASK_REG);
277}
278
279static void s3c2412_eint0_3_unmask(struct irq_data *data)
280{
281 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
282 struct samsung_pinctrl_drv_data *d = bank->drvdata;
283 unsigned long mask;
284
285 mask = readl(d->virt_base + EINTMASK_REG);
286 mask &= ~(1UL << data->hwirq);
287 writel(mask, d->virt_base + EINTMASK_REG);
288}
289
290static struct irq_chip s3c2412_eint0_3_chip = {
291 .name = "s3c2412-eint0_3",
292 .irq_ack = s3c2412_eint0_3_ack,
293 .irq_mask = s3c2412_eint0_3_mask,
294 .irq_unmask = s3c2412_eint0_3_unmask,
295 .irq_set_type = s3c24xx_eint_type,
296};
297
298static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
299{
300 struct irq_chip *chip = irq_get_chip(irq);
301 struct irq_data *data = irq_desc_get_irq_data(desc);
302 struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq);
303 unsigned int virq;
304
305 chained_irq_enter(chip, desc);
306
307 /* the first 4 eints have a simple 1 to 1 mapping */
308 virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
309 /* Something must be really wrong if an unmapped EINT is unmasked */
310 BUG_ON(!virq);
311
312 generic_handle_irq(virq);
313
314 chained_irq_exit(chip, desc);
315}
316
317/* Handling of all other eints */
318
319static void s3c24xx_eint_ack(struct irq_data *data)
320{
321 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
322 struct samsung_pinctrl_drv_data *d = bank->drvdata;
323 unsigned char index = bank->eint_offset + data->hwirq;
324
325 writel(1UL << index, d->virt_base + EINTPEND_REG);
326}
327
328static void s3c24xx_eint_mask(struct irq_data *data)
329{
330 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
331 struct samsung_pinctrl_drv_data *d = bank->drvdata;
332 unsigned char index = bank->eint_offset + data->hwirq;
333 unsigned long mask;
334
335 mask = readl(d->virt_base + EINTMASK_REG);
336 mask |= (1UL << index);
337 writel(mask, d->virt_base + EINTMASK_REG);
338}
339
340static void s3c24xx_eint_unmask(struct irq_data *data)
341{
342 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
343 struct samsung_pinctrl_drv_data *d = bank->drvdata;
344 unsigned char index = bank->eint_offset + data->hwirq;
345 unsigned long mask;
346
347 mask = readl(d->virt_base + EINTMASK_REG);
348 mask &= ~(1UL << index);
349 writel(mask, d->virt_base + EINTMASK_REG);
350}
351
352static struct irq_chip s3c24xx_eint_chip = {
353 .name = "s3c-eint",
354 .irq_ack = s3c24xx_eint_ack,
355 .irq_mask = s3c24xx_eint_mask,
356 .irq_unmask = s3c24xx_eint_unmask,
357 .irq_set_type = s3c24xx_eint_type,
358};
359
360static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc,
361 u32 offset, u32 range)
362{
363 struct irq_chip *chip = irq_get_chip(irq);
364 struct s3c24xx_eint_data *data = irq_get_handler_data(irq);
365 struct samsung_pinctrl_drv_data *d = data->drvdata;
366 unsigned int pend, mask;
367
368 chained_irq_enter(chip, desc);
369
370 pend = readl(d->virt_base + EINTPEND_REG);
371 mask = readl(d->virt_base + EINTMASK_REG);
372
373 pend &= ~mask;
374 pend &= range;
375
376 while (pend) {
377 unsigned int virq;
378
379 irq = __ffs(pend);
380 pend &= ~(1 << irq);
381 virq = irq_linear_revmap(data->domains[irq], irq - offset);
382 /* Something is really wrong if an unmapped EINT is unmasked */
383 BUG_ON(!virq);
384
385 generic_handle_irq(virq);
386 }
387
388 chained_irq_exit(chip, desc);
389}
390
391static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc)
392{
393 s3c24xx_demux_eint(irq, desc, 0, 0xf0);
394}
395
396static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc)
397{
398 s3c24xx_demux_eint(irq, desc, 8, 0xffff00);
399}
400
401static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
402 s3c2410_demux_eint0_3,
403 s3c2410_demux_eint0_3,
404 s3c2410_demux_eint0_3,
405 s3c2410_demux_eint0_3,
406 s3c24xx_demux_eint4_7,
407 s3c24xx_demux_eint8_23,
408};
409
410static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
411 s3c2412_demux_eint0_3,
412 s3c2412_demux_eint0_3,
413 s3c2412_demux_eint0_3,
414 s3c2412_demux_eint0_3,
415 s3c24xx_demux_eint4_7,
416 s3c24xx_demux_eint8_23,
417};
418
419static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
420 irq_hw_number_t hw)
421{
422 struct s3c24xx_eint_domain_data *ddata = h->host_data;
423 struct samsung_pin_bank *bank = ddata->bank;
424
425 if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
426 return -EINVAL;
427
428 if (hw <= 3) {
429 if (ddata->eint0_3_parent_only)
430 irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
431 handle_edge_irq);
432 else
433 irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
434 handle_edge_irq);
435 } else {
436 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
437 handle_edge_irq);
438 }
439 irq_set_chip_data(virq, bank);
440 set_irq_flags(virq, IRQF_VALID);
441 return 0;
442}
443
444static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
445 .map = s3c24xx_gpf_irq_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
450 irq_hw_number_t hw)
451{
452 struct s3c24xx_eint_domain_data *ddata = h->host_data;
453 struct samsung_pin_bank *bank = ddata->bank;
454
455 if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
456 return -EINVAL;
457
458 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
459 irq_set_chip_data(virq, bank);
460 set_irq_flags(virq, IRQF_VALID);
461 return 0;
462}
463
464static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
465 .map = s3c24xx_gpg_irq_map,
466 .xlate = irq_domain_xlate_twocell,
467};
468
469static const struct of_device_id s3c24xx_eint_irq_ids[] = {
470 { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
471 { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
472 { }
473};
474
475static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
476{
477 struct device *dev = d->dev;
478 const struct of_device_id *match;
479 struct device_node *eint_np = NULL;
480 struct device_node *np;
481 struct samsung_pin_bank *bank;
482 struct s3c24xx_eint_data *eint_data;
483 const struct irq_domain_ops *ops;
484 unsigned int i;
485 bool eint0_3_parent_only;
486 irq_flow_handler_t *handlers;
487
488 for_each_child_of_node(dev->of_node, np) {
489 match = of_match_node(s3c24xx_eint_irq_ids, np);
490 if (match) {
491 eint_np = np;
492 eint0_3_parent_only = (bool)match->data;
493 break;
494 }
495 }
496 if (!eint_np)
497 return -ENODEV;
498
499 eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
500 if (!eint_data)
501 return -ENOMEM;
502
503 eint_data->drvdata = d;
504
505 handlers = eint0_3_parent_only ? s3c2410_eint_handlers
506 : s3c2412_eint_handlers;
507 for (i = 0; i < NUM_EINT_IRQ; ++i) {
508 unsigned int irq;
509
510 irq = irq_of_parse_and_map(eint_np, i);
511 if (!irq) {
512 dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
513 return -ENXIO;
514 }
515
516 eint_data->parents[i] = irq;
517 irq_set_chained_handler(irq, handlers[i]);
518 irq_set_handler_data(irq, eint_data);
519 }
520
521 bank = d->ctrl->pin_banks;
522 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
523 struct s3c24xx_eint_domain_data *ddata;
524 unsigned int mask;
525 unsigned int irq;
526 unsigned int pin;
527
528 if (bank->eint_type != EINT_TYPE_WKUP)
529 continue;
530
531 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
532 if (!ddata)
533 return -ENOMEM;
534
535 ddata->bank = bank;
536 ddata->eint_data = eint_data;
537 ddata->eint0_3_parent_only = eint0_3_parent_only;
538
539 ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
540 : &s3c24xx_gpg_irq_ops;
541
542 bank->irq_domain = irq_domain_add_linear(bank->of_node,
543 bank->nr_pins, ops, ddata);
544 if (!bank->irq_domain) {
545 dev_err(dev, "wkup irq domain add failed\n");
546 return -ENXIO;
547 }
548
549 irq = bank->eint_offset;
550 mask = bank->eint_mask;
551 for (pin = 0; mask; ++pin, mask >>= 1) {
552 if (irq > NUM_EINT)
553 break;
554 if (!(mask & 1))
555 continue;
556 eint_data->domains[irq] = bank->irq_domain;
557 ++irq;
558 }
559 }
560
561 return 0;
562}
563
564static struct samsung_pin_bank s3c2412_pin_banks[] = {
565 PIN_BANK_A(23, 0x000, "gpa"),
566 PIN_BANK_2BIT(11, 0x010, "gpb"),
567 PIN_BANK_2BIT(16, 0x020, "gpc"),
568 PIN_BANK_2BIT(16, 0x030, "gpd"),
569 PIN_BANK_2BIT(16, 0x040, "gpe"),
570 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
571 PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
572 PIN_BANK_2BIT(11, 0x070, "gph"),
573 PIN_BANK_2BIT(13, 0x080, "gpj"),
574};
575
576struct samsung_pin_ctrl s3c2412_pin_ctrl[] = {
577 {
578 .pin_banks = s3c2412_pin_banks,
579 .nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
580 .eint_wkup_init = s3c24xx_eint_init,
581 .label = "S3C2412-GPIO",
582 },
583};
584
585static struct samsung_pin_bank s3c2416_pin_banks[] = {
586 PIN_BANK_A(27, 0x000, "gpa"),
587 PIN_BANK_2BIT(11, 0x010, "gpb"),
588 PIN_BANK_2BIT(16, 0x020, "gpc"),
589 PIN_BANK_2BIT(16, 0x030, "gpd"),
590 PIN_BANK_2BIT(16, 0x040, "gpe"),
591 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
592 PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
593 PIN_BANK_2BIT(15, 0x070, "gph"),
594 PIN_BANK_2BIT(16, 0x0e0, "gpk"),
595 PIN_BANK_2BIT(14, 0x0f0, "gpl"),
596 PIN_BANK_2BIT(2, 0x100, "gpm"),
597};
598
599struct samsung_pin_ctrl s3c2416_pin_ctrl[] = {
600 {
601 .pin_banks = s3c2416_pin_banks,
602 .nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
603 .eint_wkup_init = s3c24xx_eint_init,
604 .label = "S3C2416-GPIO",
605 },
606};
607
608static struct samsung_pin_bank s3c2440_pin_banks[] = {
609 PIN_BANK_A(25, 0x000, "gpa"),
610 PIN_BANK_2BIT(11, 0x010, "gpb"),
611 PIN_BANK_2BIT(16, 0x020, "gpc"),
612 PIN_BANK_2BIT(16, 0x030, "gpd"),
613 PIN_BANK_2BIT(16, 0x040, "gpe"),
614 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
615 PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
616 PIN_BANK_2BIT(11, 0x070, "gph"),
617 PIN_BANK_2BIT(13, 0x0d0, "gpj"),
618};
619
620struct samsung_pin_ctrl s3c2440_pin_ctrl[] = {
621 {
622 .pin_banks = s3c2440_pin_banks,
623 .nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
624 .eint_wkup_init = s3c24xx_eint_init,
625 .label = "S3C2440-GPIO",
626 },
627};
628
629static struct samsung_pin_bank s3c2450_pin_banks[] = {
630 PIN_BANK_A(28, 0x000, "gpa"),
631 PIN_BANK_2BIT(11, 0x010, "gpb"),
632 PIN_BANK_2BIT(16, 0x020, "gpc"),
633 PIN_BANK_2BIT(16, 0x030, "gpd"),
634 PIN_BANK_2BIT(16, 0x040, "gpe"),
635 PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
636 PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
637 PIN_BANK_2BIT(15, 0x070, "gph"),
638 PIN_BANK_2BIT(16, 0x0d0, "gpj"),
639 PIN_BANK_2BIT(16, 0x0e0, "gpk"),
640 PIN_BANK_2BIT(15, 0x0f0, "gpl"),
641 PIN_BANK_2BIT(2, 0x100, "gpm"),
642};
643
644struct samsung_pin_ctrl s3c2450_pin_ctrl[] = {
645 {
646 .pin_banks = s3c2450_pin_banks,
647 .nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
648 .eint_wkup_init = s3c24xx_eint_init,
649 .label = "S3C2450-GPIO",
650 },
651};
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 63ac22e89678..e67ff1b8042c 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1118,6 +1118,16 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
1118 { .compatible = "samsung,s3c64xx-pinctrl", 1118 { .compatible = "samsung,s3c64xx-pinctrl",
1119 .data = s3c64xx_pin_ctrl }, 1119 .data = s3c64xx_pin_ctrl },
1120#endif 1120#endif
1121#ifdef CONFIG_PINCTRL_S3C24XX
1122 { .compatible = "samsung,s3c2412-pinctrl",
1123 .data = s3c2412_pin_ctrl },
1124 { .compatible = "samsung,s3c2416-pinctrl",
1125 .data = s3c2416_pin_ctrl },
1126 { .compatible = "samsung,s3c2440-pinctrl",
1127 .data = s3c2440_pin_ctrl },
1128 { .compatible = "samsung,s3c2450-pinctrl",
1129 .data = s3c2450_pin_ctrl },
1130#endif
1121 {}, 1131 {},
1122}; 1132};
1123MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); 1133MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 26d3519240c9..79fcc2076c00 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -255,5 +255,9 @@ extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
257extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 257extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
258extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
259extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
260extern struct samsung_pin_ctrl s3c2440_pin_ctrl[];
261extern struct samsung_pin_ctrl s3c2450_pin_ctrl[];
258 262
259#endif /* __PINCTRL_SAMSUNG_H */ 263#endif /* __PINCTRL_SAMSUNG_H */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index bbff5596e922..82bf6aba0074 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1488,6 +1488,66 @@ IRQC_PINS_MUX(326, 54);
1488IRQC_PINS_MUX(327, 55); 1488IRQC_PINS_MUX(327, 55);
1489IRQC_PINS_MUX(328, 56); 1489IRQC_PINS_MUX(328, 56);
1490IRQC_PINS_MUX(329, 57); 1490IRQC_PINS_MUX(329, 57);
1491/* - MMCIF0 ----------------------------------------------------------------- */
1492static const unsigned int mmc0_data1_pins[] = {
1493 /* D[0] */
1494 164,
1495};
1496static const unsigned int mmc0_data1_mux[] = {
1497 MMCD0_0_MARK,
1498};
1499static const unsigned int mmc0_data4_pins[] = {
1500 /* D[0:3] */
1501 164, 165, 166, 167,
1502};
1503static const unsigned int mmc0_data4_mux[] = {
1504 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1505};
1506static const unsigned int mmc0_data8_pins[] = {
1507 /* D[0:7] */
1508 164, 165, 166, 167, 168, 169, 170, 171,
1509};
1510static const unsigned int mmc0_data8_mux[] = {
1511 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1512 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1513};
1514static const unsigned int mmc0_ctrl_pins[] = {
1515 /* CMD, CLK */
1516 172, 173,
1517};
1518static const unsigned int mmc0_ctrl_mux[] = {
1519 MMCCMD0_MARK, MMCCLK0_MARK,
1520};
1521/* - MMCIF1 ----------------------------------------------------------------- */
1522static const unsigned int mmc1_data1_pins[] = {
1523 /* D[0] */
1524 199,
1525};
1526static const unsigned int mmc1_data1_mux[] = {
1527 MMCD1_0_MARK,
1528};
1529static const unsigned int mmc1_data4_pins[] = {
1530 /* D[0:3] */
1531 199, 198, 197, 196,
1532};
1533static const unsigned int mmc1_data4_mux[] = {
1534 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1535};
1536static const unsigned int mmc1_data8_pins[] = {
1537 /* D[0:7] */
1538 199, 198, 197, 196, 195, 194, 193, 192,
1539};
1540static const unsigned int mmc1_data8_mux[] = {
1541 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1542 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1543};
1544static const unsigned int mmc1_ctrl_pins[] = {
1545 /* CMD, CLK */
1546 200, 203,
1547};
1548static const unsigned int mmc1_ctrl_mux[] = {
1549 MMCCMD1_MARK, MMCCLK1_MARK,
1550};
1491/* - SCIFA0 ----------------------------------------------------------------- */ 1551/* - SCIFA0 ----------------------------------------------------------------- */
1492static const unsigned int scifa0_data_pins[] = { 1552static const unsigned int scifa0_data_pins[] = {
1493 /* SCIFA0_RXD, SCIFA0_TXD */ 1553 /* SCIFA0_RXD, SCIFA0_TXD */
@@ -1683,6 +1743,86 @@ static const unsigned int scifb3_ctrl_b_pins[] = {
1683static const unsigned int scifb3_ctrl_b_mux[] = { 1743static const unsigned int scifb3_ctrl_b_mux[] = {
1684 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, 1744 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1685}; 1745};
1746/* - SDHI0 ------------------------------------------------------------------ */
1747static const unsigned int sdhi0_data1_pins[] = {
1748 /* D0 */
1749 302,
1750};
1751static const unsigned int sdhi0_data1_mux[] = {
1752 SDHID0_0_MARK,
1753};
1754static const unsigned int sdhi0_data4_pins[] = {
1755 /* D[0:3] */
1756 302, 303, 304, 305,
1757};
1758static const unsigned int sdhi0_data4_mux[] = {
1759 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1760};
1761static const unsigned int sdhi0_ctrl_pins[] = {
1762 /* CLK, CMD */
1763 308, 306,
1764};
1765static const unsigned int sdhi0_ctrl_mux[] = {
1766 SDHICLK0_MARK, SDHICMD0_MARK,
1767};
1768static const unsigned int sdhi0_cd_pins[] = {
1769 /* CD */
1770 301,
1771};
1772static const unsigned int sdhi0_cd_mux[] = {
1773 SDHICD0_MARK,
1774};
1775static const unsigned int sdhi0_wp_pins[] = {
1776 /* WP */
1777 307,
1778};
1779static const unsigned int sdhi0_wp_mux[] = {
1780 SDHIWP0_MARK,
1781};
1782/* - SDHI1 ------------------------------------------------------------------ */
1783static const unsigned int sdhi1_data1_pins[] = {
1784 /* D0 */
1785 289,
1786};
1787static const unsigned int sdhi1_data1_mux[] = {
1788 SDHID1_0_MARK,
1789};
1790static const unsigned int sdhi1_data4_pins[] = {
1791 /* D[0:3] */
1792 289, 290, 291, 292,
1793};
1794static const unsigned int sdhi1_data4_mux[] = {
1795 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1796};
1797static const unsigned int sdhi1_ctrl_pins[] = {
1798 /* CLK, CMD */
1799 293, 294,
1800};
1801static const unsigned int sdhi1_ctrl_mux[] = {
1802 SDHICLK1_MARK, SDHICMD1_MARK,
1803};
1804/* - SDHI2 ------------------------------------------------------------------ */
1805static const unsigned int sdhi2_data1_pins[] = {
1806 /* D0 */
1807 295,
1808};
1809static const unsigned int sdhi2_data1_mux[] = {
1810 SDHID2_0_MARK,
1811};
1812static const unsigned int sdhi2_data4_pins[] = {
1813 /* D[0:3] */
1814 295, 296, 297, 298,
1815};
1816static const unsigned int sdhi2_data4_mux[] = {
1817 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1818};
1819static const unsigned int sdhi2_ctrl_pins[] = {
1820 /* CLK, CMD */
1821 299, 300,
1822};
1823static const unsigned int sdhi2_ctrl_mux[] = {
1824 SDHICLK2_MARK, SDHICMD2_MARK,
1825};
1686 1826
1687static const struct sh_pfc_pin_group pinmux_groups[] = { 1827static const struct sh_pfc_pin_group pinmux_groups[] = {
1688 SH_PFC_PIN_GROUP(irqc_irq0), 1828 SH_PFC_PIN_GROUP(irqc_irq0),
@@ -1743,6 +1883,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1743 SH_PFC_PIN_GROUP(irqc_irq55), 1883 SH_PFC_PIN_GROUP(irqc_irq55),
1744 SH_PFC_PIN_GROUP(irqc_irq56), 1884 SH_PFC_PIN_GROUP(irqc_irq56),
1745 SH_PFC_PIN_GROUP(irqc_irq57), 1885 SH_PFC_PIN_GROUP(irqc_irq57),
1886 SH_PFC_PIN_GROUP(mmc0_data1),
1887 SH_PFC_PIN_GROUP(mmc0_data4),
1888 SH_PFC_PIN_GROUP(mmc0_data8),
1889 SH_PFC_PIN_GROUP(mmc0_ctrl),
1890 SH_PFC_PIN_GROUP(mmc1_data1),
1891 SH_PFC_PIN_GROUP(mmc1_data4),
1892 SH_PFC_PIN_GROUP(mmc1_data8),
1893 SH_PFC_PIN_GROUP(mmc1_ctrl),
1746 SH_PFC_PIN_GROUP(scifa0_data), 1894 SH_PFC_PIN_GROUP(scifa0_data),
1747 SH_PFC_PIN_GROUP(scifa0_clk), 1895 SH_PFC_PIN_GROUP(scifa0_clk),
1748 SH_PFC_PIN_GROUP(scifa0_ctrl), 1896 SH_PFC_PIN_GROUP(scifa0_ctrl),
@@ -1770,6 +1918,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1770 SH_PFC_PIN_GROUP(scifb3_data_b), 1918 SH_PFC_PIN_GROUP(scifb3_data_b),
1771 SH_PFC_PIN_GROUP(scifb3_clk_b), 1919 SH_PFC_PIN_GROUP(scifb3_clk_b),
1772 SH_PFC_PIN_GROUP(scifb3_ctrl_b), 1920 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1921 SH_PFC_PIN_GROUP(sdhi0_data1),
1922 SH_PFC_PIN_GROUP(sdhi0_data4),
1923 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1924 SH_PFC_PIN_GROUP(sdhi0_cd),
1925 SH_PFC_PIN_GROUP(sdhi0_wp),
1926 SH_PFC_PIN_GROUP(sdhi1_data1),
1927 SH_PFC_PIN_GROUP(sdhi1_data4),
1928 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1929 SH_PFC_PIN_GROUP(sdhi2_data1),
1930 SH_PFC_PIN_GROUP(sdhi2_data4),
1931 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1773}; 1932};
1774 1933
1775static const char * const irqc_groups[] = { 1934static const char * const irqc_groups[] = {
@@ -1833,6 +1992,20 @@ static const char * const irqc_groups[] = {
1833 "irqc_irq57", 1992 "irqc_irq57",
1834}; 1993};
1835 1994
1995static const char * const mmc0_groups[] = {
1996 "mmc0_data1",
1997 "mmc0_data4",
1998 "mmc0_data8",
1999 "mmc0_ctrl",
2000};
2001
2002static const char * const mmc1_groups[] = {
2003 "mmc1_data1",
2004 "mmc1_data4",
2005 "mmc1_data8",
2006 "mmc1_ctrl",
2007};
2008
1836static const char * const scifa0_groups[] = { 2009static const char * const scifa0_groups[] = {
1837 "scifa0_data", 2010 "scifa0_data",
1838 "scifa0_clk", 2011 "scifa0_clk",
@@ -1878,14 +2051,39 @@ static const char * const scifb3_groups[] = {
1878 "scifb3_ctrl_b", 2051 "scifb3_ctrl_b",
1879}; 2052};
1880 2053
2054static const char * const sdhi0_groups[] = {
2055 "sdhi0_data1",
2056 "sdhi0_data4",
2057 "sdhi0_ctrl",
2058 "sdhi0_cd",
2059 "sdhi0_wp",
2060};
2061
2062static const char * const sdhi1_groups[] = {
2063 "sdhi1_data1",
2064 "sdhi1_data4",
2065 "sdhi1_ctrl",
2066};
2067
2068static const char * const sdhi2_groups[] = {
2069 "sdhi2_data1",
2070 "sdhi2_data4",
2071 "sdhi2_ctrl",
2072};
2073
1881static const struct sh_pfc_function pinmux_functions[] = { 2074static const struct sh_pfc_function pinmux_functions[] = {
1882 SH_PFC_FUNCTION(irqc), 2075 SH_PFC_FUNCTION(irqc),
2076 SH_PFC_FUNCTION(mmc0),
2077 SH_PFC_FUNCTION(mmc1),
1883 SH_PFC_FUNCTION(scifa0), 2078 SH_PFC_FUNCTION(scifa0),
1884 SH_PFC_FUNCTION(scifa1), 2079 SH_PFC_FUNCTION(scifa1),
1885 SH_PFC_FUNCTION(scifb0), 2080 SH_PFC_FUNCTION(scifb0),
1886 SH_PFC_FUNCTION(scifb1), 2081 SH_PFC_FUNCTION(scifb1),
1887 SH_PFC_FUNCTION(scifb2), 2082 SH_PFC_FUNCTION(scifb2),
1888 SH_PFC_FUNCTION(scifb3), 2083 SH_PFC_FUNCTION(scifb3),
2084 SH_PFC_FUNCTION(sdhi0),
2085 SH_PFC_FUNCTION(sdhi1),
2086 SH_PFC_FUNCTION(sdhi2),
1889}; 2087};
1890 2088
1891#undef PORTCR 2089#undef PORTCR
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 1dcbabcd7b3c..f9039102bb43 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1447,11 +1447,11 @@ MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
1447MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); 1447MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
1448MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); 1448MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
1449MMC_PFC_DAT1(mmc_data1, MMC_D0); 1449MMC_PFC_DAT1(mmc_data1, MMC_D0);
1450MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), 1450MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
1451 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); 1451 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
1452MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, 1452MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
1453 MMC_D2, MMC_D3); 1453 MMC_D2, MMC_D3);
1454MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), 1454MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
1455 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 1455 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1456 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), 1456 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1457 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); 1457 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 85d77a417c0e..14f3ec267e1f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1979,6 +1979,141 @@ static const unsigned int scif1_clk_e_pins[] = {
1979static const unsigned int scif1_clk_e_mux[] = { 1979static const unsigned int scif1_clk_e_mux[] = {
1980 SCK1_E_MARK, 1980 SCK1_E_MARK,
1981}; 1981};
1982/* - HSCIF0 ----------------------------------------------------------------- */
1983static const unsigned int hscif0_data_pins[] = {
1984 /* RX, TX */
1985 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1986};
1987static const unsigned int hscif0_data_mux[] = {
1988 HRX0_MARK, HTX0_MARK,
1989};
1990static const unsigned int hscif0_clk_pins[] = {
1991 /* SCK */
1992 RCAR_GP_PIN(5, 7),
1993};
1994static const unsigned int hscif0_clk_mux[] = {
1995 HSCK0_MARK,
1996};
1997static const unsigned int hscif0_ctrl_pins[] = {
1998 /* RTS, CTS */
1999 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2000};
2001static const unsigned int hscif0_ctrl_mux[] = {
2002 HRTS0_N_MARK, HCTS0_N_MARK,
2003};
2004static const unsigned int hscif0_data_b_pins[] = {
2005 /* RX, TX */
2006 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2007};
2008static const unsigned int hscif0_data_b_mux[] = {
2009 HRX0_B_MARK, HTX0_B_MARK,
2010};
2011static const unsigned int hscif0_ctrl_b_pins[] = {
2012 /* RTS, CTS */
2013 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2014};
2015static const unsigned int hscif0_ctrl_b_mux[] = {
2016 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2017};
2018static const unsigned int hscif0_data_c_pins[] = {
2019 /* RX, TX */
2020 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2021};
2022static const unsigned int hscif0_data_c_mux[] = {
2023 HRX0_C_MARK, HTX0_C_MARK,
2024};
2025static const unsigned int hscif0_ctrl_c_pins[] = {
2026 /* RTS, CTS */
2027 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2028};
2029static const unsigned int hscif0_ctrl_c_mux[] = {
2030 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2031};
2032static const unsigned int hscif0_data_d_pins[] = {
2033 /* RX, TX */
2034 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2035};
2036static const unsigned int hscif0_data_d_mux[] = {
2037 HRX0_D_MARK, HTX0_D_MARK,
2038};
2039static const unsigned int hscif0_ctrl_d_pins[] = {
2040 /* RTS, CTS */
2041 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2042};
2043static const unsigned int hscif0_ctrl_d_mux[] = {
2044 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2045};
2046static const unsigned int hscif0_data_e_pins[] = {
2047 /* RX, TX */
2048 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2049};
2050static const unsigned int hscif0_data_e_mux[] = {
2051 HRX0_E_MARK, HTX0_E_MARK,
2052};
2053static const unsigned int hscif0_ctrl_e_pins[] = {
2054 /* RTS, CTS */
2055 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2056};
2057static const unsigned int hscif0_ctrl_e_mux[] = {
2058 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2059};
2060static const unsigned int hscif0_data_f_pins[] = {
2061 /* RX, TX */
2062 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2063};
2064static const unsigned int hscif0_data_f_mux[] = {
2065 HRX0_F_MARK, HTX0_F_MARK,
2066};
2067static const unsigned int hscif0_ctrl_f_pins[] = {
2068 /* RTS, CTS */
2069 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2070};
2071static const unsigned int hscif0_ctrl_f_mux[] = {
2072 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2073};
2074/* - HSCIF1 ----------------------------------------------------------------- */
2075static const unsigned int hscif1_data_pins[] = {
2076 /* RX, TX */
2077 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2078};
2079static const unsigned int hscif1_data_mux[] = {
2080 HRX1_MARK, HTX1_MARK,
2081};
2082static const unsigned int hscif1_clk_pins[] = {
2083 /* SCK */
2084 RCAR_GP_PIN(4, 27),
2085};
2086static const unsigned int hscif1_clk_mux[] = {
2087 HSCK1_MARK,
2088};
2089static const unsigned int hscif1_ctrl_pins[] = {
2090 /* RTS, CTS */
2091 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2092};
2093static const unsigned int hscif1_ctrl_mux[] = {
2094 HRTS1_N_MARK, HCTS1_N_MARK,
2095};
2096static const unsigned int hscif1_data_b_pins[] = {
2097 /* RX, TX */
2098 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2099};
2100static const unsigned int hscif1_data_b_mux[] = {
2101 HRX1_B_MARK, HTX1_B_MARK,
2102};
2103static const unsigned int hscif1_clk_b_pins[] = {
2104 /* SCK */
2105 RCAR_GP_PIN(1, 28),
2106};
2107static const unsigned int hscif1_clk_b_mux[] = {
2108 HSCK1_B_MARK,
2109};
2110static const unsigned int hscif1_ctrl_b_pins[] = {
2111 /* RTS, CTS */
2112 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2113};
2114static const unsigned int hscif1_ctrl_b_mux[] = {
2115 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2116};
1982/* - SCIFA0 ----------------------------------------------------------------- */ 2117/* - SCIFA0 ----------------------------------------------------------------- */
1983static const unsigned int scifa0_data_pins[] = { 2118static const unsigned int scifa0_data_pins[] = {
1984 /* RXD, TXD */ 2119 /* RXD, TXD */
@@ -2371,8 +2506,7 @@ static const unsigned int tpu0_to3_pins[] = {
2371static const unsigned int tpu0_to3_mux[] = { 2506static const unsigned int tpu0_to3_mux[] = {
2372 TPU0TO3_MARK, 2507 TPU0TO3_MARK,
2373}; 2508};
2374 2509/* - MMCIF0 ----------------------------------------------------------------- */
2375/* - MMCIF ------------------------------------------------------------------ */
2376static const unsigned int mmc0_data1_pins[] = { 2510static const unsigned int mmc0_data1_pins[] = {
2377 /* D[0] */ 2511 /* D[0] */
2378 RCAR_GP_PIN(3, 18), 2512 RCAR_GP_PIN(3, 18),
@@ -2406,7 +2540,7 @@ static const unsigned int mmc0_ctrl_pins[] = {
2406static const unsigned int mmc0_ctrl_mux[] = { 2540static const unsigned int mmc0_ctrl_mux[] = {
2407 MMC0_CLK_MARK, MMC0_CMD_MARK, 2541 MMC0_CLK_MARK, MMC0_CMD_MARK,
2408}; 2542};
2409 2543/* - MMCIF1 ----------------------------------------------------------------- */
2410static const unsigned int mmc1_data1_pins[] = { 2544static const unsigned int mmc1_data1_pins[] = {
2411 /* D[0] */ 2545 /* D[0] */
2412 RCAR_GP_PIN(3, 26), 2546 RCAR_GP_PIN(3, 26),
@@ -2427,7 +2561,7 @@ static const unsigned int mmc1_data8_pins[] = {
2427 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2561 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2428 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2562 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2429 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2563 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2430 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 2564 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2431}; 2565};
2432static const unsigned int mmc1_data8_mux[] = { 2566static const unsigned int mmc1_data8_mux[] = {
2433 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2567 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -2440,8 +2574,7 @@ static const unsigned int mmc1_ctrl_pins[] = {
2440static const unsigned int mmc1_ctrl_mux[] = { 2574static const unsigned int mmc1_ctrl_mux[] = {
2441 MMC1_CLK_MARK, MMC1_CMD_MARK, 2575 MMC1_CLK_MARK, MMC1_CMD_MARK,
2442}; 2576};
2443 2577/* - SDHI0 ------------------------------------------------------------------ */
2444/* - SDHI ------------------------------------------------------------------- */
2445static const unsigned int sdhi0_data1_pins[] = { 2578static const unsigned int sdhi0_data1_pins[] = {
2446 /* D0 */ 2579 /* D0 */
2447 RCAR_GP_PIN(3, 2), 2580 RCAR_GP_PIN(3, 2),
@@ -2477,7 +2610,7 @@ static const unsigned int sdhi0_wp_pins[] = {
2477static const unsigned int sdhi0_wp_mux[] = { 2610static const unsigned int sdhi0_wp_mux[] = {
2478 SD0_WP_MARK, 2611 SD0_WP_MARK,
2479}; 2612};
2480 2613/* - SDHI1 ------------------------------------------------------------------ */
2481static const unsigned int sdhi1_data1_pins[] = { 2614static const unsigned int sdhi1_data1_pins[] = {
2482 /* D0 */ 2615 /* D0 */
2483 RCAR_GP_PIN(3, 10), 2616 RCAR_GP_PIN(3, 10),
@@ -2513,7 +2646,7 @@ static const unsigned int sdhi1_wp_pins[] = {
2513static const unsigned int sdhi1_wp_mux[] = { 2646static const unsigned int sdhi1_wp_mux[] = {
2514 SD1_WP_MARK, 2647 SD1_WP_MARK,
2515}; 2648};
2516 2649/* - SDHI2 ------------------------------------------------------------------ */
2517static const unsigned int sdhi2_data1_pins[] = { 2650static const unsigned int sdhi2_data1_pins[] = {
2518 /* D0 */ 2651 /* D0 */
2519 RCAR_GP_PIN(3, 18), 2652 RCAR_GP_PIN(3, 18),
@@ -2549,7 +2682,7 @@ static const unsigned int sdhi2_wp_pins[] = {
2549static const unsigned int sdhi2_wp_mux[] = { 2682static const unsigned int sdhi2_wp_mux[] = {
2550 SD2_WP_MARK, 2683 SD2_WP_MARK,
2551}; 2684};
2552 2685/* - SDHI3 ------------------------------------------------------------------ */
2553static const unsigned int sdhi3_data1_pins[] = { 2686static const unsigned int sdhi3_data1_pins[] = {
2554 /* D0 */ 2687 /* D0 */
2555 RCAR_GP_PIN(3, 26), 2688 RCAR_GP_PIN(3, 26),
@@ -2591,10 +2724,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2591 SH_PFC_PIN_GROUP(eth_magic), 2724 SH_PFC_PIN_GROUP(eth_magic),
2592 SH_PFC_PIN_GROUP(eth_mdio), 2725 SH_PFC_PIN_GROUP(eth_mdio),
2593 SH_PFC_PIN_GROUP(eth_rmii), 2726 SH_PFC_PIN_GROUP(eth_rmii),
2727 SH_PFC_PIN_GROUP(hscif0_data),
2728 SH_PFC_PIN_GROUP(hscif0_clk),
2729 SH_PFC_PIN_GROUP(hscif0_ctrl),
2730 SH_PFC_PIN_GROUP(hscif0_data_b),
2731 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2732 SH_PFC_PIN_GROUP(hscif0_data_c),
2733 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
2734 SH_PFC_PIN_GROUP(hscif0_data_d),
2735 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
2736 SH_PFC_PIN_GROUP(hscif0_data_e),
2737 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
2738 SH_PFC_PIN_GROUP(hscif0_data_f),
2739 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
2740 SH_PFC_PIN_GROUP(hscif1_data),
2741 SH_PFC_PIN_GROUP(hscif1_clk),
2742 SH_PFC_PIN_GROUP(hscif1_ctrl),
2743 SH_PFC_PIN_GROUP(hscif1_data_b),
2744 SH_PFC_PIN_GROUP(hscif1_clk_b),
2745 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2594 SH_PFC_PIN_GROUP(intc_irq0), 2746 SH_PFC_PIN_GROUP(intc_irq0),
2595 SH_PFC_PIN_GROUP(intc_irq1), 2747 SH_PFC_PIN_GROUP(intc_irq1),
2596 SH_PFC_PIN_GROUP(intc_irq2), 2748 SH_PFC_PIN_GROUP(intc_irq2),
2597 SH_PFC_PIN_GROUP(intc_irq3), 2749 SH_PFC_PIN_GROUP(intc_irq3),
2750 SH_PFC_PIN_GROUP(mmc0_data1),
2751 SH_PFC_PIN_GROUP(mmc0_data4),
2752 SH_PFC_PIN_GROUP(mmc0_data8),
2753 SH_PFC_PIN_GROUP(mmc0_ctrl),
2754 SH_PFC_PIN_GROUP(mmc1_data1),
2755 SH_PFC_PIN_GROUP(mmc1_data4),
2756 SH_PFC_PIN_GROUP(mmc1_data8),
2757 SH_PFC_PIN_GROUP(mmc1_ctrl),
2598 SH_PFC_PIN_GROUP(scif0_data), 2758 SH_PFC_PIN_GROUP(scif0_data),
2599 SH_PFC_PIN_GROUP(scif0_clk), 2759 SH_PFC_PIN_GROUP(scif0_clk),
2600 SH_PFC_PIN_GROUP(scif0_ctrl), 2760 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2659,18 +2819,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2659 SH_PFC_PIN_GROUP(scifb2_clk_b), 2819 SH_PFC_PIN_GROUP(scifb2_clk_b),
2660 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 2820 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
2661 SH_PFC_PIN_GROUP(scifb2_data_c), 2821 SH_PFC_PIN_GROUP(scifb2_data_c),
2662 SH_PFC_PIN_GROUP(tpu0_to0),
2663 SH_PFC_PIN_GROUP(tpu0_to1),
2664 SH_PFC_PIN_GROUP(tpu0_to2),
2665 SH_PFC_PIN_GROUP(tpu0_to3),
2666 SH_PFC_PIN_GROUP(mmc0_data1),
2667 SH_PFC_PIN_GROUP(mmc0_data4),
2668 SH_PFC_PIN_GROUP(mmc0_data8),
2669 SH_PFC_PIN_GROUP(mmc0_ctrl),
2670 SH_PFC_PIN_GROUP(mmc1_data1),
2671 SH_PFC_PIN_GROUP(mmc1_data4),
2672 SH_PFC_PIN_GROUP(mmc1_data8),
2673 SH_PFC_PIN_GROUP(mmc1_ctrl),
2674 SH_PFC_PIN_GROUP(sdhi0_data1), 2822 SH_PFC_PIN_GROUP(sdhi0_data1),
2675 SH_PFC_PIN_GROUP(sdhi0_data4), 2823 SH_PFC_PIN_GROUP(sdhi0_data4),
2676 SH_PFC_PIN_GROUP(sdhi0_ctrl), 2824 SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2691,6 +2839,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2691 SH_PFC_PIN_GROUP(sdhi3_ctrl), 2839 SH_PFC_PIN_GROUP(sdhi3_ctrl),
2692 SH_PFC_PIN_GROUP(sdhi3_cd), 2840 SH_PFC_PIN_GROUP(sdhi3_cd),
2693 SH_PFC_PIN_GROUP(sdhi3_wp), 2841 SH_PFC_PIN_GROUP(sdhi3_wp),
2842 SH_PFC_PIN_GROUP(tpu0_to0),
2843 SH_PFC_PIN_GROUP(tpu0_to1),
2844 SH_PFC_PIN_GROUP(tpu0_to2),
2845 SH_PFC_PIN_GROUP(tpu0_to3),
2694}; 2846};
2695 2847
2696static const char * const eth_groups[] = { 2848static const char * const eth_groups[] = {
@@ -2726,6 +2878,31 @@ static const char * const scif1_groups[] = {
2726 "scif1_clk_e", 2878 "scif1_clk_e",
2727}; 2879};
2728 2880
2881static const char * const hscif0_groups[] = {
2882 "hscif0_data",
2883 "hscif0_clk",
2884 "hscif0_ctrl",
2885 "hscif0_data_b",
2886 "hscif0_ctrl_b",
2887 "hscif0_data_c",
2888 "hscif0_ctrl_c",
2889 "hscif0_data_d",
2890 "hscif0_ctrl_d",
2891 "hscif0_data_e",
2892 "hscif0_ctrl_e",
2893 "hscif0_data_f",
2894 "hscif0_ctrl_f",
2895};
2896
2897static const char * const hscif1_groups[] = {
2898 "hscif1_data",
2899 "hscif1_clk",
2900 "hscif1_ctrl",
2901 "hscif1_data_b",
2902 "hscif1_clk_b",
2903 "hscif1_ctrl_b",
2904};
2905
2729static const char * const scifa0_groups[] = { 2906static const char * const scifa0_groups[] = {
2730 "scifa0_data", 2907 "scifa0_data",
2731 "scifa0_clk", 2908 "scifa0_clk",
@@ -2850,7 +3027,11 @@ static const char * const sdhi3_groups[] = {
2850 3027
2851static const struct sh_pfc_function pinmux_functions[] = { 3028static const struct sh_pfc_function pinmux_functions[] = {
2852 SH_PFC_FUNCTION(eth), 3029 SH_PFC_FUNCTION(eth),
3030 SH_PFC_FUNCTION(hscif0),
3031 SH_PFC_FUNCTION(hscif1),
2853 SH_PFC_FUNCTION(intc), 3032 SH_PFC_FUNCTION(intc),
3033 SH_PFC_FUNCTION(mmc0),
3034 SH_PFC_FUNCTION(mmc1),
2854 SH_PFC_FUNCTION(scif0), 3035 SH_PFC_FUNCTION(scif0),
2855 SH_PFC_FUNCTION(scif1), 3036 SH_PFC_FUNCTION(scif1),
2856 SH_PFC_FUNCTION(scifa0), 3037 SH_PFC_FUNCTION(scifa0),
@@ -2859,13 +3040,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
2859 SH_PFC_FUNCTION(scifb0), 3040 SH_PFC_FUNCTION(scifb0),
2860 SH_PFC_FUNCTION(scifb1), 3041 SH_PFC_FUNCTION(scifb1),
2861 SH_PFC_FUNCTION(scifb2), 3042 SH_PFC_FUNCTION(scifb2),
2862 SH_PFC_FUNCTION(tpu0),
2863 SH_PFC_FUNCTION(mmc0),
2864 SH_PFC_FUNCTION(mmc1),
2865 SH_PFC_FUNCTION(sdhi0), 3043 SH_PFC_FUNCTION(sdhi0),
2866 SH_PFC_FUNCTION(sdhi1), 3044 SH_PFC_FUNCTION(sdhi1),
2867 SH_PFC_FUNCTION(sdhi2), 3045 SH_PFC_FUNCTION(sdhi2),
2868 SH_PFC_FUNCTION(sdhi3), 3046 SH_PFC_FUNCTION(sdhi3),
3047 SH_PFC_FUNCTION(tpu0),
2869}; 3048};
2870 3049
2871static struct pinmux_cfg_reg pinmux_config_regs[] = { 3050static struct pinmux_cfg_reg pinmux_config_regs[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 04:07:06 -0500