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path: root/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
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Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7790.c')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c3835
1 files changed, 3835 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
new file mode 100644
index 000000000000..85d77a417c0e
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -0,0 +1,3835 @@
1/*
2 * R8A7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#include <linux/kernel.h>
25#include <linux/platform_data/gpio-rcar.h>
26
27#include "core.h"
28#include "sh_pfc.h"
29
30#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
31
32#define PORT_GP_32(bank, fn, sfx) \
33 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
34 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
35 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
36 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
37 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
38 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
39 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
40 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
41 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
42 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
43 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
44 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
45 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
46 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
47 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
48 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
49
50#define PORT_GP_32_REV(bank, fn, sfx) \
51 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
52 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
53 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
54 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
55 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
56 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
57 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
58 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
59 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
60 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
61 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
62 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
63 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
64 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
65 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
66 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
67
68#define CPU_ALL_PORT(fn, sfx) \
69 PORT_GP_32(0, fn, sfx), \
70 PORT_GP_32(1, fn, sfx), \
71 PORT_GP_32(2, fn, sfx), \
72 PORT_GP_32(3, fn, sfx), \
73 PORT_GP_32(4, fn, sfx), \
74 PORT_GP_32(5, fn, sfx)
75
76#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
77
78#define _GP_GPIO(bank, pin, _name, sfx) \
79 [(bank * 32) + pin] = { \
80 .name = __stringify(_name), \
81 .enum_id = _name##_DATA, \
82 }
83
84#define _GP_DATA(bank, pin, name, sfx) \
85 PINMUX_DATA(name##_DATA, name##_FN)
86
87#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
88#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
89#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
90
91#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
92#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
93 FN_##ipsr, FN_##fn)
94
95enum {
96 PINMUX_RESERVED = 0,
97
98 PINMUX_DATA_BEGIN,
99 GP_ALL(DATA),
100 PINMUX_DATA_END,
101
102 PINMUX_FUNCTION_BEGIN,
103 GP_ALL(FN),
104
105 /* GPSR0 */
106 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
107 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
108 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
109 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
110 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
111 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
112 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
113 FN_IP3_14_12, FN_IP3_17_15,
114
115 /* GPSR1 */
116 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
117 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
118 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
119 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
120 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
121 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
122 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
123
124 /* GPSR2 */
125 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
126 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
127 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
128 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
129 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
130 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
131 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
132
133 /* GPSR3 */
134 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
135 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
136 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
137 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
138 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
139 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
140 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
141
142 /* GPSR4 */
143 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
144 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
145 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
146 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
147 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
148 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
149 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
150 FN_IP14_15_12, FN_IP14_18_16,
151
152 /* GPSR5 */
153 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
154 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
155 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
156 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
157 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
158 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
159 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
160
161 /* IPSR0 */
162 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
163 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
164 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
165 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
166 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
167 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
168 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
169 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
170 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
171 FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
172 FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
173 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
174 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
175 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
176
177 /* IPSR1 */
178 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
179 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
180 FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
181 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
182 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
183 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
184 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
185 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
186 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
187 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
188 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
189 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
190 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
191 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
192 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
193
194 /* IPSR2 */
195 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
196 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
197 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
198 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
199 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
200 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
201 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
202 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
203 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
204 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
205 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
206
207 /* IPSR3 */
208 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
209 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
210 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
211 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
212 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
213 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
214 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
215 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
216 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
217 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
218 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
219 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
220 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
221
222 /* IPSR4 */
223 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
224 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
225 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
226 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
227 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
228 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
229 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
230 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
231 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
232 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
233 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
234 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
235 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
236 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
237 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
238
239 /* IPSR5 */
240 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
241 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
242 FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
243 FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
244 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
245 FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
246 FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
247 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
248 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
249 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
250 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
251 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
252 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
253 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
254 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
255 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
256 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
257 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
258 FN_SSI_WS78_B,
259
260 /* IPSR6 */
261 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
262 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
263 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
264 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
265 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
266 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
267 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
268 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
269 FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
270 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
271 FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
272 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
273 FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
274 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
275 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
276 FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
277 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
278 FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
279 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
280 FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
281 FN_STP_IVCXO27_1_B, FN_HRX0_F,
282
283 /* IPSR7 */
284 FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
285 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
286 FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
287 FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
288 FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
289 FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
290 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
291 FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
292 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
293 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
294 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
295 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
296 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
297 FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
298 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
299 FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
300 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
301 FN_MII_RXD2,
302
303 /* IPSR8 */
304 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
305 FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
306 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
307 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
308 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
309 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
310 FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
311 FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
312 FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
313 FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
314 FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
315 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
316 FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
317 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
318 FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
319 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
320 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
321 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
322
323 /* IPSR9 */
324 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
325 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
326 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
327 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
328 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
329 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
330 FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
331 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
332 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
333 FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
334 FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
335 FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
336 FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
337 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
338 FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
339 FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
340 FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
341 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
342 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
343 FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
344 FN_VI3_CLK_B,
345
346 /* IPSR10 */
347 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
348 FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
349 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
350 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
351 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
352 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
353 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
354 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
355 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
356 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
357 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
358 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
359 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
360 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
361 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
362 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
363 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
364 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
365 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
366 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
367 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
368 FN_GLO_I0_B, FN_VI3_DATA6_B,
369
370 /* IPSR11 */
371 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
372 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
373 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
374 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
375 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
376 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
377 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
378 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
379 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
380 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
381 FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
382 FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
383 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
384 FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
385 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
386 FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
387 FN_MOUT0,
388
389 /* IPSR12 */
390 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
391 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
392 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
393 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
394 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
395 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
396 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
397 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
398 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
399 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
400 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
401 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
402 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
403 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
404 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
405 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
406 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
407 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
408 FN_CAN_DEBUGOUT4,
409
410 /* IPSR13 */
411 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
412 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
413 FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
414 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
415 FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
416 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
417 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
418 FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
419 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
420 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
421 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
422 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
423 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
424 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
425 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
426 FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
427 FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
428 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
429 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
430 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
431 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
432 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
433
434 /* IPSR14 */
435 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
436 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
437 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
438 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
439 FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
440 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
441 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
442 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
443 FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
444 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
445 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
446 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
447 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
448 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
449 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
450 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
451 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
452 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
453 FN_HRTS0_N_C,
454
455 /* IPSR15 */
456 FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
457 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
458 FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
459 FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
460 FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
461 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
462 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
463 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
464 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
465 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
466 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
467 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
468 FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
469 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
470 FN_DU2_DG6, FN_LCDOUT14,
471
472 /* IPSR16 */
473 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
474 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
475 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
476 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
477 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
478 FN_TCLK1_B,
479
480 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
481 FN_SEL_SCIF1_4,
482 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
483 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
484 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
485 FN_SEL_SCIFB1_4,
486 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
487 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
488 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
489 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
490 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
491 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
492 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
493 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
494 FN_SEL_VI3_0, FN_SEL_VI3_1,
495 FN_SEL_VI2_0, FN_SEL_VI2_1,
496 FN_SEL_VI1_0, FN_SEL_VI1_1,
497 FN_SEL_VI0_0, FN_SEL_VI0_1,
498 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
499 FN_SEL_LBS_0, FN_SEL_LBS_1,
500 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
501 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
502 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
503
504 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
505 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
506 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
507 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
508 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
509 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
510 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
511 FN_SEL_ADI_0, FN_SEL_ADI_1,
512 FN_SEL_SSP_0, FN_SEL_SSP_1,
513 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
514 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
515 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
516 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
517 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
518 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
519 FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
520 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
521 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
522
523 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
524 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
525 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
526 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
527 FN_SEL_IIC2_4,
528 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
529 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
530 FN_SEL_I2C2_4,
531 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
532 PINMUX_FUNCTION_END,
533
534 PINMUX_MARK_BEGIN,
535
536 VI1_DATA7_VI1_B7_MARK,
537
538 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
539 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
540 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
541
542 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
543 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
544 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
545 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
546 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
547 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
548 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
549 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
550 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
551 SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
552 SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
553 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
554 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
555 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
556
557 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
558 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
559 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
560 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
561 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
562 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
563 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
564 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
565 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
566 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
567 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
568 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
569 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
570 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
571 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
572
573 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
574 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
575 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
576 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
577 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
578 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
579 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
580 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
581 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
582 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
583 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
584
585 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
586 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
587 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
588 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
589 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
590 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
591 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
592 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
593 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
594 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
595 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
596 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
597 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
598
599 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
600 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
601 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
602 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
603 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
604 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
605 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
606 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
607 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
608 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
609 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
610 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
611 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
612 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
613 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
614
615 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
616 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
617 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
618 VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
619 INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
620 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
621 VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
622 SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
623 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
624 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
625 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
626 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
627 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
628 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
629 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
630 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
631 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
632 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
633 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
634 SSI_WS78_B_MARK,
635
636 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
637 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
638 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
639 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
640 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
641 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
642 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
643 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
644 ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
645 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
646 SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
647 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
648 SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
649 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
650 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
651 RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
652 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
653 RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
654 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
655 ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
656 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
657
658 ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
659 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
660 RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
661 ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
662 HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
663 SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
664 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
665 ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
666 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
667 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
668 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
669 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
670 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
671 PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
672 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
673 ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
674 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
675 MII_RXD2_MARK,
676
677 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
678 MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
679 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
680 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
681 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
682 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
683 MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
684 MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
685 MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
686 AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
687 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
688 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
689 MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
690 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
691 AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
692 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
693 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
694 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
695
696 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
697 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
698 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
699 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
700 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
701 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
702 SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
703 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
704 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
705 SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
706 AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
707 AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
708 SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
709 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
710 MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
711 AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
712 SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
713 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
714 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
715 SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
716 VI3_CLK_B_MARK,
717
718 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
719 GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
720 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
721 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
722 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
723 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
724 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
725 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
726 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
727 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
728 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
729 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
730 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
731 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
732 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
733 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
734 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
735 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
736 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
737 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
738 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
739 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
740
741 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
742 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
743 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
744 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
745 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
746 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
747 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
748 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
749 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
750 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
751 RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
752 RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
753 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
754 SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
755 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
756 RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
757 MOUT0_MARK,
758
759 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
760 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
761 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
762 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
763 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
764 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
765 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
766 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
767 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
768 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
769 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
770 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
771 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
772 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
773 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
774 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
775 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
776 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
777 CAN_DEBUGOUT4_MARK,
778
779 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
780 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
781 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
782 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
783 BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
784 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
785 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
786 FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
787 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
788 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
789 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
790 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
791 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
792 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
793 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
794 BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
795 FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
796 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
797 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
798 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
799 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
800 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
801
802 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
803 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
804 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
805 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
806 SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
807 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
808 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
809 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
810 LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
811 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
812 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
813 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
814 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
815 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
816 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
817 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
818 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
819 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
820 HRTS0_N_C_MARK,
821
822 SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
823 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
824 DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
825 SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
826 SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
827 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
828 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
829 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
830 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
831 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
832 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
833 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
834 SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
835 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
836 DU2_DG6_MARK, LCDOUT14_MARK,
837
838 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
839 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
840 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
841 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
842 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
843 TCLK1_B_MARK,
844 PINMUX_MARK_END,
845};
846
847static const pinmux_enum_t pinmux_data[] = {
848 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
849
850 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
851 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
852 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
853 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
854 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
855 PINMUX_DATA(AVS1_MARK, FN_AVS1),
856 PINMUX_DATA(AVS2_MARK, FN_AVS2),
857 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
858 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
859
860 PINMUX_IPSR_DATA(IP0_2_0, D0),
861 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
862 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
863 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
864 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
865 PINMUX_IPSR_DATA(IP0_5_3, D1),
866 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
867 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
868 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
869 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
870 PINMUX_IPSR_DATA(IP0_8_6, D2),
871 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
872 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
873 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
874 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
875 PINMUX_IPSR_DATA(IP0_11_9, D3),
876 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
877 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
878 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
880 PINMUX_IPSR_DATA(IP0_15_12, D4),
881 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
882 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
883 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
884 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
885 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
886 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
887 PINMUX_IPSR_DATA(IP0_19_16, D5),
888 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
889 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
890 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
891 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
892 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
893 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
894 PINMUX_IPSR_DATA(IP0_22_20, D6),
895 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
896 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
897 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
898 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
899 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
900 PINMUX_IPSR_DATA(IP0_26_23, D7),
901 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
902 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
903 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
904 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
905 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
906 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
907 PINMUX_IPSR_DATA(IP0_30_27, D8),
908 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
909 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
910 PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
911 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
912 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
913 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
914
915 PINMUX_IPSR_DATA(IP1_3_0, D9),
916 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
917 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
918 PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
919 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
920 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
921 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
922 PINMUX_IPSR_DATA(IP1_7_4, D10),
923 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
924 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
925 PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
926 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
927 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
928 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
929 PINMUX_IPSR_DATA(IP1_11_8, D11),
930 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
931 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
932 PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
933 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
934 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
935 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
936 PINMUX_IPSR_DATA(IP1_14_12, D12),
937 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
938 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
939 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
940 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
941 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
942 PINMUX_IPSR_DATA(IP1_17_15, D13),
943 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
944 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
945 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
946 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
947 PINMUX_IPSR_DATA(IP1_21_18, D14),
948 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
949 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
950 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
951 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
952 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
953 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
954 PINMUX_IPSR_DATA(IP1_25_22, D15),
955 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
956 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
957 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
958 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
959 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
960 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
961 PINMUX_IPSR_DATA(IP1_27_26, A0),
962 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
963 PINMUX_IPSR_DATA(IP1_29_28, A1),
964 PINMUX_IPSR_DATA(IP1_29_28, PWM4),
965
966 PINMUX_IPSR_DATA(IP2_2_0, A2),
967 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
968 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
969 PINMUX_IPSR_DATA(IP2_5_3, A3),
970 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
971 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
972 PINMUX_IPSR_DATA(IP2_8_6, A4),
973 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
974 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
975 PINMUX_IPSR_DATA(IP2_11_9, A5),
976 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
977 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
978 PINMUX_IPSR_DATA(IP2_14_12, A6),
979 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
980 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
981 PINMUX_IPSR_DATA(IP2_17_15, A7),
982 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
983 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
984 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
985 PINMUX_IPSR_DATA(IP2_21_18, A8),
986 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
987 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
988 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
989 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
990 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
991 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
992 PINMUX_IPSR_DATA(IP2_25_22, A9),
993 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
994 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
995 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
996 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
997 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
998 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
999 PINMUX_IPSR_DATA(IP2_28_26, A10),
1000 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
1001 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
1002 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
1003 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
1004 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
1005
1006 PINMUX_IPSR_DATA(IP3_3_0, A11),
1007 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1008 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
1009 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
1010 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
1011 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
1012 PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
1013 PINMUX_IPSR_DATA(IP3_7_4, A12),
1014 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
1015 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
1016 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
1017 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
1018 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
1019 PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
1020 PINMUX_IPSR_DATA(IP3_11_8, A13),
1021 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1022 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
1023 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
1024 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
1025 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
1026 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
1027 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
1028 PINMUX_IPSR_DATA(IP3_14_12, A14),
1029 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
1030 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
1031 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
1032 PINMUX_IPSR_DATA(IP3_17_15, A15),
1033 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
1034 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
1035 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
1036 PINMUX_IPSR_DATA(IP3_19_18, A16),
1037 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
1038 PINMUX_IPSR_DATA(IP3_22_20, A17),
1039 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
1040 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
1041 PINMUX_IPSR_DATA(IP3_25_23, A18),
1042 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
1043 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
1044 PINMUX_IPSR_DATA(IP3_28_26, A19),
1045 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
1046 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
1047 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
1048 PINMUX_IPSR_DATA(IP3_31_29, A20),
1049 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
1050 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
1051 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
1052 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
1053
1054 PINMUX_IPSR_DATA(IP4_2_0, A21),
1055 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
1056 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
1057 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1058 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1059 PINMUX_IPSR_DATA(IP4_5_3, A22),
1060 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1061 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1063 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1064 PINMUX_IPSR_DATA(IP4_8_6, A23),
1065 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1066 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1067 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1068 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1069 PINMUX_IPSR_DATA(IP4_11_9, A24),
1070 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1071 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1072 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1073 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1074 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1075 PINMUX_IPSR_DATA(IP4_14_12, A25),
1076 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1077 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1078 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1079 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1081 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1082 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1083 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1084 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1085 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1086 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1087 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1088 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1089 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1090 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1091 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1092 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1093 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1094 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1095 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1096 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1097 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1098 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1099 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1100 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1101 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1102 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1103 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1104 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1105 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1106 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1107 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1108 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1109 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1110 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1111 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1112
1113 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1114 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1115 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1117 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1118 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
1120 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1121 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1122 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1123 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
1124 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1125 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1126 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
1127 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1128 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1129 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1130 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1131 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1132 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1133 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1134 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
1135 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1136 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
1137 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1138 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1139 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1141 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1142 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1143 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1144 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1145 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1146 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1147 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1148 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1149 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1150 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1151 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1152 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1153 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1154 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1155 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1156 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1157 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1158 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1159 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1160 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1161 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1162 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1163 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1164 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1165 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1166 PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
1167 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1168 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1169 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1170 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1171 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1172 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1173 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1174 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1175 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1176 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1177 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1178 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1179
1180 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1181 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1182 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1183 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1184 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1185 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1186 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1187 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1188 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1189 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1190 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1191 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1192 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1193 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1194 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1195 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1196 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1197 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1198 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1200 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1201 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1202 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1203 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1204 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1205 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1207 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1208 PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
1209 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1211 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1212 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
1213 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
1214 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1215 PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
1216 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1218 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1219 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
1220 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
1221 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1222 PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
1223 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1225 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1226 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1227 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1228 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1229 PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
1230 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1231 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1232 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1233 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1234 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1235 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1236 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1237 PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
1238 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1239 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1240 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1241 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1242 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1243 PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
1244 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1245 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1246 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1247
1248 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1249 PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
1250 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1251 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1252 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1253 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1254 PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
1255 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
1256 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
1257 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
1258 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1259 PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
1260 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1261 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1262 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1263 PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
1264 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1265 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1266 PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
1267 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1268 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1269 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1270 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1271 PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
1272 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1273 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1274 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1275 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1276 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1277 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1278 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1279 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1280 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1281 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1282 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1283 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1284 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1285 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1286 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1287 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1288 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1289 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1290 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1291 PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
1292 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1293 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1294 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1295 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1296 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1297 PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
1298 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1299 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1300 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1301 PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
1302
1303 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1304 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1305 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1306 PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
1307 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1308 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1309 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1310 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1311 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1312 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1313 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1314 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1315 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1316 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1317 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1318 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1319 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1320 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1321 PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
1322 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1323 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1324 PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
1325 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1326 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1327 PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
1328 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1329 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1330 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1331 PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
1332 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1333 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1334 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1335 PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
1336 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1337 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1338 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1339 PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
1340 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1341 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1342 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1343 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1344 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1345 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1346 PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
1347 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1348 PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
1349 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1350 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1351 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1352 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1353 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1354 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1355 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1356
1357 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1358 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1359 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1360 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1361 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1362 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1363 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1364 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1365 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1366 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1367 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1368 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1369 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1370 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1371 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1372 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1373 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1374 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
1376 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
1377 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1378 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1379 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1380 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1381 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1382 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1383 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
1385 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
1386 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1387 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1388 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1389 PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
1390 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1391 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1392 PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
1393 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1394 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1395 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1396 PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
1397 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1398 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1399 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1400 PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
1401 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1402 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1403 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1404 PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
1405 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1406 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1407 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1408 PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
1409 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1410 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1411 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1412 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1413 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1414 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1415 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1416 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
1417 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
1418 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1419 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1420
1421 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1422 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1423 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1424 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1425 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1426 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1427 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
1428 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
1429 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1430 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1431 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1432 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1433 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1434 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1435 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1436 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1437 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1438 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1439 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1440 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1441 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1442 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1443 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1444 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1445 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1446 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1447 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1448 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1449 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1450 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1451 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1452 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1453 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1454 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1455 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1456 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1457 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1458 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
1459 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1460 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1461 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1462 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1463 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1464 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1465 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1466 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1467 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1468 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
1469 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1470 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1471 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1472 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1473 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1474 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1475 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1476 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1477 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1478 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1479 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1480 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1481 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1482 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1483 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1484 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1485 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1486 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1487 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1488 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1489 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1490 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1491 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1492
1493 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1494 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1495 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1496 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1497 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1498 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1499 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1500 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1501 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1502 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1503 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1504 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1505 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1506 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1507 PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1508 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1509 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1510 PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1511 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1512 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1513 PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1514 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1515 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1516 PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1517 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1518 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1519 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1520 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1521 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1522 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1523 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1524 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1525 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1526 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1527 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1528 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1529 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1530 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1531 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
1532 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1533 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
1534 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1535 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
1536 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1537 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
1538 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
1539 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1540 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1541 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1542 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
1543 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
1544 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1545 PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
1546 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1547 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1548 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1549 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
1550 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1551 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1552 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1553
1554 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1555 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1556 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1557 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1558 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1559 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1560 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1561 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1562 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1563 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1564 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1565 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
1566 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1567 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1568 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1569 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1570 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1571 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1572 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1573 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1575 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1576 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1577 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1578 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1579 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1580 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1581 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1582 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1583 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1584 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1585 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1586 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1587 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1588 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1589 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1590 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1591 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1592 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1593 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1594 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1595 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1596 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1597 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1598 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1599 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1600 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1601 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1602 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1603 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1604 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1605 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1607 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1608 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1609 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1610
1611 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1612 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1613 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1614 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1615 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1616 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1617 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1618 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1619 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1620 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
1621 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1622 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1623 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1624 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1625 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
1626 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1629 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1630 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1631 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1632 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1633 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1634 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
1635 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1636 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1637 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1638 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1639 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1640 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1641 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1642 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1643 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1644 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1645 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1647 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1648 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1649 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1650 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1651 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1652 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1653 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1654 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1655 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1656 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1657 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1658 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1659 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1660 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
1661 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1662 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1663 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
1664 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1665 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1666 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1667 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1668 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1669 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1670 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1671 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1672 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1673 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1674 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1675 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1676 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1677 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1678 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1679
1680 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1681 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1682 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1683 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1684 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1685 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1686 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1687 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1688 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1689 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1690 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1691 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1692 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1693 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
1694 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
1695 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1696 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1697 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1698 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1699 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1700 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1701 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1702 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1703 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1704 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1705 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1706 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1707 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
1708 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1709 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1710 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
1711 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
1712 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
1713 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
1714 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1715 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1716 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
1717 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1718 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1719 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1720 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1721 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1722 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1723 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1724 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1725 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1726 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1727 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1728 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1729 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1730 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1731 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1732 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1733 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1734 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1735 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1736 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1737 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1738 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1739 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
1740 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1741 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1742 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1743 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1744
1745 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1746 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1747 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1748 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1749 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1750 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
1751 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1752 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1753 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1754 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1755 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
1756 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
1757 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1758 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1759 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1760 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1761 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
1762 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
1763 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1764 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1765 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1766 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1767 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
1768 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
1769 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1770 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1771 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1772 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1773 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1774 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1775 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1776 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1777 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1778 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1779 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1780 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1781 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1782 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1783 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1784 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1785 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1786 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1787 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1788 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1789 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1790 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1791 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1792 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1793 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1794 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
1795 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1796 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1797 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1798 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1799 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1800 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1801 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1802 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1803
1804 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1805 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1806 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1807 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1808 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1809 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1810 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1811 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1812 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1813 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1814 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1815 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1816 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1817 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
1818 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1819 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1820 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1821 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1822};
1823
1824static struct sh_pfc_pin pinmux_pins[] = {
1825 PINMUX_GPIO_GP_ALL(),
1826};
1827
1828/* - ETH -------------------------------------------------------------------- */
1829static const unsigned int eth_link_pins[] = {
1830 /* LINK */
1831 RCAR_GP_PIN(2, 22),
1832};
1833static const unsigned int eth_link_mux[] = {
1834 ETH_LINK_MARK,
1835};
1836static const unsigned int eth_magic_pins[] = {
1837 /* MAGIC */
1838 RCAR_GP_PIN(2, 27),
1839};
1840static const unsigned int eth_magic_mux[] = {
1841 ETH_MAGIC_MARK,
1842};
1843static const unsigned int eth_mdio_pins[] = {
1844 /* MDC, MDIO */
1845 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1846};
1847static const unsigned int eth_mdio_mux[] = {
1848 ETH_MDC_MARK, ETH_MDIO_MARK,
1849};
1850static const unsigned int eth_rmii_pins[] = {
1851 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1852 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1853 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1854 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1855};
1856static const unsigned int eth_rmii_mux[] = {
1857 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1858 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1859};
1860/* - INTC ------------------------------------------------------------------- */
1861static const unsigned int intc_irq0_pins[] = {
1862 /* IRQ */
1863 RCAR_GP_PIN(1, 25),
1864};
1865static const unsigned int intc_irq0_mux[] = {
1866 IRQ0_MARK,
1867};
1868static const unsigned int intc_irq1_pins[] = {
1869 /* IRQ */
1870 RCAR_GP_PIN(1, 27),
1871};
1872static const unsigned int intc_irq1_mux[] = {
1873 IRQ1_MARK,
1874};
1875static const unsigned int intc_irq2_pins[] = {
1876 /* IRQ */
1877 RCAR_GP_PIN(1, 29),
1878};
1879static const unsigned int intc_irq2_mux[] = {
1880 IRQ2_MARK,
1881};
1882static const unsigned int intc_irq3_pins[] = {
1883 /* IRQ */
1884 RCAR_GP_PIN(1, 23),
1885};
1886static const unsigned int intc_irq3_mux[] = {
1887 IRQ3_MARK,
1888};
1889/* - SCIF0 ----------------------------------------------------------------- */
1890static const unsigned int scif0_data_pins[] = {
1891 /* RX, TX */
1892 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1893};
1894static const unsigned int scif0_data_mux[] = {
1895 RX0_MARK, TX0_MARK,
1896};
1897static const unsigned int scif0_clk_pins[] = {
1898 /* SCK */
1899 RCAR_GP_PIN(4, 27),
1900};
1901static const unsigned int scif0_clk_mux[] = {
1902 SCK0_MARK,
1903};
1904static const unsigned int scif0_ctrl_pins[] = {
1905 /* RTS, CTS */
1906 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
1907};
1908static const unsigned int scif0_ctrl_mux[] = {
1909 RTS0_N_TANS_MARK, CTS0_N_MARK,
1910};
1911static const unsigned int scif0_data_b_pins[] = {
1912 /* RX, TX */
1913 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1914};
1915static const unsigned int scif0_data_b_mux[] = {
1916 RX0_B_MARK, TX0_B_MARK,
1917};
1918/* - SCIF1 ----------------------------------------------------------------- */
1919static const unsigned int scif1_data_pins[] = {
1920 /* RX, TX */
1921 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1922};
1923static const unsigned int scif1_data_mux[] = {
1924 RX1_MARK, TX1_MARK,
1925};
1926static const unsigned int scif1_clk_pins[] = {
1927 /* SCK */
1928 RCAR_GP_PIN(4, 20),
1929};
1930static const unsigned int scif1_clk_mux[] = {
1931 SCK1_MARK,
1932};
1933static const unsigned int scif1_ctrl_pins[] = {
1934 /* RTS, CTS */
1935 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
1936};
1937static const unsigned int scif1_ctrl_mux[] = {
1938 RTS1_N_TANS_MARK, CTS1_N_MARK,
1939};
1940static const unsigned int scif1_data_b_pins[] = {
1941 /* RX, TX */
1942 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1943};
1944static const unsigned int scif1_data_b_mux[] = {
1945 RX1_B_MARK, TX1_B_MARK,
1946};
1947static const unsigned int scif1_data_c_pins[] = {
1948 /* RX, TX */
1949 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
1950};
1951static const unsigned int scif1_data_c_mux[] = {
1952 RX1_C_MARK, TX1_C_MARK,
1953};
1954static const unsigned int scif1_data_d_pins[] = {
1955 /* RX, TX */
1956 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1957};
1958static const unsigned int scif1_data_d_mux[] = {
1959 RX1_D_MARK, TX1_D_MARK,
1960};
1961static const unsigned int scif1_clk_d_pins[] = {
1962 /* SCK */
1963 RCAR_GP_PIN(3, 17),
1964};
1965static const unsigned int scif1_clk_d_mux[] = {
1966 SCK1_D_MARK,
1967};
1968static const unsigned int scif1_data_e_pins[] = {
1969 /* RX, TX */
1970 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1971};
1972static const unsigned int scif1_data_e_mux[] = {
1973 RX1_E_MARK, TX1_E_MARK,
1974};
1975static const unsigned int scif1_clk_e_pins[] = {
1976 /* SCK */
1977 RCAR_GP_PIN(2, 20),
1978};
1979static const unsigned int scif1_clk_e_mux[] = {
1980 SCK1_E_MARK,
1981};
1982/* - SCIFA0 ----------------------------------------------------------------- */
1983static const unsigned int scifa0_data_pins[] = {
1984 /* RXD, TXD */
1985 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1986};
1987static const unsigned int scifa0_data_mux[] = {
1988 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1989};
1990static const unsigned int scifa0_clk_pins[] = {
1991 /* SCK */
1992 RCAR_GP_PIN(4, 27),
1993};
1994static const unsigned int scifa0_clk_mux[] = {
1995 SCIFA0_SCK_MARK,
1996};
1997static const unsigned int scifa0_ctrl_pins[] = {
1998 /* RTS, CTS */
1999 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2000};
2001static const unsigned int scifa0_ctrl_mux[] = {
2002 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2003};
2004static const unsigned int scifa0_data_b_pins[] = {
2005 /* RXD, TXD */
2006 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2007};
2008static const unsigned int scifa0_data_b_mux[] = {
2009 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2010};
2011static const unsigned int scifa0_clk_b_pins[] = {
2012 /* SCK */
2013 RCAR_GP_PIN(1, 19),
2014};
2015static const unsigned int scifa0_clk_b_mux[] = {
2016 SCIFA0_SCK_B_MARK,
2017};
2018static const unsigned int scifa0_ctrl_b_pins[] = {
2019 /* RTS, CTS */
2020 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2021};
2022static const unsigned int scifa0_ctrl_b_mux[] = {
2023 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2024};
2025/* - SCIFA1 ----------------------------------------------------------------- */
2026static const unsigned int scifa1_data_pins[] = {
2027 /* RXD, TXD */
2028 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2029};
2030static const unsigned int scifa1_data_mux[] = {
2031 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2032};
2033static const unsigned int scifa1_clk_pins[] = {
2034 /* SCK */
2035 RCAR_GP_PIN(4, 20),
2036};
2037static const unsigned int scifa1_clk_mux[] = {
2038 SCIFA1_SCK_MARK,
2039};
2040static const unsigned int scifa1_ctrl_pins[] = {
2041 /* RTS, CTS */
2042 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2043};
2044static const unsigned int scifa1_ctrl_mux[] = {
2045 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2046};
2047static const unsigned int scifa1_data_b_pins[] = {
2048 /* RXD, TXD */
2049 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2050};
2051static const unsigned int scifa1_data_b_mux[] = {
2052 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2053};
2054static const unsigned int scifa1_clk_b_pins[] = {
2055 /* SCK */
2056 RCAR_GP_PIN(0, 23),
2057};
2058static const unsigned int scifa1_clk_b_mux[] = {
2059 SCIFA1_SCK_B_MARK,
2060};
2061static const unsigned int scifa1_ctrl_b_pins[] = {
2062 /* RTS, CTS */
2063 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2064};
2065static const unsigned int scifa1_ctrl_b_mux[] = {
2066 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2067};
2068static const unsigned int scifa1_data_c_pins[] = {
2069 /* RXD, TXD */
2070 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2071};
2072static const unsigned int scifa1_data_c_mux[] = {
2073 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2074};
2075static const unsigned int scifa1_clk_c_pins[] = {
2076 /* SCK */
2077 RCAR_GP_PIN(0, 8),
2078};
2079static const unsigned int scifa1_clk_c_mux[] = {
2080 SCIFA1_SCK_C_MARK,
2081};
2082static const unsigned int scifa1_ctrl_c_pins[] = {
2083 /* RTS, CTS */
2084 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2085};
2086static const unsigned int scifa1_ctrl_c_mux[] = {
2087 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2088};
2089static const unsigned int scifa1_data_d_pins[] = {
2090 /* RXD, TXD */
2091 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2092};
2093static const unsigned int scifa1_data_d_mux[] = {
2094 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2095};
2096static const unsigned int scifa1_clk_d_pins[] = {
2097 /* SCK */
2098 RCAR_GP_PIN(2, 10),
2099};
2100static const unsigned int scifa1_clk_d_mux[] = {
2101 SCIFA1_SCK_D_MARK,
2102};
2103static const unsigned int scifa1_ctrl_d_pins[] = {
2104 /* RTS, CTS */
2105 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2106};
2107static const unsigned int scifa1_ctrl_d_mux[] = {
2108 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2109};
2110/* - SCIFA2 ----------------------------------------------------------------- */
2111static const unsigned int scifa2_data_pins[] = {
2112 /* RXD, TXD */
2113 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2114};
2115static const unsigned int scifa2_data_mux[] = {
2116 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2117};
2118static const unsigned int scifa2_clk_pins[] = {
2119 /* SCK */
2120 RCAR_GP_PIN(5, 4),
2121};
2122static const unsigned int scifa2_clk_mux[] = {
2123 SCIFA2_SCK_MARK,
2124};
2125static const unsigned int scifa2_ctrl_pins[] = {
2126 /* RTS, CTS */
2127 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2128};
2129static const unsigned int scifa2_ctrl_mux[] = {
2130 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2131};
2132static const unsigned int scifa2_data_b_pins[] = {
2133 /* RXD, TXD */
2134 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2135};
2136static const unsigned int scifa2_data_b_mux[] = {
2137 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2138};
2139static const unsigned int scifa2_data_c_pins[] = {
2140 /* RXD, TXD */
2141 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2142};
2143static const unsigned int scifa2_data_c_mux[] = {
2144 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2145};
2146static const unsigned int scifa2_clk_c_pins[] = {
2147 /* SCK */
2148 RCAR_GP_PIN(5, 29),
2149};
2150static const unsigned int scifa2_clk_c_mux[] = {
2151 SCIFA2_SCK_C_MARK,
2152};
2153/* - SCIFB0 ----------------------------------------------------------------- */
2154static const unsigned int scifb0_data_pins[] = {
2155 /* RXD, TXD */
2156 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2157};
2158static const unsigned int scifb0_data_mux[] = {
2159 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2160};
2161static const unsigned int scifb0_clk_pins[] = {
2162 /* SCK */
2163 RCAR_GP_PIN(4, 8),
2164};
2165static const unsigned int scifb0_clk_mux[] = {
2166 SCIFB0_SCK_MARK,
2167};
2168static const unsigned int scifb0_ctrl_pins[] = {
2169 /* RTS, CTS */
2170 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2171};
2172static const unsigned int scifb0_ctrl_mux[] = {
2173 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2174};
2175static const unsigned int scifb0_data_b_pins[] = {
2176 /* RXD, TXD */
2177 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2178};
2179static const unsigned int scifb0_data_b_mux[] = {
2180 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2181};
2182static const unsigned int scifb0_clk_b_pins[] = {
2183 /* SCK */
2184 RCAR_GP_PIN(3, 9),
2185};
2186static const unsigned int scifb0_clk_b_mux[] = {
2187 SCIFB0_SCK_B_MARK,
2188};
2189static const unsigned int scifb0_ctrl_b_pins[] = {
2190 /* RTS, CTS */
2191 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2192};
2193static const unsigned int scifb0_ctrl_b_mux[] = {
2194 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2195};
2196static const unsigned int scifb0_data_c_pins[] = {
2197 /* RXD, TXD */
2198 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2199};
2200static const unsigned int scifb0_data_c_mux[] = {
2201 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2202};
2203/* - SCIFB1 ----------------------------------------------------------------- */
2204static const unsigned int scifb1_data_pins[] = {
2205 /* RXD, TXD */
2206 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2207};
2208static const unsigned int scifb1_data_mux[] = {
2209 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2210};
2211static const unsigned int scifb1_clk_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(4, 14),
2214};
2215static const unsigned int scifb1_clk_mux[] = {
2216 SCIFB1_SCK_MARK,
2217};
2218static const unsigned int scifb1_ctrl_pins[] = {
2219 /* RTS, CTS */
2220 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2221};
2222static const unsigned int scifb1_ctrl_mux[] = {
2223 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2224};
2225static const unsigned int scifb1_data_b_pins[] = {
2226 /* RXD, TXD */
2227 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2228};
2229static const unsigned int scifb1_data_b_mux[] = {
2230 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2231};
2232static const unsigned int scifb1_clk_b_pins[] = {
2233 /* SCK */
2234 RCAR_GP_PIN(3, 1),
2235};
2236static const unsigned int scifb1_clk_b_mux[] = {
2237 SCIFB1_SCK_B_MARK,
2238};
2239static const unsigned int scifb1_ctrl_b_pins[] = {
2240 /* RTS, CTS */
2241 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2242};
2243static const unsigned int scifb1_ctrl_b_mux[] = {
2244 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2245};
2246static const unsigned int scifb1_data_c_pins[] = {
2247 /* RXD, TXD */
2248 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2249};
2250static const unsigned int scifb1_data_c_mux[] = {
2251 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2252};
2253static const unsigned int scifb1_data_d_pins[] = {
2254 /* RXD, TXD */
2255 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2256};
2257static const unsigned int scifb1_data_d_mux[] = {
2258 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2259};
2260static const unsigned int scifb1_data_e_pins[] = {
2261 /* RXD, TXD */
2262 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2263};
2264static const unsigned int scifb1_data_e_mux[] = {
2265 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2266};
2267static const unsigned int scifb1_clk_e_pins[] = {
2268 /* SCK */
2269 RCAR_GP_PIN(3, 17),
2270};
2271static const unsigned int scifb1_clk_e_mux[] = {
2272 SCIFB1_SCK_E_MARK,
2273};
2274static const unsigned int scifb1_data_f_pins[] = {
2275 /* RXD, TXD */
2276 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2277};
2278static const unsigned int scifb1_data_f_mux[] = {
2279 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2280};
2281static const unsigned int scifb1_data_g_pins[] = {
2282 /* RXD, TXD */
2283 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2284};
2285static const unsigned int scifb1_data_g_mux[] = {
2286 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2287};
2288static const unsigned int scifb1_clk_g_pins[] = {
2289 /* SCK */
2290 RCAR_GP_PIN(2, 20),
2291};
2292static const unsigned int scifb1_clk_g_mux[] = {
2293 SCIFB1_SCK_G_MARK,
2294};
2295/* - SCIFB2 ----------------------------------------------------------------- */
2296static const unsigned int scifb2_data_pins[] = {
2297 /* RXD, TXD */
2298 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2299};
2300static const unsigned int scifb2_data_mux[] = {
2301 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2302};
2303static const unsigned int scifb2_clk_pins[] = {
2304 /* SCK */
2305 RCAR_GP_PIN(4, 21),
2306};
2307static const unsigned int scifb2_clk_mux[] = {
2308 SCIFB2_SCK_MARK,
2309};
2310static const unsigned int scifb2_ctrl_pins[] = {
2311 /* RTS, CTS */
2312 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
2313};
2314static const unsigned int scifb2_ctrl_mux[] = {
2315 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2316};
2317static const unsigned int scifb2_data_b_pins[] = {
2318 /* RXD, TXD */
2319 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
2320};
2321static const unsigned int scifb2_data_b_mux[] = {
2322 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2323};
2324static const unsigned int scifb2_clk_b_pins[] = {
2325 /* SCK */
2326 RCAR_GP_PIN(0, 31),
2327};
2328static const unsigned int scifb2_clk_b_mux[] = {
2329 SCIFB2_SCK_B_MARK,
2330};
2331static const unsigned int scifb2_ctrl_b_pins[] = {
2332 /* RTS, CTS */
2333 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
2334};
2335static const unsigned int scifb2_ctrl_b_mux[] = {
2336 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2337};
2338static const unsigned int scifb2_data_c_pins[] = {
2339 /* RXD, TXD */
2340 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2341};
2342static const unsigned int scifb2_data_c_mux[] = {
2343 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2344};
2345/* - TPU0 ------------------------------------------------------------------- */
2346static const unsigned int tpu0_to0_pins[] = {
2347 /* TO */
2348 RCAR_GP_PIN(0, 20),
2349};
2350static const unsigned int tpu0_to0_mux[] = {
2351 TPU0TO0_MARK,
2352};
2353static const unsigned int tpu0_to1_pins[] = {
2354 /* TO */
2355 RCAR_GP_PIN(0, 21),
2356};
2357static const unsigned int tpu0_to1_mux[] = {
2358 TPU0TO1_MARK,
2359};
2360static const unsigned int tpu0_to2_pins[] = {
2361 /* TO */
2362 RCAR_GP_PIN(0, 22),
2363};
2364static const unsigned int tpu0_to2_mux[] = {
2365 TPU0TO2_MARK,
2366};
2367static const unsigned int tpu0_to3_pins[] = {
2368 /* TO */
2369 RCAR_GP_PIN(0, 23),
2370};
2371static const unsigned int tpu0_to3_mux[] = {
2372 TPU0TO3_MARK,
2373};
2374
2375/* - MMCIF ------------------------------------------------------------------ */
2376static const unsigned int mmc0_data1_pins[] = {
2377 /* D[0] */
2378 RCAR_GP_PIN(3, 18),
2379};
2380static const unsigned int mmc0_data1_mux[] = {
2381 MMC0_D0_MARK,
2382};
2383static const unsigned int mmc0_data4_pins[] = {
2384 /* D[0:3] */
2385 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2386 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2387};
2388static const unsigned int mmc0_data4_mux[] = {
2389 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2390};
2391static const unsigned int mmc0_data8_pins[] = {
2392 /* D[0:7] */
2393 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2394 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2395 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2396 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2397};
2398static const unsigned int mmc0_data8_mux[] = {
2399 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2400 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2401};
2402static const unsigned int mmc0_ctrl_pins[] = {
2403 /* CLK, CMD */
2404 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2405};
2406static const unsigned int mmc0_ctrl_mux[] = {
2407 MMC0_CLK_MARK, MMC0_CMD_MARK,
2408};
2409
2410static const unsigned int mmc1_data1_pins[] = {
2411 /* D[0] */
2412 RCAR_GP_PIN(3, 26),
2413};
2414static const unsigned int mmc1_data1_mux[] = {
2415 MMC1_D0_MARK,
2416};
2417static const unsigned int mmc1_data4_pins[] = {
2418 /* D[0:3] */
2419 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2420 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2421};
2422static const unsigned int mmc1_data4_mux[] = {
2423 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2424};
2425static const unsigned int mmc1_data8_pins[] = {
2426 /* D[0:7] */
2427 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2428 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2429 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2430 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2431};
2432static const unsigned int mmc1_data8_mux[] = {
2433 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2434 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2435};
2436static const unsigned int mmc1_ctrl_pins[] = {
2437 /* CLK, CMD */
2438 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2439};
2440static const unsigned int mmc1_ctrl_mux[] = {
2441 MMC1_CLK_MARK, MMC1_CMD_MARK,
2442};
2443
2444/* - SDHI ------------------------------------------------------------------- */
2445static const unsigned int sdhi0_data1_pins[] = {
2446 /* D0 */
2447 RCAR_GP_PIN(3, 2),
2448};
2449static const unsigned int sdhi0_data1_mux[] = {
2450 SD0_DAT0_MARK,
2451};
2452static const unsigned int sdhi0_data4_pins[] = {
2453 /* D[0:3] */
2454 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2455};
2456static const unsigned int sdhi0_data4_mux[] = {
2457 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2458};
2459static const unsigned int sdhi0_ctrl_pins[] = {
2460 /* CLK, CMD */
2461 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2462};
2463static const unsigned int sdhi0_ctrl_mux[] = {
2464 SD0_CLK_MARK, SD0_CMD_MARK,
2465};
2466static const unsigned int sdhi0_cd_pins[] = {
2467 /* CD */
2468 RCAR_GP_PIN(3, 6),
2469};
2470static const unsigned int sdhi0_cd_mux[] = {
2471 SD0_CD_MARK,
2472};
2473static const unsigned int sdhi0_wp_pins[] = {
2474 /* WP */
2475 RCAR_GP_PIN(3, 7),
2476};
2477static const unsigned int sdhi0_wp_mux[] = {
2478 SD0_WP_MARK,
2479};
2480
2481static const unsigned int sdhi1_data1_pins[] = {
2482 /* D0 */
2483 RCAR_GP_PIN(3, 10),
2484};
2485static const unsigned int sdhi1_data1_mux[] = {
2486 SD1_DAT0_MARK,
2487};
2488static const unsigned int sdhi1_data4_pins[] = {
2489 /* D[0:3] */
2490 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2491};
2492static const unsigned int sdhi1_data4_mux[] = {
2493 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2494};
2495static const unsigned int sdhi1_ctrl_pins[] = {
2496 /* CLK, CMD */
2497 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2498};
2499static const unsigned int sdhi1_ctrl_mux[] = {
2500 SD1_CLK_MARK, SD1_CMD_MARK,
2501};
2502static const unsigned int sdhi1_cd_pins[] = {
2503 /* CD */
2504 RCAR_GP_PIN(3, 14),
2505};
2506static const unsigned int sdhi1_cd_mux[] = {
2507 SD1_CD_MARK,
2508};
2509static const unsigned int sdhi1_wp_pins[] = {
2510 /* WP */
2511 RCAR_GP_PIN(3, 15),
2512};
2513static const unsigned int sdhi1_wp_mux[] = {
2514 SD1_WP_MARK,
2515};
2516
2517static const unsigned int sdhi2_data1_pins[] = {
2518 /* D0 */
2519 RCAR_GP_PIN(3, 18),
2520};
2521static const unsigned int sdhi2_data1_mux[] = {
2522 SD2_DAT0_MARK,
2523};
2524static const unsigned int sdhi2_data4_pins[] = {
2525 /* D[0:3] */
2526 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2527};
2528static const unsigned int sdhi2_data4_mux[] = {
2529 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2530};
2531static const unsigned int sdhi2_ctrl_pins[] = {
2532 /* CLK, CMD */
2533 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2534};
2535static const unsigned int sdhi2_ctrl_mux[] = {
2536 SD2_CLK_MARK, SD2_CMD_MARK,
2537};
2538static const unsigned int sdhi2_cd_pins[] = {
2539 /* CD */
2540 RCAR_GP_PIN(3, 22),
2541};
2542static const unsigned int sdhi2_cd_mux[] = {
2543 SD2_CD_MARK,
2544};
2545static const unsigned int sdhi2_wp_pins[] = {
2546 /* WP */
2547 RCAR_GP_PIN(3, 23),
2548};
2549static const unsigned int sdhi2_wp_mux[] = {
2550 SD2_WP_MARK,
2551};
2552
2553static const unsigned int sdhi3_data1_pins[] = {
2554 /* D0 */
2555 RCAR_GP_PIN(3, 26),
2556};
2557static const unsigned int sdhi3_data1_mux[] = {
2558 SD3_DAT0_MARK,
2559};
2560static const unsigned int sdhi3_data4_pins[] = {
2561 /* D[0:3] */
2562 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2563};
2564static const unsigned int sdhi3_data4_mux[] = {
2565 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2566};
2567static const unsigned int sdhi3_ctrl_pins[] = {
2568 /* CLK, CMD */
2569 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2570};
2571static const unsigned int sdhi3_ctrl_mux[] = {
2572 SD3_CLK_MARK, SD3_CMD_MARK,
2573};
2574static const unsigned int sdhi3_cd_pins[] = {
2575 /* CD */
2576 RCAR_GP_PIN(3, 30),
2577};
2578static const unsigned int sdhi3_cd_mux[] = {
2579 SD3_CD_MARK,
2580};
2581static const unsigned int sdhi3_wp_pins[] = {
2582 /* WP */
2583 RCAR_GP_PIN(3, 31),
2584};
2585static const unsigned int sdhi3_wp_mux[] = {
2586 SD3_WP_MARK,
2587};
2588
2589static const struct sh_pfc_pin_group pinmux_groups[] = {
2590 SH_PFC_PIN_GROUP(eth_link),
2591 SH_PFC_PIN_GROUP(eth_magic),
2592 SH_PFC_PIN_GROUP(eth_mdio),
2593 SH_PFC_PIN_GROUP(eth_rmii),
2594 SH_PFC_PIN_GROUP(intc_irq0),
2595 SH_PFC_PIN_GROUP(intc_irq1),
2596 SH_PFC_PIN_GROUP(intc_irq2),
2597 SH_PFC_PIN_GROUP(intc_irq3),
2598 SH_PFC_PIN_GROUP(scif0_data),
2599 SH_PFC_PIN_GROUP(scif0_clk),
2600 SH_PFC_PIN_GROUP(scif0_ctrl),
2601 SH_PFC_PIN_GROUP(scif0_data_b),
2602 SH_PFC_PIN_GROUP(scif1_data),
2603 SH_PFC_PIN_GROUP(scif1_clk),
2604 SH_PFC_PIN_GROUP(scif1_ctrl),
2605 SH_PFC_PIN_GROUP(scif1_data_b),
2606 SH_PFC_PIN_GROUP(scif1_data_c),
2607 SH_PFC_PIN_GROUP(scif1_data_d),
2608 SH_PFC_PIN_GROUP(scif1_clk_d),
2609 SH_PFC_PIN_GROUP(scif1_data_e),
2610 SH_PFC_PIN_GROUP(scif1_clk_e),
2611 SH_PFC_PIN_GROUP(scifa0_data),
2612 SH_PFC_PIN_GROUP(scifa0_clk),
2613 SH_PFC_PIN_GROUP(scifa0_ctrl),
2614 SH_PFC_PIN_GROUP(scifa0_data_b),
2615 SH_PFC_PIN_GROUP(scifa0_clk_b),
2616 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
2617 SH_PFC_PIN_GROUP(scifa1_data),
2618 SH_PFC_PIN_GROUP(scifa1_clk),
2619 SH_PFC_PIN_GROUP(scifa1_ctrl),
2620 SH_PFC_PIN_GROUP(scifa1_data_b),
2621 SH_PFC_PIN_GROUP(scifa1_clk_b),
2622 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
2623 SH_PFC_PIN_GROUP(scifa1_data_c),
2624 SH_PFC_PIN_GROUP(scifa1_clk_c),
2625 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
2626 SH_PFC_PIN_GROUP(scifa1_data_d),
2627 SH_PFC_PIN_GROUP(scifa1_clk_d),
2628 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
2629 SH_PFC_PIN_GROUP(scifa2_data),
2630 SH_PFC_PIN_GROUP(scifa2_clk),
2631 SH_PFC_PIN_GROUP(scifa2_ctrl),
2632 SH_PFC_PIN_GROUP(scifa2_data_b),
2633 SH_PFC_PIN_GROUP(scifa2_data_c),
2634 SH_PFC_PIN_GROUP(scifa2_clk_c),
2635 SH_PFC_PIN_GROUP(scifb0_data),
2636 SH_PFC_PIN_GROUP(scifb0_clk),
2637 SH_PFC_PIN_GROUP(scifb0_ctrl),
2638 SH_PFC_PIN_GROUP(scifb0_data_b),
2639 SH_PFC_PIN_GROUP(scifb0_clk_b),
2640 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
2641 SH_PFC_PIN_GROUP(scifb0_data_c),
2642 SH_PFC_PIN_GROUP(scifb1_data),
2643 SH_PFC_PIN_GROUP(scifb1_clk),
2644 SH_PFC_PIN_GROUP(scifb1_ctrl),
2645 SH_PFC_PIN_GROUP(scifb1_data_b),
2646 SH_PFC_PIN_GROUP(scifb1_clk_b),
2647 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
2648 SH_PFC_PIN_GROUP(scifb1_data_c),
2649 SH_PFC_PIN_GROUP(scifb1_data_d),
2650 SH_PFC_PIN_GROUP(scifb1_data_e),
2651 SH_PFC_PIN_GROUP(scifb1_clk_e),
2652 SH_PFC_PIN_GROUP(scifb1_data_f),
2653 SH_PFC_PIN_GROUP(scifb1_data_g),
2654 SH_PFC_PIN_GROUP(scifb1_clk_g),
2655 SH_PFC_PIN_GROUP(scifb2_data),
2656 SH_PFC_PIN_GROUP(scifb2_clk),
2657 SH_PFC_PIN_GROUP(scifb2_ctrl),
2658 SH_PFC_PIN_GROUP(scifb2_data_b),
2659 SH_PFC_PIN_GROUP(scifb2_clk_b),
2660 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
2661 SH_PFC_PIN_GROUP(scifb2_data_c),
2662 SH_PFC_PIN_GROUP(tpu0_to0),
2663 SH_PFC_PIN_GROUP(tpu0_to1),
2664 SH_PFC_PIN_GROUP(tpu0_to2),
2665 SH_PFC_PIN_GROUP(tpu0_to3),
2666 SH_PFC_PIN_GROUP(mmc0_data1),
2667 SH_PFC_PIN_GROUP(mmc0_data4),
2668 SH_PFC_PIN_GROUP(mmc0_data8),
2669 SH_PFC_PIN_GROUP(mmc0_ctrl),
2670 SH_PFC_PIN_GROUP(mmc1_data1),
2671 SH_PFC_PIN_GROUP(mmc1_data4),
2672 SH_PFC_PIN_GROUP(mmc1_data8),
2673 SH_PFC_PIN_GROUP(mmc1_ctrl),
2674 SH_PFC_PIN_GROUP(sdhi0_data1),
2675 SH_PFC_PIN_GROUP(sdhi0_data4),
2676 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2677 SH_PFC_PIN_GROUP(sdhi0_cd),
2678 SH_PFC_PIN_GROUP(sdhi0_wp),
2679 SH_PFC_PIN_GROUP(sdhi1_data1),
2680 SH_PFC_PIN_GROUP(sdhi1_data4),
2681 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2682 SH_PFC_PIN_GROUP(sdhi1_cd),
2683 SH_PFC_PIN_GROUP(sdhi1_wp),
2684 SH_PFC_PIN_GROUP(sdhi2_data1),
2685 SH_PFC_PIN_GROUP(sdhi2_data4),
2686 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2687 SH_PFC_PIN_GROUP(sdhi2_cd),
2688 SH_PFC_PIN_GROUP(sdhi2_wp),
2689 SH_PFC_PIN_GROUP(sdhi3_data1),
2690 SH_PFC_PIN_GROUP(sdhi3_data4),
2691 SH_PFC_PIN_GROUP(sdhi3_ctrl),
2692 SH_PFC_PIN_GROUP(sdhi3_cd),
2693 SH_PFC_PIN_GROUP(sdhi3_wp),
2694};
2695
2696static const char * const eth_groups[] = {
2697 "eth_link",
2698 "eth_magic",
2699 "eth_mdio",
2700 "eth_rmii",
2701};
2702
2703static const char * const intc_groups[] = {
2704 "intc_irq0",
2705 "intc_irq1",
2706 "intc_irq2",
2707 "intc_irq3",
2708};
2709
2710static const char * const scif0_groups[] = {
2711 "scif0_data",
2712 "scif0_clk",
2713 "scif0_ctrl",
2714 "scif0_data_b",
2715};
2716
2717static const char * const scif1_groups[] = {
2718 "scif1_data",
2719 "scif1_clk",
2720 "scif1_ctrl",
2721 "scif1_data_b",
2722 "scif1_data_c",
2723 "scif1_data_d",
2724 "scif1_clk_d",
2725 "scif1_data_e",
2726 "scif1_clk_e",
2727};
2728
2729static const char * const scifa0_groups[] = {
2730 "scifa0_data",
2731 "scifa0_clk",
2732 "scifa0_ctrl",
2733 "scifa0_data_b",
2734 "scifa0_clk_b",
2735 "scifa0_ctrl_b",
2736};
2737
2738static const char * const scifa1_groups[] = {
2739 "scifa1_data",
2740 "scifa1_clk",
2741 "scifa1_ctrl",
2742 "scifa1_data_b",
2743 "scifa1_clk_b",
2744 "scifa1_ctrl_b",
2745 "scifa1_data_c",
2746 "scifa1_clk_c",
2747 "scifa1_ctrl_c",
2748 "scifa1_data_d",
2749 "scifa1_clk_d",
2750 "scifa1_ctrl_d",
2751};
2752
2753static const char * const scifa2_groups[] = {
2754 "scifa2_data",
2755 "scifa2_clk",
2756 "scifa2_ctrl",
2757 "scifa2_data_b",
2758 "scifa2_data_c",
2759 "scifa2_clk_c",
2760};
2761
2762static const char * const scifb0_groups[] = {
2763 "scifb0_data",
2764 "scifb0_clk",
2765 "scifb0_ctrl",
2766 "scifb0_data_b",
2767 "scifb0_clk_b",
2768 "scifb0_ctrl_b",
2769 "scifb0_data_c",
2770};
2771
2772static const char * const scifb1_groups[] = {
2773 "scifb1_data",
2774 "scifb1_clk",
2775 "scifb1_ctrl",
2776 "scifb1_data_b",
2777 "scifb1_clk_b",
2778 "scifb1_ctrl_b",
2779 "scifb1_data_c",
2780 "scifb1_data_d",
2781 "scifb1_data_e",
2782 "scifb1_clk_e",
2783 "scifb1_data_f",
2784 "scifb1_data_g",
2785 "scifb1_clk_g",
2786};
2787
2788static const char * const scifb2_groups[] = {
2789 "scifb2_data",
2790 "scifb2_clk",
2791 "scifb2_ctrl",
2792 "scifb2_data_b",
2793 "scifb2_clk_b",
2794 "scifb2_ctrl_b",
2795 "scifb2_data_c",
2796};
2797
2798static const char * const tpu0_groups[] = {
2799 "tpu0_to0",
2800 "tpu0_to1",
2801 "tpu0_to2",
2802 "tpu0_to3",
2803};
2804
2805static const char * const mmc0_groups[] = {
2806 "mmc0_data1",
2807 "mmc0_data4",
2808 "mmc0_data8",
2809 "mmc0_ctrl",
2810};
2811
2812static const char * const mmc1_groups[] = {
2813 "mmc1_data1",
2814 "mmc1_data4",
2815 "mmc1_data8",
2816 "mmc1_ctrl",
2817};
2818
2819static const char * const sdhi0_groups[] = {
2820 "sdhi0_data1",
2821 "sdhi0_data4",
2822 "sdhi0_ctrl",
2823 "sdhi0_cd",
2824 "sdhi0_wp",
2825};
2826
2827static const char * const sdhi1_groups[] = {
2828 "sdhi1_data1",
2829 "sdhi1_data4",
2830 "sdhi1_ctrl",
2831 "sdhi1_cd",
2832 "sdhi1_wp",
2833};
2834
2835static const char * const sdhi2_groups[] = {
2836 "sdhi2_data1",
2837 "sdhi2_data4",
2838 "sdhi2_ctrl",
2839 "sdhi2_cd",
2840 "sdhi2_wp",
2841};
2842
2843static const char * const sdhi3_groups[] = {
2844 "sdhi3_data1",
2845 "sdhi3_data4",
2846 "sdhi3_ctrl",
2847 "sdhi3_cd",
2848 "sdhi3_wp",
2849};
2850
2851static const struct sh_pfc_function pinmux_functions[] = {
2852 SH_PFC_FUNCTION(eth),
2853 SH_PFC_FUNCTION(intc),
2854 SH_PFC_FUNCTION(scif0),
2855 SH_PFC_FUNCTION(scif1),
2856 SH_PFC_FUNCTION(scifa0),
2857 SH_PFC_FUNCTION(scifa1),
2858 SH_PFC_FUNCTION(scifa2),
2859 SH_PFC_FUNCTION(scifb0),
2860 SH_PFC_FUNCTION(scifb1),
2861 SH_PFC_FUNCTION(scifb2),
2862 SH_PFC_FUNCTION(tpu0),
2863 SH_PFC_FUNCTION(mmc0),
2864 SH_PFC_FUNCTION(mmc1),
2865 SH_PFC_FUNCTION(sdhi0),
2866 SH_PFC_FUNCTION(sdhi1),
2867 SH_PFC_FUNCTION(sdhi2),
2868 SH_PFC_FUNCTION(sdhi3),
2869};
2870
2871static struct pinmux_cfg_reg pinmux_config_regs[] = {
2872 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
2873 GP_0_31_FN, FN_IP3_17_15,
2874 GP_0_30_FN, FN_IP3_14_12,
2875 GP_0_29_FN, FN_IP3_11_8,
2876 GP_0_28_FN, FN_IP3_7_4,
2877 GP_0_27_FN, FN_IP3_3_0,
2878 GP_0_26_FN, FN_IP2_28_26,
2879 GP_0_25_FN, FN_IP2_25_22,
2880 GP_0_24_FN, FN_IP2_21_18,
2881 GP_0_23_FN, FN_IP2_17_15,
2882 GP_0_22_FN, FN_IP2_14_12,
2883 GP_0_21_FN, FN_IP2_11_9,
2884 GP_0_20_FN, FN_IP2_8_6,
2885 GP_0_19_FN, FN_IP2_5_3,
2886 GP_0_18_FN, FN_IP2_2_0,
2887 GP_0_17_FN, FN_IP1_29_28,
2888 GP_0_16_FN, FN_IP1_27_26,
2889 GP_0_15_FN, FN_IP1_25_22,
2890 GP_0_14_FN, FN_IP1_21_18,
2891 GP_0_13_FN, FN_IP1_17_15,
2892 GP_0_12_FN, FN_IP1_14_12,
2893 GP_0_11_FN, FN_IP1_11_8,
2894 GP_0_10_FN, FN_IP1_7_4,
2895 GP_0_9_FN, FN_IP1_3_0,
2896 GP_0_8_FN, FN_IP0_30_27,
2897 GP_0_7_FN, FN_IP0_26_23,
2898 GP_0_6_FN, FN_IP0_22_20,
2899 GP_0_5_FN, FN_IP0_19_16,
2900 GP_0_4_FN, FN_IP0_15_12,
2901 GP_0_3_FN, FN_IP0_11_9,
2902 GP_0_2_FN, FN_IP0_8_6,
2903 GP_0_1_FN, FN_IP0_5_3,
2904 GP_0_0_FN, FN_IP0_2_0 }
2905 },
2906 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
2907 0, 0,
2908 0, 0,
2909 GP_1_29_FN, FN_IP6_13_11,
2910 GP_1_28_FN, FN_IP6_10_9,
2911 GP_1_27_FN, FN_IP6_8_6,
2912 GP_1_26_FN, FN_IP6_5_3,
2913 GP_1_25_FN, FN_IP6_2_0,
2914 GP_1_24_FN, FN_IP5_29_27,
2915 GP_1_23_FN, FN_IP5_26_24,
2916 GP_1_22_FN, FN_IP5_23_21,
2917 GP_1_21_FN, FN_IP5_20_18,
2918 GP_1_20_FN, FN_IP5_17_15,
2919 GP_1_19_FN, FN_IP5_14_13,
2920 GP_1_18_FN, FN_IP5_12_10,
2921 GP_1_17_FN, FN_IP5_9_6,
2922 GP_1_16_FN, FN_IP5_5_3,
2923 GP_1_15_FN, FN_IP5_2_0,
2924 GP_1_14_FN, FN_IP4_29_27,
2925 GP_1_13_FN, FN_IP4_26_24,
2926 GP_1_12_FN, FN_IP4_23_21,
2927 GP_1_11_FN, FN_IP4_20_18,
2928 GP_1_10_FN, FN_IP4_17_15,
2929 GP_1_9_FN, FN_IP4_14_12,
2930 GP_1_8_FN, FN_IP4_11_9,
2931 GP_1_7_FN, FN_IP4_8_6,
2932 GP_1_6_FN, FN_IP4_5_3,
2933 GP_1_5_FN, FN_IP4_2_0,
2934 GP_1_4_FN, FN_IP3_31_29,
2935 GP_1_3_FN, FN_IP3_28_26,
2936 GP_1_2_FN, FN_IP3_25_23,
2937 GP_1_1_FN, FN_IP3_22_20,
2938 GP_1_0_FN, FN_IP3_19_18, }
2939 },
2940 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
2941 0, 0,
2942 0, 0,
2943 GP_2_29_FN, FN_IP7_15_13,
2944 GP_2_28_FN, FN_IP7_12_10,
2945 GP_2_27_FN, FN_IP7_9_8,
2946 GP_2_26_FN, FN_IP7_7_6,
2947 GP_2_25_FN, FN_IP7_5_3,
2948 GP_2_24_FN, FN_IP7_2_0,
2949 GP_2_23_FN, FN_IP6_31_29,
2950 GP_2_22_FN, FN_IP6_28_26,
2951 GP_2_21_FN, FN_IP6_25_23,
2952 GP_2_20_FN, FN_IP6_22_20,
2953 GP_2_19_FN, FN_IP6_19_17,
2954 GP_2_18_FN, FN_IP6_16_14,
2955 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
2956 GP_2_16_FN, FN_IP8_27,
2957 GP_2_15_FN, FN_IP8_26,
2958 GP_2_14_FN, FN_IP8_25_24,
2959 GP_2_13_FN, FN_IP8_23_22,
2960 GP_2_12_FN, FN_IP8_21_20,
2961 GP_2_11_FN, FN_IP8_19_18,
2962 GP_2_10_FN, FN_IP8_17_16,
2963 GP_2_9_FN, FN_IP8_15_14,
2964 GP_2_8_FN, FN_IP8_13_12,
2965 GP_2_7_FN, FN_IP8_11_10,
2966 GP_2_6_FN, FN_IP8_9_8,
2967 GP_2_5_FN, FN_IP8_7_6,
2968 GP_2_4_FN, FN_IP8_5_4,
2969 GP_2_3_FN, FN_IP8_3_2,
2970 GP_2_2_FN, FN_IP8_1_0,
2971 GP_2_1_FN, FN_IP7_30_29,
2972 GP_2_0_FN, FN_IP7_28_27 }
2973 },
2974 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
2975 GP_3_31_FN, FN_IP11_21_18,
2976 GP_3_30_FN, FN_IP11_17_15,
2977 GP_3_29_FN, FN_IP11_14_13,
2978 GP_3_28_FN, FN_IP11_12_11,
2979 GP_3_27_FN, FN_IP11_10_9,
2980 GP_3_26_FN, FN_IP11_8_7,
2981 GP_3_25_FN, FN_IP11_6_5,
2982 GP_3_24_FN, FN_IP11_4,
2983 GP_3_23_FN, FN_IP11_3_0,
2984 GP_3_22_FN, FN_IP10_29_26,
2985 GP_3_21_FN, FN_IP10_25_23,
2986 GP_3_20_FN, FN_IP10_22_19,
2987 GP_3_19_FN, FN_IP10_18_15,
2988 GP_3_18_FN, FN_IP10_14_11,
2989 GP_3_17_FN, FN_IP10_10_7,
2990 GP_3_16_FN, FN_IP10_6_4,
2991 GP_3_15_FN, FN_IP10_3_0,
2992 GP_3_14_FN, FN_IP9_31_28,
2993 GP_3_13_FN, FN_IP9_27_26,
2994 GP_3_12_FN, FN_IP9_25_24,
2995 GP_3_11_FN, FN_IP9_23_22,
2996 GP_3_10_FN, FN_IP9_21_20,
2997 GP_3_9_FN, FN_IP9_19_18,
2998 GP_3_8_FN, FN_IP9_17_16,
2999 GP_3_7_FN, FN_IP9_15_12,
3000 GP_3_6_FN, FN_IP9_11_8,
3001 GP_3_5_FN, FN_IP9_7_6,
3002 GP_3_4_FN, FN_IP9_5_4,
3003 GP_3_3_FN, FN_IP9_3_2,
3004 GP_3_2_FN, FN_IP9_1_0,
3005 GP_3_1_FN, FN_IP8_30_29,
3006 GP_3_0_FN, FN_IP8_28 }
3007 },
3008 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3009 GP_4_31_FN, FN_IP14_18_16,
3010 GP_4_30_FN, FN_IP14_15_12,
3011 GP_4_29_FN, FN_IP14_11_9,
3012 GP_4_28_FN, FN_IP14_8_6,
3013 GP_4_27_FN, FN_IP14_5_3,
3014 GP_4_26_FN, FN_IP14_2_0,
3015 GP_4_25_FN, FN_IP13_30_29,
3016 GP_4_24_FN, FN_IP13_28_26,
3017 GP_4_23_FN, FN_IP13_25_23,
3018 GP_4_22_FN, FN_IP13_22_19,
3019 GP_4_21_FN, FN_IP13_18_16,
3020 GP_4_20_FN, FN_IP13_15_13,
3021 GP_4_19_FN, FN_IP13_12_10,
3022 GP_4_18_FN, FN_IP13_9_7,
3023 GP_4_17_FN, FN_IP13_6_3,
3024 GP_4_16_FN, FN_IP13_2_0,
3025 GP_4_15_FN, FN_IP12_30_28,
3026 GP_4_14_FN, FN_IP12_27_25,
3027 GP_4_13_FN, FN_IP12_24_23,
3028 GP_4_12_FN, FN_IP12_22_20,
3029 GP_4_11_FN, FN_IP12_19_17,
3030 GP_4_10_FN, FN_IP12_16_14,
3031 GP_4_9_FN, FN_IP12_13_11,
3032 GP_4_8_FN, FN_IP12_10_8,
3033 GP_4_7_FN, FN_IP12_7_6,
3034 GP_4_6_FN, FN_IP12_5_4,
3035 GP_4_5_FN, FN_IP12_3_2,
3036 GP_4_4_FN, FN_IP12_1_0,
3037 GP_4_3_FN, FN_IP11_31_30,
3038 GP_4_2_FN, FN_IP11_29_27,
3039 GP_4_1_FN, FN_IP11_26_24,
3040 GP_4_0_FN, FN_IP11_23_22 }
3041 },
3042 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3043 GP_5_31_FN, FN_IP7_24_22,
3044 GP_5_30_FN, FN_IP7_21_19,
3045 GP_5_29_FN, FN_IP7_18_16,
3046 GP_5_28_FN, FN_DU_DOTCLKIN2,
3047 GP_5_27_FN, FN_IP7_26_25,
3048 GP_5_26_FN, FN_DU_DOTCLKIN0,
3049 GP_5_25_FN, FN_AVS2,
3050 GP_5_24_FN, FN_AVS1,
3051 GP_5_23_FN, FN_USB2_OVC,
3052 GP_5_22_FN, FN_USB2_PWEN,
3053 GP_5_21_FN, FN_IP16_7,
3054 GP_5_20_FN, FN_IP16_6,
3055 GP_5_19_FN, FN_USB0_OVC_VBUS,
3056 GP_5_18_FN, FN_USB0_PWEN,
3057 GP_5_17_FN, FN_IP16_5_3,
3058 GP_5_16_FN, FN_IP16_2_0,
3059 GP_5_15_FN, FN_IP15_29_28,
3060 GP_5_14_FN, FN_IP15_27_26,
3061 GP_5_13_FN, FN_IP15_25_23,
3062 GP_5_12_FN, FN_IP15_22_20,
3063 GP_5_11_FN, FN_IP15_19_18,
3064 GP_5_10_FN, FN_IP15_17_16,
3065 GP_5_9_FN, FN_IP15_15_14,
3066 GP_5_8_FN, FN_IP15_13_12,
3067 GP_5_7_FN, FN_IP15_11_9,
3068 GP_5_6_FN, FN_IP15_8_6,
3069 GP_5_5_FN, FN_IP15_5_3,
3070 GP_5_4_FN, FN_IP15_2_0,
3071 GP_5_3_FN, FN_IP14_30_28,
3072 GP_5_2_FN, FN_IP14_27_25,
3073 GP_5_1_FN, FN_IP14_24_22,
3074 GP_5_0_FN, FN_IP14_21_19 }
3075 },
3076 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3077 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
3078 /* IP0_31 [1] */
3079 0, 0,
3080 /* IP0_30_27 [4] */
3081 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
3082 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
3083 0, 0, 0, 0, 0, 0, 0, 0, 0,
3084 /* IP0_26_23 [4] */
3085 FN_D7, FN_AD_DI_B, FN_SDA2_C,
3086 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
3087 0, 0, 0, 0, 0, 0, 0, 0, 0,
3088 /* IP0_22_20 [3] */
3089 FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
3090 FN_SCL2_CIS_C, 0, 0,
3091 /* IP0_19_16 [4] */
3092 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
3093 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
3094 0, 0, 0, 0, 0, 0, 0, 0, 0,
3095 /* IP0_15_12 [4] */
3096 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
3097 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
3098 0, 0, 0, 0, 0, 0, 0, 0, 0,
3099 /* IP0_11_9 [3] */
3100 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
3101 0, 0, 0,
3102 /* IP0_8_6 [3] */
3103 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
3104 0, 0, 0,
3105 /* IP0_5_3 [3] */
3106 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
3107 0, 0, 0,
3108 /* IP0_2_0 [3] */
3109 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
3110 0, 0, 0, }
3111 },
3112 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3113 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
3114 /* IP1_31_30 [2] */
3115 0, 0, 0, 0,
3116 /* IP1_29_28 [2] */
3117 FN_A1, FN_PWM4, 0, 0,
3118 /* IP1_27_26 [2] */
3119 FN_A0, FN_PWM3, 0, 0,
3120 /* IP1_25_22 [4] */
3121 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
3122 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
3123 0, 0, 0, 0, 0, 0, 0, 0, 0,
3124 /* IP1_21_18 [4] */
3125 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
3126 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
3127 0, 0, 0, 0, 0, 0, 0, 0, 0,
3128 /* IP1_17_15 [3] */
3129 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
3130 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
3131 0, 0, 0,
3132 /* IP1_14_12 [3] */
3133 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
3134 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
3135 0, 0,
3136 /* IP1_11_8 [4] */
3137 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
3138 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
3139 0, 0, 0, 0, 0, 0, 0, 0, 0,
3140 /* IP1_7_4 [4] */
3141 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
3142 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
3143 0, 0, 0, 0, 0, 0, 0, 0, 0,
3144 /* IP1_3_0 [4] */
3145 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
3146 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
3147 0, 0, 0, 0, 0, 0, 0, 0, 0, }
3148 },
3149 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3150 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
3151 /* IP2_31_29 [3] */
3152 0, 0, 0, 0, 0, 0, 0, 0,
3153 /* IP2_28_26 [3] */
3154 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
3155 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
3156 /* IP2_25_22 [4] */
3157 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
3158 FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
3159 0, 0, 0, 0, 0, 0, 0, 0,
3160 /* IP2_21_18 [4] */
3161 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
3162 FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
3163 0, 0, 0, 0, 0, 0, 0, 0,
3164 /* IP2_17_15 [3] */
3165 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
3166 0, 0, 0, 0,
3167 /* IP2_14_12 [3] */
3168 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
3169 /* IP2_11_9 [3] */
3170 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
3171 /* IP2_8_6 [3] */
3172 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
3173 /* IP2_5_3 [3] */
3174 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
3175 /* IP2_2_0 [3] */
3176 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
3177 },
3178 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3179 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
3180 /* IP3_31_29 [3] */
3181 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
3182 0, 0, 0,
3183 /* IP3_28_26 [3] */
3184 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
3185 0, 0, 0, 0,
3186 /* IP3_25_23 [3] */
3187 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
3188 /* IP3_22_20 [3] */
3189 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
3190 /* IP3_19_18 [2] */
3191 FN_A16, FN_ATAWR1_N, 0, 0,
3192 /* IP3_17_15 [3] */
3193 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
3194 0, 0, 0, 0,
3195 /* IP3_14_12 [3] */
3196 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
3197 0, 0, 0, 0,
3198 /* IP3_11_8 [4] */
3199 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
3200 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
3201 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
3202 /* IP3_7_4 [4] */
3203 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
3204 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
3205 0, 0, 0, 0, 0, 0, 0, 0, 0,
3206 /* IP3_3_0 [4] */
3207 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
3208 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
3209 0, 0, 0, 0, 0, 0, 0, 0, }
3210 },
3211 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3212 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3213 /* IP4_31_30 [2] */
3214 0, 0, 0, 0,
3215 /* IP4_29_27 [3] */
3216 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
3217 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
3218 /* IP4_26_24 [3] */
3219 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
3220 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
3221 /* IP4_23_21 [3] */
3222 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
3223 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
3224 /* IP4_20_18 [3] */
3225 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
3226 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
3227 /* IP4_17_15 [3] */
3228 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
3229 0, 0, 0,
3230 /* IP4_14_12 [3] */
3231 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
3232 FN_VI2_FIELD_B, 0, 0,
3233 /* IP4_11_9 [3] */
3234 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
3235 FN_VI2_CLKENB_B, 0, 0,
3236 /* IP4_8_6 [3] */
3237 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
3238 /* IP4_5_3 [3] */
3239 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
3240 /* IP4_2_0 [3] */
3241 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
3242 }
3243 },
3244 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3245 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
3246 /* IP5_31_30 [2] */
3247 0, 0, 0, 0,
3248 /* IP5_29_27 [3] */
3249 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
3250 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
3251 /* IP5_26_24 [3] */
3252 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
3253 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
3254 FN_MSIOF0_SCK_B, 0,
3255 /* IP5_23_21 [3] */
3256 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
3257 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
3258 FN_IERX_C, 0,
3259 /* IP5_20_18 [3] */
3260 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
3261 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
3262 /* IP5_17_15 [3] */
3263 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
3264 FN_INTC_IRQ4_N, 0, 0,
3265 /* IP5_14_13 [2] */
3266 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
3267 /* IP5_12_10 [3] */
3268 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
3269 0, 0,
3270 /* IP5_9_6 [4] */
3271 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
3272 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
3273 FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
3274 /* IP5_5_3 [3] */
3275 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
3276 FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
3277 FN_INTC_EN0_N, FN_SCL1_CIS,
3278 /* IP5_2_0 [3] */
3279 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
3280 FN_VI2_R3, 0, 0, }
3281 },
3282 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3283 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
3284 /* IP6_31_29 [3] */
3285 FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
3286 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
3287 /* IP6_28_26 [3] */
3288 FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
3289 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
3290 /* IP6_25_23 [3] */
3291 FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
3292 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
3293 /* IP6_22_20 [3] */
3294 FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
3295 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
3296 /* IP6_19_17 [3] */
3297 FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
3298 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
3299 /* IP6_16_14 [3] */
3300 FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
3301 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
3302 FN_SCL2_CIS_E, 0,
3303 /* IP6_13_11 [3] */
3304 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
3305 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
3306 /* IP6_10_9 [2] */
3307 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
3308 /* IP6_8_6 [3] */
3309 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
3310 FN_SSI_SDATA8_C, 0, 0, 0,
3311 /* IP6_5_3 [3] */
3312 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
3313 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
3314 /* IP6_2_0 [3] */
3315 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
3316 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
3317 },
3318 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3319 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
3320 /* IP7_31 [1] */
3321 0, 0,
3322 /* IP7_30_29 [2] */
3323 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
3324 FN_MII_RXD2,
3325 /* IP7_28_27 [2] */
3326 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
3327 /* IP7_26_25 [2] */
3328 FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
3329 /* IP7_24_22 [3] */
3330 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
3331 0, 0, 0,
3332 /* IP7_21_19 [3] */
3333 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
3334 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
3335 /* IP7_18_16 [3] */
3336 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
3337 FN_GLO_SS_C, 0, 0, 0,
3338 /* IP7_15_13 [3] */
3339 FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
3340 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
3341 /* IP7_12_10 [3] */
3342 FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
3343 FN_GLO_SCLK_C, 0, 0, 0,
3344 /* IP7_9_8 [2] */
3345 FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
3346 /* IP7_7_6 [2] */
3347 FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
3348 /* IP7_5_3 [3] */
3349 FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
3350 0, 0, 0,
3351 /* IP7_2_0 [3] */
3352 FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
3353 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
3354 },
3355 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3356 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
3357 2, 2, 2, 2, 2, 2, 2) {
3358 /* IP8_31 [1] */
3359 0, 0,
3360 /* IP8_30_29 [2] */
3361 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
3362 /* IP8_28 [1] */
3363 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
3364 /* IP8_27 [1] */
3365 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
3366 /* IP8_26 [1] */
3367 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
3368 /* IP8_25_24 [2] */
3369 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
3370 FN_AVB_MAGIC, FN_MII_MAGIC,
3371 /* IP8_23_22 [2] */
3372 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
3373 /* IP8_21_20 [2] */
3374 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
3375 FN_MII_MDIO,
3376 /* IP8_19_18 [2] */
3377 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
3378 /* IP8_17_16 [2] */
3379 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
3380 /* IP8_15_14 [2] */
3381 FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
3382 /* IP8_13_12 [2] */
3383 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
3384 /* IP8_11_10 [2] */
3385 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
3386 /* IP8_9_8 [2] */
3387 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
3388 /* IP8_7_6 [2] */
3389 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
3390 /* IP8_5_4 [2] */
3391 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
3392 /* IP8_3_2 [2] */
3393 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
3394 /* IP8_1_0 [2] */
3395 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
3396 },
3397 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3398 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
3399 /* IP9_31_28 [4] */
3400 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
3401 FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
3402 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
3403 /* IP9_27_26 [2] */
3404 FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
3405 /* IP9_25_24 [2] */
3406 FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
3407 /* IP9_23_22 [2] */
3408 FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
3409 /* IP9_21_20 [2] */
3410 FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
3411 /* IP9_19_18 [2] */
3412 FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
3413 /* IP9_17_16 [2] */
3414 FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
3415 /* IP9_15_12 [4] */
3416 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
3417 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
3418 FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
3419 /* IP9_11_8 [4] */
3420 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
3421 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
3422 FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
3423 /* IP9_7_6 [2] */
3424 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
3425 /* IP9_5_4 [2] */
3426 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
3427 /* IP9_3_2 [2] */
3428 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
3429 /* IP9_1_0 [2] */
3430 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
3431 },
3432 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3433 2, 4, 3, 4, 4, 4, 4, 3, 4) {
3434 /* IP10_31_30 [2] */
3435 0, 0, 0, 0,
3436 /* IP10_29_26 [4] */
3437 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
3438 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
3439 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
3440 /* IP10_25_23 [3] */
3441 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
3442 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
3443 /* IP10_22_19 [4] */
3444 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
3445 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
3446 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
3447 /* IP10_18_15 [4] */
3448 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
3449 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
3450 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
3451 0, 0, 0, 0, 0, 0,
3452 /* IP10_14_11 [4] */
3453 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
3454 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
3455 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
3456 0, 0, 0, 0, 0, 0, 0,
3457 /* IP10_10_7 [4] */
3458 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
3459 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
3460 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
3461 0, 0, 0, 0, 0, 0, 0,
3462 /* IP10_6_4 [3] */
3463 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
3464 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
3465 FN_VI3_DATA0_B, 0,
3466 /* IP10_3_0 [4] */
3467 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
3468 FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
3469 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
3470 },
3471 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3472 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
3473 /* IP11_31_30 [2] */
3474 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
3475 /* IP11_29_27 [3] */
3476 FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
3477 FN_RDS_CLK_B, 0, 0,
3478 /* IP11_26_24 [3] */
3479 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
3480 0, 0, 0,
3481 /* IP11_23_22 [2] */
3482 FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
3483 /* IP11_21_18 [4] */
3484 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
3485 FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
3486 FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
3487 /* IP11_17_15 [3] */
3488 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
3489 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
3490 /* IP11_14_13 [2] */
3491 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
3492 /* IP11_12_11 [2] */
3493 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
3494 /* IP11_10_9 [2] */
3495 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
3496 /* IP11_8_7 [2] */
3497 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
3498 /* IP11_6_5 [2] */
3499 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
3500 /* IP11_4 [1] */
3501 FN_SD3_CLK, FN_MMC1_CLK,
3502 /* IP11_3_0 [4] */
3503 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
3504 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
3505 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
3506 },
3507 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3508 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3509 /* IP12_31 [1] */
3510 0, 0,
3511 /* IP12_30_28 [3] */
3512 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
3513 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
3514 FN_CAN_DEBUGOUT4, 0, 0,
3515 /* IP12_27_25 [3] */
3516 FN_SSI_SCK5, FN_SCIFB1_SCK,
3517 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
3518 FN_CAN_DEBUGOUT3, 0, 0,
3519 /* IP12_24_23 [2] */
3520 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
3521 FN_CAN_DEBUGOUT2,
3522 /* IP12_22_20 [3] */
3523 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
3524 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
3525 /* IP12_19_17 [3] */
3526 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
3527 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
3528 /* IP12_16_14 [3] */
3529 FN_SSI_SDATA3, FN_STP_ISCLK_0,
3530 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
3531 /* IP12_13_11 [3] */
3532 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
3533 FN_CAN_STEP0, 0, 0, 0,
3534 /* IP12_10_8 [3] */
3535 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
3536 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
3537 /* IP12_7_6 [2] */
3538 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
3539 /* IP12_5_4 [2] */
3540 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
3541 /* IP12_3_2 [2] */
3542 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
3543 /* IP12_1_0 [2] */
3544 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
3545 },
3546 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3547 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
3548 /* IP13_31 [1] */
3549 0, 0,
3550 /* IP13_30_29 [2] */
3551 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
3552 /* IP13_28_26 [3] */
3553 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
3554 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
3555 /* IP13_25_23 [3] */
3556 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
3557 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
3558 /* IP13_22_19 [4] */
3559 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
3560 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
3561 FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
3562 0, 0, 0, 0,
3563 /* IP13_18_16 [3] */
3564 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
3565 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
3566 /* IP13_15_13 [3] */
3567 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
3568 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
3569 /* IP13_12_10 [3] */
3570 FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
3571 FN_CAN_DEBUGOUT8, 0, 0,
3572 /* IP13_9_7 [3] */
3573 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
3574 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
3575 /* IP13_6_3 [4] */
3576 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
3577 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
3578 FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
3579 /* IP13_2_0 [3] */
3580 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
3581 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
3582 },
3583 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
3584 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
3585 /* IP14_30 [1] */
3586 0, 0,
3587 /* IP14_30_28 [3] */
3588 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
3589 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
3590 FN_HRTS0_N_C, 0,
3591 /* IP14_27_25 [3] */
3592 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
3593 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
3594 /* IP14_24_22 [3] */
3595 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
3596 FN_LCDOUT9, 0, 0, 0,
3597 /* IP14_21_19 [3] */
3598 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
3599 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
3600 /* IP14_18_16 [3] */
3601 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
3602 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
3603 /* IP14_15_12 [4] */
3604 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
3605 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
3606 0, 0, 0, 0, 0, 0, 0,
3607 /* IP14_11_9 [3] */
3608 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
3609 0, 0, 0,
3610 /* IP14_8_6 [3] */
3611 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
3612 0, 0, 0,
3613 /* IP14_5_3 [3] */
3614 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
3615 FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
3616 /* IP14_2_0 [3] */
3617 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
3618 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
3619 FN_REMOCON, 0, }
3620 },
3621 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
3622 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
3623 /* IP15_31_30 [2] */
3624 0, 0, 0, 0,
3625 /* IP15_29_28 [2] */
3626 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
3627 /* IP15_27_26 [2] */
3628 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
3629 /* IP15_25_23 [3] */
3630 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
3631 FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
3632 /* IP15_22_20 [3] */
3633 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
3634 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
3635 /* IP15_19_18 [2] */
3636 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
3637 /* IP15_17_16 [2] */
3638 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
3639 /* IP15_15_14 [2] */
3640 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
3641 /* IP15_13_12 [2] */
3642 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
3643 /* IP15_11_9 [3] */
3644 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
3645 0, 0, 0,
3646 /* IP15_8_6 [3] */
3647 FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
3648 FN_SDA2, FN_SDA2_CIS, 0,
3649 /* IP15_5_3 [3] */
3650 FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
3651 FN_SCL2, FN_SCL2_CIS, 0,
3652 /* IP15_2_0 [3] */
3653 FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
3654 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
3655 },
3656 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
3657 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
3658 /* IP16_31_28 [4] */
3659 0, 0, 0, 0, 0, 0, 0, 0,
3660 0, 0, 0, 0, 0, 0, 0, 0,
3661 /* IP16_27_24 [4] */
3662 0, 0, 0, 0, 0, 0, 0, 0,
3663 0, 0, 0, 0, 0, 0, 0, 0,
3664 /* IP16_23_20 [4] */
3665 0, 0, 0, 0, 0, 0, 0, 0,
3666 0, 0, 0, 0, 0, 0, 0, 0,
3667 /* IP16_19_16 [4] */
3668 0, 0, 0, 0, 0, 0, 0, 0,
3669 0, 0, 0, 0, 0, 0, 0, 0,
3670 /* IP16_15_12 [4] */
3671 0, 0, 0, 0, 0, 0, 0, 0,
3672 0, 0, 0, 0, 0, 0, 0, 0,
3673 /* IP16_11_8 [4] */
3674 0, 0, 0, 0, 0, 0, 0, 0,
3675 0, 0, 0, 0, 0, 0, 0, 0,
3676 /* IP16_7 [1] */
3677 FN_USB1_OVC, FN_TCLK1_B,
3678 /* IP16_6 [1] */
3679 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
3680 /* IP16_5_3 [3] */
3681 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
3682 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
3683 /* IP16_2_0 [3] */
3684 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
3685 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
3686 },
3687 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
3688 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
3689 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
3690 /* SEL_SCIF1 [3] */
3691 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
3692 FN_SEL_SCIF1_4, 0, 0, 0,
3693 /* SEL_SCIFB [2] */
3694 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
3695 /* SEL_SCIFB2 [2] */
3696 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
3697 /* SEL_SCIFB1 [3] */
3698 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
3699 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
3700 FN_SEL_SCIFB1_6, 0,
3701 /* SEL_SCIFA1 [2] */
3702 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
3703 FN_SEL_SCIFA1_3,
3704 /* SEL_SCIF0 [1] */
3705 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
3706 /* SEL_SCIFA [1] */
3707 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
3708 /* SEL_SOF1 [1] */
3709 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
3710 /* SEL_SSI7 [2] */
3711 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3712 /* SEL_SSI6 [1] */
3713 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
3714 /* SEL_SSI5 [2] */
3715 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
3716 /* SEL_VI3 [1] */
3717 FN_SEL_VI3_0, FN_SEL_VI3_1,
3718 /* SEL_VI2 [1] */
3719 FN_SEL_VI2_0, FN_SEL_VI2_1,
3720 /* SEL_VI1 [1] */
3721 FN_SEL_VI1_0, FN_SEL_VI1_1,
3722 /* SEL_VI0 [1] */
3723 FN_SEL_VI0_0, FN_SEL_VI0_1,
3724 /* SEL_TSIF1 [2] */
3725 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
3726 /* RESERVED [1] */
3727 0, 0,
3728 /* SEL_LBS [1] */
3729 FN_SEL_LBS_0, FN_SEL_LBS_1,
3730 /* SEL_TSIF0 [2] */
3731 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
3732 /* SEL_SOF3 [1] */
3733 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
3734 /* SEL_SOF0 [1] */
3735 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
3736 },
3737 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3738 3, 1, 1, 1, 2, 1, 2, 1, 2,
3739 1, 1, 1, 3, 3, 2, 3, 2, 2) {
3740 /* RESERVED [3] */
3741 0, 0, 0, 0, 0, 0, 0, 0,
3742 /* SEL_TMU1 [1] */
3743 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
3744 /* SEL_HSCIF1 [1] */
3745 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3746 /* SEL_SCIFCLK [1] */
3747 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3748 /* SEL_CAN0 [2] */
3749 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3750 /* SEL_CANCLK [1] */
3751 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
3752 /* SEL_SCIFA2 [2] */
3753 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
3754 /* SEL_CAN1 [1] */
3755 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
3756 /* RESERVED [2] */
3757 0, 0, 0, 0,
3758 /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
3759 0, 0,
3760 /* SEL_ADI [1] */
3761 FN_SEL_ADI_0, FN_SEL_ADI_1,
3762 /* SEL_SSP [1] */
3763 FN_SEL_SSP_0, FN_SEL_SSP_1,
3764 /* SEL_FM [3] */
3765 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
3766 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
3767 /* SEL_HSCIF0 [3] */
3768 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
3769 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
3770 /* SEL_GPS [2] */
3771 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
3772 /* SEL_RDS [3] */
3773 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
3774 FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
3775 /* SEL_SIM [2] */
3776 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
3777 /* SEL_SSI8 [2] */
3778 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
3779 },
3780 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
3781 1, 1, 2, 4, 4, 2, 2,
3782 4, 2, 3, 2, 3, 2) {
3783 /* SEL_IICDVFS [1] */
3784 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
3785 /* SEL_IIC0 [1] */
3786 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
3787 /* RESERVED [2] */
3788 0, 0, 0, 0,
3789 /* RESERVED [4] */
3790 0, 0, 0, 0, 0, 0, 0, 0,
3791 0, 0, 0, 0, 0, 0, 0, 0,
3792 /* RESERVED [4] */
3793 0, 0, 0, 0, 0, 0, 0, 0,
3794 0, 0, 0, 0, 0, 0, 0, 0,
3795 /* RESERVED [2] */
3796 0, 0, 0, 0,
3797 /* SEL_IEB [2] */
3798 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
3799 /* RESERVED [4] */
3800 0, 0, 0, 0, 0, 0, 0, 0,
3801 0, 0, 0, 0, 0, 0, 0, 0,
3802 /* RESERVED [2] */
3803 0, 0, 0, 0,
3804 /* SEL_IIC2 [3] */
3805 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
3806 FN_SEL_IIC2_4, 0, 0, 0,
3807 /* SEL_IIC1 [2] */
3808 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
3809 /* SEL_I2C2 [3] */
3810 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3811 FN_SEL_I2C2_4, 0, 0, 0,
3812 /* SEL_I2C1 [2] */
3813 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
3814 },
3815 { },
3816};
3817
3818const struct sh_pfc_soc_info r8a7790_pinmux_info = {
3819 .name = "r8a77900_pfc",
3820 .unlock_reg = 0xe6060000, /* PMMR */
3821
3822 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3823
3824 .pins = pinmux_pins,
3825 .nr_pins = ARRAY_SIZE(pinmux_pins),
3826 .groups = pinmux_groups,
3827 .nr_groups = ARRAY_SIZE(pinmux_groups),
3828 .functions = pinmux_functions,
3829 .nr_functions = ARRAY_SIZE(pinmux_functions),
3830
3831 .cfg_regs = pinmux_config_regs,
3832
3833 .gpio_data = pinmux_data,
3834 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3835};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 22:08:29 -0500