aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl/qcom
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pinctrl/qcom')
-rw-r--r--drivers/pinctrl/qcom/Kconfig8
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8084.c1243
3 files changed, 1252 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d160a710d704..81275af9638b 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -15,6 +15,14 @@ config PINCTRL_APQ8064
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform. 16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
17 17
18config PINCTRL_APQ8084
19 tristate "Qualcomm APQ8084 pin controller driver"
20 depends on GPIOLIB && OF
21 select PINCTRL_MSM
22 help
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
24 Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
25
18config PINCTRL_IPQ8064 26config PINCTRL_IPQ8064
19 tristate "Qualcomm IPQ8064 pin controller driver" 27 tristate "Qualcomm IPQ8064 pin controller driver"
20 depends on GPIOLIB && OF 28 depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 2a02602d715c..ba8519fcd8d3 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -1,6 +1,7 @@
1# Qualcomm pin control drivers 1# Qualcomm pin control drivers
2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o 2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o 3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
4obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
4obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o 5obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
5obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o 6obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
6obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o 7obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c
new file mode 100644
index 000000000000..5362959c448f
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -0,0 +1,1243 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc apq8084_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169 PINCTRL_PIN(146, "GPIO_146"),
170
171 PINCTRL_PIN(147, "SDC1_CLK"),
172 PINCTRL_PIN(148, "SDC1_CMD"),
173 PINCTRL_PIN(149, "SDC1_DATA"),
174 PINCTRL_PIN(150, "SDC2_CLK"),
175 PINCTRL_PIN(151, "SDC2_CMD"),
176 PINCTRL_PIN(152, "SDC2_DATA"),
177};
178
179#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
180
181DECLARE_APQ_GPIO_PINS(0);
182DECLARE_APQ_GPIO_PINS(1);
183DECLARE_APQ_GPIO_PINS(2);
184DECLARE_APQ_GPIO_PINS(3);
185DECLARE_APQ_GPIO_PINS(4);
186DECLARE_APQ_GPIO_PINS(5);
187DECLARE_APQ_GPIO_PINS(6);
188DECLARE_APQ_GPIO_PINS(7);
189DECLARE_APQ_GPIO_PINS(8);
190DECLARE_APQ_GPIO_PINS(9);
191DECLARE_APQ_GPIO_PINS(10);
192DECLARE_APQ_GPIO_PINS(11);
193DECLARE_APQ_GPIO_PINS(12);
194DECLARE_APQ_GPIO_PINS(13);
195DECLARE_APQ_GPIO_PINS(14);
196DECLARE_APQ_GPIO_PINS(15);
197DECLARE_APQ_GPIO_PINS(16);
198DECLARE_APQ_GPIO_PINS(17);
199DECLARE_APQ_GPIO_PINS(18);
200DECLARE_APQ_GPIO_PINS(19);
201DECLARE_APQ_GPIO_PINS(20);
202DECLARE_APQ_GPIO_PINS(21);
203DECLARE_APQ_GPIO_PINS(22);
204DECLARE_APQ_GPIO_PINS(23);
205DECLARE_APQ_GPIO_PINS(24);
206DECLARE_APQ_GPIO_PINS(25);
207DECLARE_APQ_GPIO_PINS(26);
208DECLARE_APQ_GPIO_PINS(27);
209DECLARE_APQ_GPIO_PINS(28);
210DECLARE_APQ_GPIO_PINS(29);
211DECLARE_APQ_GPIO_PINS(30);
212DECLARE_APQ_GPIO_PINS(31);
213DECLARE_APQ_GPIO_PINS(32);
214DECLARE_APQ_GPIO_PINS(33);
215DECLARE_APQ_GPIO_PINS(34);
216DECLARE_APQ_GPIO_PINS(35);
217DECLARE_APQ_GPIO_PINS(36);
218DECLARE_APQ_GPIO_PINS(37);
219DECLARE_APQ_GPIO_PINS(38);
220DECLARE_APQ_GPIO_PINS(39);
221DECLARE_APQ_GPIO_PINS(40);
222DECLARE_APQ_GPIO_PINS(41);
223DECLARE_APQ_GPIO_PINS(42);
224DECLARE_APQ_GPIO_PINS(43);
225DECLARE_APQ_GPIO_PINS(44);
226DECLARE_APQ_GPIO_PINS(45);
227DECLARE_APQ_GPIO_PINS(46);
228DECLARE_APQ_GPIO_PINS(47);
229DECLARE_APQ_GPIO_PINS(48);
230DECLARE_APQ_GPIO_PINS(49);
231DECLARE_APQ_GPIO_PINS(50);
232DECLARE_APQ_GPIO_PINS(51);
233DECLARE_APQ_GPIO_PINS(52);
234DECLARE_APQ_GPIO_PINS(53);
235DECLARE_APQ_GPIO_PINS(54);
236DECLARE_APQ_GPIO_PINS(55);
237DECLARE_APQ_GPIO_PINS(56);
238DECLARE_APQ_GPIO_PINS(57);
239DECLARE_APQ_GPIO_PINS(58);
240DECLARE_APQ_GPIO_PINS(59);
241DECLARE_APQ_GPIO_PINS(60);
242DECLARE_APQ_GPIO_PINS(61);
243DECLARE_APQ_GPIO_PINS(62);
244DECLARE_APQ_GPIO_PINS(63);
245DECLARE_APQ_GPIO_PINS(64);
246DECLARE_APQ_GPIO_PINS(65);
247DECLARE_APQ_GPIO_PINS(66);
248DECLARE_APQ_GPIO_PINS(67);
249DECLARE_APQ_GPIO_PINS(68);
250DECLARE_APQ_GPIO_PINS(69);
251DECLARE_APQ_GPIO_PINS(70);
252DECLARE_APQ_GPIO_PINS(71);
253DECLARE_APQ_GPIO_PINS(72);
254DECLARE_APQ_GPIO_PINS(73);
255DECLARE_APQ_GPIO_PINS(74);
256DECLARE_APQ_GPIO_PINS(75);
257DECLARE_APQ_GPIO_PINS(76);
258DECLARE_APQ_GPIO_PINS(77);
259DECLARE_APQ_GPIO_PINS(78);
260DECLARE_APQ_GPIO_PINS(79);
261DECLARE_APQ_GPIO_PINS(80);
262DECLARE_APQ_GPIO_PINS(81);
263DECLARE_APQ_GPIO_PINS(82);
264DECLARE_APQ_GPIO_PINS(83);
265DECLARE_APQ_GPIO_PINS(84);
266DECLARE_APQ_GPIO_PINS(85);
267DECLARE_APQ_GPIO_PINS(86);
268DECLARE_APQ_GPIO_PINS(87);
269DECLARE_APQ_GPIO_PINS(88);
270DECLARE_APQ_GPIO_PINS(89);
271DECLARE_APQ_GPIO_PINS(90);
272DECLARE_APQ_GPIO_PINS(91);
273DECLARE_APQ_GPIO_PINS(92);
274DECLARE_APQ_GPIO_PINS(93);
275DECLARE_APQ_GPIO_PINS(94);
276DECLARE_APQ_GPIO_PINS(95);
277DECLARE_APQ_GPIO_PINS(96);
278DECLARE_APQ_GPIO_PINS(97);
279DECLARE_APQ_GPIO_PINS(98);
280DECLARE_APQ_GPIO_PINS(99);
281DECLARE_APQ_GPIO_PINS(100);
282DECLARE_APQ_GPIO_PINS(101);
283DECLARE_APQ_GPIO_PINS(102);
284DECLARE_APQ_GPIO_PINS(103);
285DECLARE_APQ_GPIO_PINS(104);
286DECLARE_APQ_GPIO_PINS(105);
287DECLARE_APQ_GPIO_PINS(106);
288DECLARE_APQ_GPIO_PINS(107);
289DECLARE_APQ_GPIO_PINS(108);
290DECLARE_APQ_GPIO_PINS(109);
291DECLARE_APQ_GPIO_PINS(110);
292DECLARE_APQ_GPIO_PINS(111);
293DECLARE_APQ_GPIO_PINS(112);
294DECLARE_APQ_GPIO_PINS(113);
295DECLARE_APQ_GPIO_PINS(114);
296DECLARE_APQ_GPIO_PINS(115);
297DECLARE_APQ_GPIO_PINS(116);
298DECLARE_APQ_GPIO_PINS(117);
299DECLARE_APQ_GPIO_PINS(118);
300DECLARE_APQ_GPIO_PINS(119);
301DECLARE_APQ_GPIO_PINS(120);
302DECLARE_APQ_GPIO_PINS(121);
303DECLARE_APQ_GPIO_PINS(122);
304DECLARE_APQ_GPIO_PINS(123);
305DECLARE_APQ_GPIO_PINS(124);
306DECLARE_APQ_GPIO_PINS(125);
307DECLARE_APQ_GPIO_PINS(126);
308DECLARE_APQ_GPIO_PINS(127);
309DECLARE_APQ_GPIO_PINS(128);
310DECLARE_APQ_GPIO_PINS(129);
311DECLARE_APQ_GPIO_PINS(130);
312DECLARE_APQ_GPIO_PINS(131);
313DECLARE_APQ_GPIO_PINS(132);
314DECLARE_APQ_GPIO_PINS(133);
315DECLARE_APQ_GPIO_PINS(134);
316DECLARE_APQ_GPIO_PINS(135);
317DECLARE_APQ_GPIO_PINS(136);
318DECLARE_APQ_GPIO_PINS(137);
319DECLARE_APQ_GPIO_PINS(138);
320DECLARE_APQ_GPIO_PINS(139);
321DECLARE_APQ_GPIO_PINS(140);
322DECLARE_APQ_GPIO_PINS(141);
323DECLARE_APQ_GPIO_PINS(142);
324DECLARE_APQ_GPIO_PINS(143);
325DECLARE_APQ_GPIO_PINS(144);
326DECLARE_APQ_GPIO_PINS(145);
327DECLARE_APQ_GPIO_PINS(146);
328
329static const unsigned int sdc1_clk_pins[] = { 147 };
330static const unsigned int sdc1_cmd_pins[] = { 148 };
331static const unsigned int sdc1_data_pins[] = { 149 };
332static const unsigned int sdc2_clk_pins[] = { 150 };
333static const unsigned int sdc2_cmd_pins[] = { 151 };
334static const unsigned int sdc2_data_pins[] = { 152 };
335
336#define FUNCTION(fname) \
337 [APQ_MUX_##fname] = { \
338 .name = #fname, \
339 .groups = fname##_groups, \
340 .ngroups = ARRAY_SIZE(fname##_groups), \
341 }
342
343#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
344 { \
345 .name = "gpio" #id, \
346 .pins = gpio##id##_pins, \
347 .npins = ARRAY_SIZE(gpio##id##_pins), \
348 .funcs = (int[]){ \
349 APQ_MUX_gpio, \
350 APQ_MUX_##f1, \
351 APQ_MUX_##f2, \
352 APQ_MUX_##f3, \
353 APQ_MUX_##f4, \
354 APQ_MUX_##f5, \
355 APQ_MUX_##f6, \
356 APQ_MUX_##f7 \
357 }, \
358 .nfuncs = 8, \
359 .ctl_reg = 0x1000 + 0x10 * id, \
360 .io_reg = 0x1004 + 0x10 * id, \
361 .intr_cfg_reg = 0x1008 + 0x10 * id, \
362 .intr_status_reg = 0x100c + 0x10 * id, \
363 .intr_target_reg = 0x1008 + 0x10 * id, \
364 .mux_bit = 2, \
365 .pull_bit = 0, \
366 .drv_bit = 6, \
367 .oe_bit = 9, \
368 .in_bit = 0, \
369 .out_bit = 1, \
370 .intr_enable_bit = 0, \
371 .intr_status_bit = 0, \
372 .intr_ack_high = 0, \
373 .intr_target_bit = 5, \
374 .intr_raw_status_bit = 4, \
375 .intr_polarity_bit = 1, \
376 .intr_detection_bit = 2, \
377 .intr_detection_width = 2, \
378 }
379
380#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
381 { \
382 .name = #pg_name, \
383 .pins = pg_name##_pins, \
384 .npins = ARRAY_SIZE(pg_name##_pins), \
385 .ctl_reg = ctl, \
386 .io_reg = 0, \
387 .intr_cfg_reg = 0, \
388 .intr_status_reg = 0, \
389 .intr_target_reg = 0, \
390 .mux_bit = -1, \
391 .pull_bit = pull, \
392 .drv_bit = drv, \
393 .oe_bit = -1, \
394 .in_bit = -1, \
395 .out_bit = -1, \
396 .intr_enable_bit = -1, \
397 .intr_status_bit = -1, \
398 .intr_target_bit = -1, \
399 .intr_raw_status_bit = -1, \
400 .intr_polarity_bit = -1, \
401 .intr_detection_bit = -1, \
402 .intr_detection_width = -1, \
403 }
404
405enum apq8084_functions {
406 APQ_MUX_adsp_ext,
407 APQ_MUX_audio_ref,
408 APQ_MUX_blsp_i2c1,
409 APQ_MUX_blsp_i2c2,
410 APQ_MUX_blsp_i2c3,
411 APQ_MUX_blsp_i2c4,
412 APQ_MUX_blsp_i2c5,
413 APQ_MUX_blsp_i2c6,
414 APQ_MUX_blsp_i2c7,
415 APQ_MUX_blsp_i2c8,
416 APQ_MUX_blsp_i2c9,
417 APQ_MUX_blsp_i2c10,
418 APQ_MUX_blsp_i2c11,
419 APQ_MUX_blsp_i2c12,
420 APQ_MUX_blsp_spi1,
421 APQ_MUX_blsp_spi1_cs1,
422 APQ_MUX_blsp_spi1_cs2,
423 APQ_MUX_blsp_spi1_cs3,
424 APQ_MUX_blsp_spi2,
425 APQ_MUX_blsp_spi3,
426 APQ_MUX_blsp_spi3_cs1,
427 APQ_MUX_blsp_spi3_cs2,
428 APQ_MUX_blsp_spi3_cs3,
429 APQ_MUX_blsp_spi4,
430 APQ_MUX_blsp_spi5,
431 APQ_MUX_blsp_spi6,
432 APQ_MUX_blsp_spi7,
433 APQ_MUX_blsp_spi8,
434 APQ_MUX_blsp_spi9,
435 APQ_MUX_blsp_spi10,
436 APQ_MUX_blsp_spi10_cs1,
437 APQ_MUX_blsp_spi10_cs2,
438 APQ_MUX_blsp_spi10_cs3,
439 APQ_MUX_blsp_spi11,
440 APQ_MUX_blsp_spi12,
441 APQ_MUX_blsp_uart1,
442 APQ_MUX_blsp_uart2,
443 APQ_MUX_blsp_uart3,
444 APQ_MUX_blsp_uart4,
445 APQ_MUX_blsp_uart5,
446 APQ_MUX_blsp_uart6,
447 APQ_MUX_blsp_uart7,
448 APQ_MUX_blsp_uart8,
449 APQ_MUX_blsp_uart9,
450 APQ_MUX_blsp_uart10,
451 APQ_MUX_blsp_uart11,
452 APQ_MUX_blsp_uart12,
453 APQ_MUX_blsp_uim1,
454 APQ_MUX_blsp_uim2,
455 APQ_MUX_blsp_uim3,
456 APQ_MUX_blsp_uim4,
457 APQ_MUX_blsp_uim5,
458 APQ_MUX_blsp_uim6,
459 APQ_MUX_blsp_uim7,
460 APQ_MUX_blsp_uim8,
461 APQ_MUX_blsp_uim9,
462 APQ_MUX_blsp_uim10,
463 APQ_MUX_blsp_uim11,
464 APQ_MUX_blsp_uim12,
465 APQ_MUX_cam_mclk0,
466 APQ_MUX_cam_mclk1,
467 APQ_MUX_cam_mclk2,
468 APQ_MUX_cam_mclk3,
469 APQ_MUX_cci_async,
470 APQ_MUX_cci_async_in0,
471 APQ_MUX_cci_i2c0,
472 APQ_MUX_cci_i2c1,
473 APQ_MUX_cci_timer0,
474 APQ_MUX_cci_timer1,
475 APQ_MUX_cci_timer2,
476 APQ_MUX_cci_timer3,
477 APQ_MUX_cci_timer4,
478 APQ_MUX_edp_hpd,
479 APQ_MUX_gcc_gp1,
480 APQ_MUX_gcc_gp2,
481 APQ_MUX_gcc_gp3,
482 APQ_MUX_gcc_obt,
483 APQ_MUX_gcc_vtt,
484 APQ_MUX_gp_mn,
485 APQ_MUX_gp_pdm0,
486 APQ_MUX_gp_pdm1,
487 APQ_MUX_gp_pdm2,
488 APQ_MUX_gp0_clk,
489 APQ_MUX_gp1_clk,
490 APQ_MUX_gpio,
491 APQ_MUX_hdmi_cec,
492 APQ_MUX_hdmi_ddc,
493 APQ_MUX_hdmi_dtest,
494 APQ_MUX_hdmi_hpd,
495 APQ_MUX_hdmi_rcv,
496 APQ_MUX_hsic,
497 APQ_MUX_ldo_en,
498 APQ_MUX_ldo_update,
499 APQ_MUX_mdp_vsync,
500 APQ_MUX_pci_e0,
501 APQ_MUX_pci_e0_n,
502 APQ_MUX_pci_e0_rst,
503 APQ_MUX_pci_e1,
504 APQ_MUX_pci_e1_rst,
505 APQ_MUX_pci_e1_rst_n,
506 APQ_MUX_pci_e1_clkreq_n,
507 APQ_MUX_pri_mi2s,
508 APQ_MUX_qua_mi2s,
509 APQ_MUX_sata_act,
510 APQ_MUX_sata_devsleep,
511 APQ_MUX_sata_devsleep_n,
512 APQ_MUX_sd_write,
513 APQ_MUX_sdc_emmc_mode,
514 APQ_MUX_sdc3,
515 APQ_MUX_sdc4,
516 APQ_MUX_sec_mi2s,
517 APQ_MUX_slimbus,
518 APQ_MUX_spdif_tx,
519 APQ_MUX_spkr_i2s,
520 APQ_MUX_spkr_i2s_ws,
521 APQ_MUX_spss_geni,
522 APQ_MUX_ter_mi2s,
523 APQ_MUX_tsif1,
524 APQ_MUX_tsif2,
525 APQ_MUX_uim,
526 APQ_MUX_uim_batt_alarm,
527 APQ_MUX_NA,
528};
529
530static const char * const gpio_groups[] = {
531 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
532 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
533 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
534 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
535 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
536 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
537 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
538 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
539 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
540 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
541 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
542 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
543 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
544 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
545 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
546 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
547 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
548 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
549 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
550 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
551 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
552 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146"
553};
554
555static const char * const adsp_ext_groups[] = {
556 "gpio34"
557};
558static const char * const audio_ref_groups[] = {
559 "gpio100"
560};
561static const char * const blsp_i2c1_groups[] = {
562 "gpio2", "gpio3"
563};
564static const char * const blsp_i2c2_groups[] = {
565 "gpio6", "gpio7"
566};
567static const char * const blsp_i2c3_groups[] = {
568 "gpio10", "gpio11"
569};
570static const char * const blsp_i2c4_groups[] = {
571 "gpio29", "gpio30"
572};
573static const char * const blsp_i2c5_groups[] = {
574 "gpio41", "gpio42"
575};
576static const char * const blsp_i2c6_groups[] = {
577 "gpio45", "gpio46"
578};
579static const char * const blsp_i2c7_groups[] = {
580 "gpio132", "gpio133"
581};
582static const char * const blsp_i2c8_groups[] = {
583 "gpio53", "gpio54"
584};
585static const char * const blsp_i2c9_groups[] = {
586 "gpio57", "gpio58"
587};
588static const char * const blsp_i2c10_groups[] = {
589 "gpio61", "gpio62"
590};
591static const char * const blsp_i2c11_groups[] = {
592 "gpio65", "gpio66"
593};
594static const char * const blsp_i2c12_groups[] = {
595 "gpio49", "gpio50"
596};
597static const char * const blsp_spi1_groups[] = {
598 "gpio0", "gpio1", "gpio2", "gpio3"
599};
600static const char * const blsp_spi2_groups[] = {
601 "gpio4", "gpio5", "gpio6", "gpio7"
602};
603static const char * const blsp_spi3_groups[] = {
604 "gpio8", "gpio9", "gpio10", "gpio11"
605};
606static const char * const blsp_spi4_groups[] = {
607 "gpio27", "gpio28", "gpio29", "gpio30"
608};
609static const char * const blsp_spi5_groups[] = {
610 "gpio39", "gpio40", "gpio41", "gpio42"
611};
612static const char * const blsp_spi6_groups[] = {
613 "gpio43", "gpio44", "gpio45", "gpio46"
614};
615static const char * const blsp_spi7_groups[] = {
616 "gpio130", "gpio131", "gpio132", "gpio133"
617};
618static const char * const blsp_spi8_groups[] = {
619 "gpio51", "gpio52", "gpio53", "gpio54"
620};
621static const char * const blsp_spi9_groups[] = {
622 "gpio55", "gpio56", "gpio57", "gpio58"
623};
624static const char * const blsp_spi10_groups[] = {
625 "gpio59", "gpio60", "gpio61", "gpio62"
626};
627static const char * const blsp_spi11_groups[] = {
628 "gpio63", "gpio64", "gpio65", "gpio66"
629};
630static const char * const blsp_spi12_groups[] = {
631 "gpio47", "gpio48", "gpio49", "gpio50"
632};
633static const char * const blsp_uart1_groups[] = {
634 "gpio0", "gpio1", "gpio2", "gpio3"
635};
636static const char * const blsp_uart2_groups[] = {
637 "gpio4", "gpio5", "gpio6", "gpio7"
638};
639static const char * const blsp_uart3_groups[] = {
640 "gpio8"
641};
642static const char * const blsp_uart4_groups[] = {
643 "gpio27", "gpio28", "gpio29", "gpio30"
644};
645static const char * const blsp_uart5_groups[] = {
646 "gpio39", "gpio40", "gpio41", "gpio42"
647};
648static const char * const blsp_uart6_groups[] = {
649 "gpio43", "gpio44", "gpio45", "gpio46"
650};
651static const char * const blsp_uart7_groups[] = {
652 "gpio130", "gpio131", "gpio132", "gpio133"
653};
654static const char * const blsp_uart8_groups[] = {
655 "gpio51", "gpio52", "gpio53", "gpio54"
656};
657static const char * const blsp_uart9_groups[] = {
658 "gpio55", "gpio56", "gpio57", "gpio58"
659};
660static const char * const blsp_uart10_groups[] = {
661 "gpio59", "gpio60", "gpio61", "gpio62"
662};
663static const char * const blsp_uart11_groups[] = {
664 "gpio63", "gpio64", "gpio65", "gpio66"
665};
666static const char * const blsp_uart12_groups[] = {
667 "gpio47", "gpio48", "gpio49", "gpio50"
668};
669static const char * const blsp_uim1_groups[] = {
670 "gpio0", "gpio1"
671};
672static const char * const blsp_uim2_groups[] = {
673 "gpio4", "gpio5"
674};
675static const char * const blsp_uim3_groups[] = {
676 "gpio8", "gpio9"
677};
678static const char * const blsp_uim4_groups[] = {
679 "gpio27", "gpio28"
680};
681static const char * const blsp_uim5_groups[] = {
682 "gpio39", "gpio40"
683};
684static const char * const blsp_uim6_groups[] = {
685 "gpio43", "gpio44"
686};
687static const char * const blsp_uim7_groups[] = {
688 "gpio130", "gpio131"
689};
690static const char * const blsp_uim8_groups[] = {
691 "gpio51", "gpio52"
692};
693static const char * const blsp_uim9_groups[] = {
694 "gpio55", "gpio56"
695};
696static const char * const blsp_uim10_groups[] = {
697 "gpio59", "gpio60"
698};
699static const char * const blsp_uim11_groups[] = {
700 "gpio63", "gpio64"
701};
702static const char * const blsp_uim12_groups[] = {
703 "gpio47", "gpio48"
704};
705static const char * const blsp_spi1_cs1_groups[] = {
706 "gpio116"
707};
708static const char * const blsp_spi1_cs2_groups[] = {
709 "gpio117"
710};
711static const char * const blsp_spi1_cs3_groups[] = {
712 "gpio118"
713};
714static const char * const blsp_spi3_cs1_groups[] = {
715 "gpio67"
716};
717static const char * const blsp_spi3_cs2_groups[] = {
718 "gpio71"
719};
720static const char * const blsp_spi3_cs3_groups[] = {
721 "gpio72"
722};
723static const char * const blsp_spi10_cs1_groups[] = {
724 "gpio106"
725};
726static const char * const blsp_spi10_cs2_groups[] = {
727 "gpio111"
728};
729static const char * const blsp_spi10_cs3_groups[] = {
730 "gpio128"
731};
732static const char * const cam_mclk0_groups[] = {
733 "gpio15"
734};
735static const char * const cam_mclk1_groups[] = {
736 "gpio16"
737};
738static const char * const cam_mclk2_groups[] = {
739 "gpio17"
740};
741static const char * const cam_mclk3_groups[] = {
742 "gpio18"
743};
744static const char * const cci_async_groups[] = {
745 "gpio26", "gpio119"
746};
747static const char * const cci_async_in0_groups[] = {
748 "gpio120"
749};
750static const char * const cci_i2c0_groups[] = {
751 "gpio19", "gpio20"
752};
753static const char * const cci_i2c1_groups[] = {
754 "gpio21", "gpio22"
755};
756static const char * const cci_timer0_groups[] = {
757 "gpio23"
758};
759static const char * const cci_timer1_groups[] = {
760 "gpio24"
761};
762static const char * const cci_timer2_groups[] = {
763 "gpio25"
764};
765static const char * const cci_timer3_groups[] = {
766 "gpio26"
767};
768static const char * const cci_timer4_groups[] = {
769 "gpio119"
770};
771static const char * const edp_hpd_groups[] = {
772 "gpio103"
773};
774static const char * const gcc_gp1_groups[] = {
775 "gpio37"
776};
777static const char * const gcc_gp2_groups[] = {
778 "gpio38"
779};
780static const char * const gcc_gp3_groups[] = {
781 "gpio86"
782};
783static const char * const gcc_obt_groups[] = {
784 "gpio127"
785};
786static const char * const gcc_vtt_groups[] = {
787 "gpio126"
788};
789static const char * const gp_mn_groups[] = {
790 "gpio29"
791};
792static const char * const gp_pdm0_groups[] = {
793 "gpio48", "gpio83"
794};
795static const char * const gp_pdm1_groups[] = {
796 "gpio84", "gpio101"
797};
798static const char * const gp_pdm2_groups[] = {
799 "gpio85", "gpio110"
800};
801static const char * const gp0_clk_groups[] = {
802 "gpio25"
803};
804static const char * const gp1_clk_groups[] = {
805 "gpio26"
806};
807static const char * const hdmi_cec_groups[] = {
808 "gpio31"
809};
810static const char * const hdmi_ddc_groups[] = {
811 "gpio32", "gpio33"
812};
813static const char * const hdmi_dtest_groups[] = {
814 "gpio123"
815};
816static const char * const hdmi_hpd_groups[] = {
817 "gpio34"
818};
819static const char * const hdmi_rcv_groups[] = {
820 "gpio125"
821};
822static const char * const hsic_groups[] = {
823 "gpio134", "gpio135"
824};
825static const char * const ldo_en_groups[] = {
826 "gpio124"
827};
828static const char * const ldo_update_groups[] = {
829 "gpio125"
830};
831static const char * const mdp_vsync_groups[] = {
832 "gpio12", "gpio13", "gpio14"
833};
834static const char * const pci_e0_groups[] = {
835 "gpio68", "gpio70"
836};
837static const char * const pci_e0_n_groups[] = {
838 "gpio68", "gpio70"
839};
840static const char * const pci_e0_rst_groups[] = {
841 "gpio70"
842};
843static const char * const pci_e1_groups[] = {
844 "gpio140"
845};
846static const char * const pci_e1_rst_groups[] = {
847 "gpio140"
848};
849static const char * const pci_e1_rst_n_groups[] = {
850 "gpio140"
851};
852static const char * const pci_e1_clkreq_n_groups[] = {
853 "gpio141"
854};
855static const char * const pri_mi2s_groups[] = {
856 "gpio76", "gpio77", "gpio78", "gpio79", "gpio80"
857};
858static const char * const qua_mi2s_groups[] = {
859 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"
860};
861static const char * const sata_act_groups[] = {
862 "gpio129"
863};
864static const char * const sata_devsleep_groups[] = {
865 "gpio119"
866};
867static const char * const sata_devsleep_n_groups[] = {
868 "gpio119"
869};
870static const char * const sd_write_groups[] = {
871 "gpio75"
872};
873static const char * const sdc_emmc_mode_groups[] = {
874 "gpio146"
875};
876static const char * const sdc3_groups[] = {
877 "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72"
878};
879static const char * const sdc4_groups[] = {
880 "gpio82", "gpio83", "gpio84", "gpio85", "gpio86",
881 "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
882};
883static const char * const sec_mi2s_groups[] = {
884 "gpio81", "gpio82", "gpio83", "gpio84", "gpio85"
885};
886static const char * const slimbus_groups[] = {
887 "gpio98", "gpio99"
888};
889static const char * const spdif_tx_groups[] = {
890 "gpio124", "gpio136", "gpio142"
891};
892static const char * const spkr_i2s_groups[] = {
893 "gpio98", "gpio99", "gpio100"
894};
895static const char * const spkr_i2s_ws_groups[] = {
896 "gpio104"
897};
898static const char * const spss_geni_groups[] = {
899 "gpio8", "gpio9"
900};
901static const char * const ter_mi2s_groups[] = {
902 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90"
903};
904static const char * const tsif1_groups[] = {
905 "gpio82", "gpio83", "gpio84", "gpio85", "gpio86"
906};
907static const char * const tsif2_groups[] = {
908 "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
909};
910static const char * const uim_groups[] = {
911 "gpio130", "gpio131", "gpio132", "gpio133"
912};
913static const char * const uim_batt_alarm_groups[] = {
914 "gpio102"
915};
916static const struct msm_function apq8084_functions[] = {
917 FUNCTION(adsp_ext),
918 FUNCTION(audio_ref),
919 FUNCTION(blsp_i2c1),
920 FUNCTION(blsp_i2c2),
921 FUNCTION(blsp_i2c3),
922 FUNCTION(blsp_i2c4),
923 FUNCTION(blsp_i2c5),
924 FUNCTION(blsp_i2c6),
925 FUNCTION(blsp_i2c7),
926 FUNCTION(blsp_i2c8),
927 FUNCTION(blsp_i2c9),
928 FUNCTION(blsp_i2c10),
929 FUNCTION(blsp_i2c11),
930 FUNCTION(blsp_i2c12),
931 FUNCTION(blsp_spi1),
932 FUNCTION(blsp_spi1_cs1),
933 FUNCTION(blsp_spi1_cs2),
934 FUNCTION(blsp_spi1_cs3),
935 FUNCTION(blsp_spi2),
936 FUNCTION(blsp_spi3),
937 FUNCTION(blsp_spi3_cs1),
938 FUNCTION(blsp_spi3_cs2),
939 FUNCTION(blsp_spi3_cs3),
940 FUNCTION(blsp_spi4),
941 FUNCTION(blsp_spi5),
942 FUNCTION(blsp_spi6),
943 FUNCTION(blsp_spi7),
944 FUNCTION(blsp_spi8),
945 FUNCTION(blsp_spi9),
946 FUNCTION(blsp_spi10),
947 FUNCTION(blsp_spi10_cs1),
948 FUNCTION(blsp_spi10_cs2),
949 FUNCTION(blsp_spi10_cs3),
950 FUNCTION(blsp_spi11),
951 FUNCTION(blsp_spi12),
952 FUNCTION(blsp_uart1),
953 FUNCTION(blsp_uart2),
954 FUNCTION(blsp_uart3),
955 FUNCTION(blsp_uart4),
956 FUNCTION(blsp_uart5),
957 FUNCTION(blsp_uart6),
958 FUNCTION(blsp_uart7),
959 FUNCTION(blsp_uart8),
960 FUNCTION(blsp_uart9),
961 FUNCTION(blsp_uart10),
962 FUNCTION(blsp_uart11),
963 FUNCTION(blsp_uart12),
964 FUNCTION(blsp_uim1),
965 FUNCTION(blsp_uim2),
966 FUNCTION(blsp_uim3),
967 FUNCTION(blsp_uim4),
968 FUNCTION(blsp_uim5),
969 FUNCTION(blsp_uim6),
970 FUNCTION(blsp_uim7),
971 FUNCTION(blsp_uim8),
972 FUNCTION(blsp_uim9),
973 FUNCTION(blsp_uim10),
974 FUNCTION(blsp_uim11),
975 FUNCTION(blsp_uim12),
976 FUNCTION(cam_mclk0),
977 FUNCTION(cam_mclk1),
978 FUNCTION(cam_mclk2),
979 FUNCTION(cam_mclk3),
980 FUNCTION(cci_async),
981 FUNCTION(cci_async_in0),
982 FUNCTION(cci_i2c0),
983 FUNCTION(cci_i2c1),
984 FUNCTION(cci_timer0),
985 FUNCTION(cci_timer1),
986 FUNCTION(cci_timer2),
987 FUNCTION(cci_timer3),
988 FUNCTION(cci_timer4),
989 FUNCTION(edp_hpd),
990 FUNCTION(gcc_gp1),
991 FUNCTION(gcc_gp2),
992 FUNCTION(gcc_gp3),
993 FUNCTION(gcc_obt),
994 FUNCTION(gcc_vtt),
995 FUNCTION(gp_mn),
996 FUNCTION(gp_pdm0),
997 FUNCTION(gp_pdm1),
998 FUNCTION(gp_pdm2),
999 FUNCTION(gp0_clk),
1000 FUNCTION(gp1_clk),
1001 FUNCTION(gpio),
1002 FUNCTION(hdmi_cec),
1003 FUNCTION(hdmi_ddc),
1004 FUNCTION(hdmi_dtest),
1005 FUNCTION(hdmi_hpd),
1006 FUNCTION(hdmi_rcv),
1007 FUNCTION(hsic),
1008 FUNCTION(ldo_en),
1009 FUNCTION(ldo_update),
1010 FUNCTION(mdp_vsync),
1011 FUNCTION(pci_e0),
1012 FUNCTION(pci_e0_n),
1013 FUNCTION(pci_e0_rst),
1014 FUNCTION(pci_e1),
1015 FUNCTION(pci_e1_rst),
1016 FUNCTION(pci_e1_rst_n),
1017 FUNCTION(pci_e1_clkreq_n),
1018 FUNCTION(pri_mi2s),
1019 FUNCTION(qua_mi2s),
1020 FUNCTION(sata_act),
1021 FUNCTION(sata_devsleep),
1022 FUNCTION(sata_devsleep_n),
1023 FUNCTION(sd_write),
1024 FUNCTION(sdc_emmc_mode),
1025 FUNCTION(sdc3),
1026 FUNCTION(sdc4),
1027 FUNCTION(sec_mi2s),
1028 FUNCTION(slimbus),
1029 FUNCTION(spdif_tx),
1030 FUNCTION(spkr_i2s),
1031 FUNCTION(spkr_i2s_ws),
1032 FUNCTION(spss_geni),
1033 FUNCTION(ter_mi2s),
1034 FUNCTION(tsif1),
1035 FUNCTION(tsif2),
1036 FUNCTION(uim),
1037 FUNCTION(uim_batt_alarm),
1038};
1039
1040static const struct msm_pingroup apq8084_groups[] = {
1041 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1042 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1043 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1044 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1045 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1046 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1047 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1048 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1049 PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA),
1050 PINGROUP(9, blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA),
1051 PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1052 PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1053 PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
1054 PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
1055 PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
1056 PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
1057 PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
1058 PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
1059 PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
1060 PINGROUP(19, cci_i2c0, NA, NA, NA, NA, NA, NA),
1061 PINGROUP(20, cci_i2c0, NA, NA, NA, NA, NA, NA),
1062 PINGROUP(21, cci_i2c1, NA, NA, NA, NA, NA, NA),
1063 PINGROUP(22, cci_i2c1, NA, NA, NA, NA, NA, NA),
1064 PINGROUP(23, cci_timer0, NA, NA, NA, NA, NA, NA),
1065 PINGROUP(24, cci_timer1, NA, NA, NA, NA, NA, NA),
1066 PINGROUP(25, cci_timer2, gp0_clk, NA, NA, NA, NA, NA),
1067 PINGROUP(26, cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA),
1068 PINGROUP(27, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1069 PINGROUP(28, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1070 PINGROUP(29, blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA),
1071 PINGROUP(30, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
1072 PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
1073 PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
1074 PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
1075 PINGROUP(34, hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA),
1076 PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
1077 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
1078 PINGROUP(37, gcc_gp1, NA, NA, NA, NA, NA, NA),
1079 PINGROUP(38, gcc_gp2, NA, NA, NA, NA, NA, NA),
1080 PINGROUP(39, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1081 PINGROUP(40, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1082 PINGROUP(41, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1083 PINGROUP(42, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1084 PINGROUP(43, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1085 PINGROUP(44, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1086 PINGROUP(45, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1087 PINGROUP(46, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1088 PINGROUP(47, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
1089 PINGROUP(48, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA),
1090 PINGROUP(49, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1091 PINGROUP(50, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1092 PINGROUP(51, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1093 PINGROUP(52, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1094 PINGROUP(53, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1095 PINGROUP(54, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1096 PINGROUP(55, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1097 PINGROUP(56, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1098 PINGROUP(57, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1099 PINGROUP(58, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1100 PINGROUP(59, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1101 PINGROUP(60, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1102 PINGROUP(61, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1103 PINGROUP(62, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1104 PINGROUP(63, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1105 PINGROUP(64, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1106 PINGROUP(65, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1107 PINGROUP(66, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1108 PINGROUP(67, sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA),
1109 PINGROUP(68, sdc3, pci_e0, NA, NA, NA, NA, NA),
1110 PINGROUP(69, sdc3, NA, NA, NA, NA, NA, NA),
1111 PINGROUP(70, sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA),
1112 PINGROUP(71, sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA),
1113 PINGROUP(72, sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA),
1114 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
1115 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
1116 PINGROUP(75, sd_write, NA, NA, NA, NA, NA, NA),
1117 PINGROUP(76, pri_mi2s, NA, NA, NA, NA, NA, NA),
1118 PINGROUP(77, pri_mi2s, NA, NA, NA, NA, NA, NA),
1119 PINGROUP(78, pri_mi2s, NA, NA, NA, NA, NA, NA),
1120 PINGROUP(79, pri_mi2s, NA, NA, NA, NA, NA, NA),
1121 PINGROUP(80, pri_mi2s, NA, NA, NA, NA, NA, NA),
1122 PINGROUP(81, sec_mi2s, NA, NA, NA, NA, NA, NA),
1123 PINGROUP(82, sec_mi2s, sdc4, tsif1, NA, NA, NA, NA),
1124 PINGROUP(83, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0),
1125 PINGROUP(84, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1),
1126 PINGROUP(85, sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA),
1127 PINGROUP(86, ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3),
1128 PINGROUP(87, ter_mi2s, NA, NA, NA, NA, NA, NA),
1129 PINGROUP(88, ter_mi2s, NA, NA, NA, NA, NA, NA),
1130 PINGROUP(89, ter_mi2s, NA, NA, NA, NA, NA, NA),
1131 PINGROUP(90, ter_mi2s, NA, NA, NA, NA, NA, NA),
1132 PINGROUP(91, qua_mi2s, sdc4, tsif2, NA, NA, NA, NA),
1133 PINGROUP(92, qua_mi2s, NA, NA, NA, NA, NA, NA),
1134 PINGROUP(93, qua_mi2s, NA, NA, NA, NA, NA, NA),
1135 PINGROUP(94, qua_mi2s, NA, NA, NA, NA, NA, NA),
1136 PINGROUP(95, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1),
1137 PINGROUP(96, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2),
1138 PINGROUP(97, qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA),
1139 PINGROUP(98, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1140 PINGROUP(99, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1141 PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA),
1142 PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA),
1143 PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
1144 PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA),
1145 PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA),
1146 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
1147 PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA),
1148 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
1149 PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
1150 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
1151 PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA),
1152 PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA),
1153 PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
1154 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
1155 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
1156 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
1157 PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA),
1158 PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA),
1159 PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA),
1160 PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA),
1161 PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA),
1162 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
1163 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
1164 PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA),
1165 PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA),
1166 PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA),
1167 PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA),
1168 PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA),
1169 PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA),
1170 PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA),
1171 PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1172 PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1173 PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1174 PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1175 PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA),
1176 PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA),
1177 PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA),
1178 PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
1179 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
1180 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
1181 PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA),
1182 PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA),
1183 PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA),
1184 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
1185 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
1186 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
1187 PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA),
1188
1189 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
1190 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
1191 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
1192 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
1193 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
1194 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
1195};
1196
1197#define NUM_GPIO_PINGROUPS 147
1198
1199static const struct msm_pinctrl_soc_data apq8084_pinctrl = {
1200 .pins = apq8084_pins,
1201 .npins = ARRAY_SIZE(apq8084_pins),
1202 .functions = apq8084_functions,
1203 .nfunctions = ARRAY_SIZE(apq8084_functions),
1204 .groups = apq8084_groups,
1205 .ngroups = ARRAY_SIZE(apq8084_groups),
1206 .ngpios = NUM_GPIO_PINGROUPS,
1207};
1208
1209static int apq8084_pinctrl_probe(struct platform_device *pdev)
1210{
1211 return msm_pinctrl_probe(pdev, &apq8084_pinctrl);
1212}
1213
1214static const struct of_device_id apq8084_pinctrl_of_match[] = {
1215 { .compatible = "qcom,apq8084-pinctrl", },
1216 { },
1217};
1218
1219static struct platform_driver apq8084_pinctrl_driver = {
1220 .driver = {
1221 .name = "apq8084-pinctrl",
1222 .owner = THIS_MODULE,
1223 .of_match_table = apq8084_pinctrl_of_match,
1224 },
1225 .probe = apq8084_pinctrl_probe,
1226 .remove = msm_pinctrl_remove,
1227};
1228
1229static int __init apq8084_pinctrl_init(void)
1230{
1231 return platform_driver_register(&apq8084_pinctrl_driver);
1232}
1233arch_initcall(apq8084_pinctrl_init);
1234
1235static void __exit apq8084_pinctrl_exit(void)
1236{
1237 platform_driver_unregister(&apq8084_pinctrl_driver);
1238}
1239module_exit(apq8084_pinctrl_exit);
1240
1241MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");
1242MODULE_LICENSE("GPL v2");
1243MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 09:26:10 -0400