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path: root/drivers/pinctrl/pinctrl-tegra20.c
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-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c2860
1 files changed, 2860 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
new file mode 100644
index 000000000000..f69ff96aa292
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -0,0 +1,2860 @@
1/*
2 * Pinctrl data for the NVIDIA Tegra20 pinmux
3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23
24#include "pinctrl-tegra.h"
25
26/*
27 * Most pins affected by the pinmux can also be GPIOs. Define these first.
28 * These must match how the GPIO driver names/numbers its pins.
29 */
30#define _GPIO(offset) (offset)
31
32#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
33#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
34#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
35#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
36#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
37#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
38#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
39#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
40#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
41#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
42#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
43#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
44#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
45#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
46#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
47#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
48#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
49#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
50#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
51#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
52#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
53#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
54#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
55#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
56#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
57#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
58#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
59#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
60#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
61#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
62#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
63#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
64#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
65#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
66#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
67#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
68#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
69#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
70#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
71#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
72#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
73#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
74#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
75#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
76#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
77#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
78#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
79#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
80#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
81#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
82#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
83#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
84#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
85#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
86#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
87#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
88#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
89#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
90#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
91#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
92#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
93#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
94#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
95#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
96#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
97#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
98#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
99#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
100#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
101#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
102#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
103#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
104#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
105#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
106#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
107#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
108#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
109#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
110#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
111#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
112#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
113#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
114#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
115#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
116#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
117#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
118#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
119#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
120#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
121#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
122#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
123#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
124#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
125#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
126#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
127#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
128#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
129#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
130#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
131#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
132#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
133#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
134#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
135#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
136#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
137#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
138#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
139#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
140#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
141#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
142#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
143#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
144#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
145#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
146#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
147#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
148#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
149#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
150#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
151#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
152#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
153#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
154#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
155#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
156#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
157#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
158#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
159#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
160#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
161#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
162#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
163#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
164#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
165#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
166#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
167#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
168#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
169#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
170#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
171#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
172#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
173#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
174#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
175#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
176#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
177#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
178#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
179#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
180#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
181#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
182#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
183#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
184#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
185#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
186#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
187#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
188#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
189#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
190#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
191#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
192#define TEGRA_PIN_PU0 _GPIO(160)
193#define TEGRA_PIN_PU1 _GPIO(161)
194#define TEGRA_PIN_PU2 _GPIO(162)
195#define TEGRA_PIN_PU3 _GPIO(163)
196#define TEGRA_PIN_PU4 _GPIO(164)
197#define TEGRA_PIN_PU5 _GPIO(165)
198#define TEGRA_PIN_PU6 _GPIO(166)
199#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
200#define TEGRA_PIN_PV0 _GPIO(168)
201#define TEGRA_PIN_PV1 _GPIO(169)
202#define TEGRA_PIN_PV2 _GPIO(170)
203#define TEGRA_PIN_PV3 _GPIO(171)
204#define TEGRA_PIN_PV4 _GPIO(172)
205#define TEGRA_PIN_PV5 _GPIO(173)
206#define TEGRA_PIN_PV6 _GPIO(174)
207#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
208#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
209#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
210#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
211#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
212#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
213#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
214#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
215#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
216#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
217#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
218#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
219#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
220#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
221#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
222#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
223#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
224#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
225#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
226#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
227#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
228#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
229#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
230#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
231#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
232#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
233#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
234#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
235#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
236#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
237#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
238#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
239#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
240#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
241#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
242#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
243#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
244#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
245#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
246#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
247#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
248#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
249#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
250#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
251#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
252#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
253#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
254#define TEGRA_PIN_PBB6 _GPIO(222)
255#define TEGRA_PIN_PBB7 _GPIO(223)
256
257/* All non-GPIO pins follow */
258#define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
259#define _PIN(offset) (NUM_GPIOS + (offset))
260
261#define TEGRA_PIN_CRT_HSYNC _PIN(30)
262#define TEGRA_PIN_CRT_VSYNC _PIN(31)
263#define TEGRA_PIN_DDC_SCL _PIN(32)
264#define TEGRA_PIN_DDC_SDA _PIN(33)
265#define TEGRA_PIN_OWC _PIN(34)
266#define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
267#define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
268#define TEGRA_PIN_PWR_INT_N _PIN(37)
269#define TEGRA_PIN_CLK_32_K_IN _PIN(38)
270#define TEGRA_PIN_DDR_COMP_PD _PIN(39)
271#define TEGRA_PIN_DDR_COMP_PU _PIN(40)
272#define TEGRA_PIN_DDR_A0 _PIN(41)
273#define TEGRA_PIN_DDR_A1 _PIN(42)
274#define TEGRA_PIN_DDR_A2 _PIN(43)
275#define TEGRA_PIN_DDR_A3 _PIN(44)
276#define TEGRA_PIN_DDR_A4 _PIN(45)
277#define TEGRA_PIN_DDR_A5 _PIN(46)
278#define TEGRA_PIN_DDR_A6 _PIN(47)
279#define TEGRA_PIN_DDR_A7 _PIN(48)
280#define TEGRA_PIN_DDR_A8 _PIN(49)
281#define TEGRA_PIN_DDR_A9 _PIN(50)
282#define TEGRA_PIN_DDR_A10 _PIN(51)
283#define TEGRA_PIN_DDR_A11 _PIN(52)
284#define TEGRA_PIN_DDR_A12 _PIN(53)
285#define TEGRA_PIN_DDR_A13 _PIN(54)
286#define TEGRA_PIN_DDR_A14 _PIN(55)
287#define TEGRA_PIN_DDR_CAS_N _PIN(56)
288#define TEGRA_PIN_DDR_BA0 _PIN(57)
289#define TEGRA_PIN_DDR_BA1 _PIN(58)
290#define TEGRA_PIN_DDR_BA2 _PIN(59)
291#define TEGRA_PIN_DDR_DQS0P _PIN(60)
292#define TEGRA_PIN_DDR_DQS0N _PIN(61)
293#define TEGRA_PIN_DDR_DQS1P _PIN(62)
294#define TEGRA_PIN_DDR_DQS1N _PIN(63)
295#define TEGRA_PIN_DDR_DQS2P _PIN(64)
296#define TEGRA_PIN_DDR_DQS2N _PIN(65)
297#define TEGRA_PIN_DDR_DQS3P _PIN(66)
298#define TEGRA_PIN_DDR_DQS3N _PIN(67)
299#define TEGRA_PIN_DDR_CKE0 _PIN(68)
300#define TEGRA_PIN_DDR_CKE1 _PIN(69)
301#define TEGRA_PIN_DDR_CLK _PIN(70)
302#define TEGRA_PIN_DDR_CLK_N _PIN(71)
303#define TEGRA_PIN_DDR_DM0 _PIN(72)
304#define TEGRA_PIN_DDR_DM1 _PIN(73)
305#define TEGRA_PIN_DDR_DM2 _PIN(74)
306#define TEGRA_PIN_DDR_DM3 _PIN(75)
307#define TEGRA_PIN_DDR_ODT _PIN(76)
308#define TEGRA_PIN_DDR_QUSE0 _PIN(77)
309#define TEGRA_PIN_DDR_QUSE1 _PIN(78)
310#define TEGRA_PIN_DDR_QUSE2 _PIN(79)
311#define TEGRA_PIN_DDR_QUSE3 _PIN(80)
312#define TEGRA_PIN_DDR_RAS_N _PIN(81)
313#define TEGRA_PIN_DDR_WE_N _PIN(82)
314#define TEGRA_PIN_DDR_DQ0 _PIN(83)
315#define TEGRA_PIN_DDR_DQ1 _PIN(84)
316#define TEGRA_PIN_DDR_DQ2 _PIN(85)
317#define TEGRA_PIN_DDR_DQ3 _PIN(86)
318#define TEGRA_PIN_DDR_DQ4 _PIN(87)
319#define TEGRA_PIN_DDR_DQ5 _PIN(88)
320#define TEGRA_PIN_DDR_DQ6 _PIN(89)
321#define TEGRA_PIN_DDR_DQ7 _PIN(90)
322#define TEGRA_PIN_DDR_DQ8 _PIN(91)
323#define TEGRA_PIN_DDR_DQ9 _PIN(92)
324#define TEGRA_PIN_DDR_DQ10 _PIN(93)
325#define TEGRA_PIN_DDR_DQ11 _PIN(94)
326#define TEGRA_PIN_DDR_DQ12 _PIN(95)
327#define TEGRA_PIN_DDR_DQ13 _PIN(96)
328#define TEGRA_PIN_DDR_DQ14 _PIN(97)
329#define TEGRA_PIN_DDR_DQ15 _PIN(98)
330#define TEGRA_PIN_DDR_DQ16 _PIN(99)
331#define TEGRA_PIN_DDR_DQ17 _PIN(100)
332#define TEGRA_PIN_DDR_DQ18 _PIN(101)
333#define TEGRA_PIN_DDR_DQ19 _PIN(102)
334#define TEGRA_PIN_DDR_DQ20 _PIN(103)
335#define TEGRA_PIN_DDR_DQ21 _PIN(104)
336#define TEGRA_PIN_DDR_DQ22 _PIN(105)
337#define TEGRA_PIN_DDR_DQ23 _PIN(106)
338#define TEGRA_PIN_DDR_DQ24 _PIN(107)
339#define TEGRA_PIN_DDR_DQ25 _PIN(108)
340#define TEGRA_PIN_DDR_DQ26 _PIN(109)
341#define TEGRA_PIN_DDR_DQ27 _PIN(110)
342#define TEGRA_PIN_DDR_DQ28 _PIN(111)
343#define TEGRA_PIN_DDR_DQ29 _PIN(112)
344#define TEGRA_PIN_DDR_DQ30 _PIN(113)
345#define TEGRA_PIN_DDR_DQ31 _PIN(114)
346#define TEGRA_PIN_DDR_CS0_N _PIN(115)
347#define TEGRA_PIN_DDR_CS1_N _PIN(116)
348#define TEGRA_PIN_SYS_RESET _PIN(117)
349#define TEGRA_PIN_JTAG_TRST_N _PIN(118)
350#define TEGRA_PIN_JTAG_TDO _PIN(119)
351#define TEGRA_PIN_JTAG_TMS _PIN(120)
352#define TEGRA_PIN_JTAG_TCK _PIN(121)
353#define TEGRA_PIN_JTAG_TDI _PIN(122)
354#define TEGRA_PIN_TEST_MODE_EN _PIN(123)
355
356static const struct pinctrl_pin_desc tegra20_pins[] = {
357 PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
358 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
359 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
360 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
361 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
362 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
363 PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
364 PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
365 PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
366 PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
367 PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
368 PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
369 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
370 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
371 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
372 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
373 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
374 PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
375 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
376 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
377 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
378 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
379 PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
380 PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
381 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
382 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
383 PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
384 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
385 PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
386 PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
387 PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
388 PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
389 PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
390 PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
391 PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
392 PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
393 PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
394 PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
395 PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
396 PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
397 PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
398 PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
399 PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
400 PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
401 PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
402 PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
403 PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
404 PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
405 PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
406 PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
407 PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
408 PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
409 PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
410 PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
411 PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
412 PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
413 PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
414 PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
415 PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
416 PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
417 PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
418 PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
419 PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
420 PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
421 PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
422 PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
423 PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
424 PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
425 PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
426 PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
427 PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
428 PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
429 PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
430 PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
431 PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
432 PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
433 PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
434 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
435 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
436 PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
437 PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
438 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
439 PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
440 PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
441 PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
442 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
443 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
444 PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
445 PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
446 PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
447 PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
448 PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
449 PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
450 PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
451 PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
452 PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
453 PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
454 PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
455 PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
456 PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
457 PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
458 PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
459 PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
460 PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
461 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
462 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
463 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
464 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
465 PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
466 PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
467 PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
468 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
469 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
470 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
471 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
472 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
473 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
474 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
475 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
476 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
477 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
478 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
479 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
480 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
481 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
482 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
483 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
484 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
485 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
486 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
487 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
488 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
489 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
490 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
491 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
492 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
493 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
494 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
495 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
496 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
497 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
498 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
499 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
500 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
501 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
502 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
503 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
504 PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
505 PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
506 PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
507 PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
508 PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
509 PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
510 PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
511 PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
512 PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
513 PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
514 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
515 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
516 PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
517 /* PU0..6: GPIO only */
518 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
519 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
520 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
521 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
522 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
523 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
524 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
525 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
526 /* PV0..1: GPIO only */
527 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
528 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
529 /* PV2..3: Balls are named after GPIO not function */
530 PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
531 PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
532 /* PV4..6: GPIO only */
533 PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
534 PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
535 PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
536 PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
537 PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
538 PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
539 PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
540 PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
541 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
542 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
543 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
544 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
545 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
546 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
547 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
548 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
549 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
550 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
551 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
552 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
553 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
554 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
555 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
556 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
557 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
558 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
559 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
560 PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
561 PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
562 PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
563 PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
564 PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
565 PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
566 PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
567 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
568 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
569 PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
570 PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
571 PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
572 PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
573 PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
574 PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
575 PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
576 PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
577 PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
578 PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
579 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
580 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
581 PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
582 PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
583 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
584 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
585 PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
586 PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
587 PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
588 PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
589 PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
590 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
591 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
592 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
593 PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
594 PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
595 PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
596 PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
597 PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
598 PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
599 PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
600 PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
601 PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
602 PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
603 PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
604 PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
605 PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
606 PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
607 PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
608 PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
609 PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
610 PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
611 PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
612 PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
613 PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
614 PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
615 PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
616 PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
617 PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
618 PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
619 PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
620 PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
621 PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
622 PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
623 PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
624 PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
625 PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
626 PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
627 PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
628 PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
629 PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
630 PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
631 PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
632 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
633 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
634 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
635 PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
636 PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
637 PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
638 PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
639 PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
640 PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
641 PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
642 PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
643 PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
644 PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
645 PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
646 PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
647 PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
648 PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
649 PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
650 PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
651 PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
652 PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
653 PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
654 PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
655 PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
656 PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
657 PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
658 PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
659 PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
660 PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
661 PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
662 PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
663 PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
664 PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
665 PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
666 PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
667 PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
668 PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
669 PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
670 PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
671 PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
672 PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
673 PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
674 PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
675 PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
676 PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
677 PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
678 PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
679};
680
681static const unsigned ata_pins[] = {
682 TEGRA_PIN_GMI_CS6_N_PI3,
683 TEGRA_PIN_GMI_CS7_N_PI6,
684 TEGRA_PIN_GMI_RST_N_PI4,
685};
686
687static const unsigned atb_pins[] = {
688 TEGRA_PIN_GMI_CS5_N_PI2,
689 TEGRA_PIN_GMI_DPD_PT7,
690};
691
692static const unsigned atc_pins[] = {
693 TEGRA_PIN_GMI_IORDY_PI5,
694 TEGRA_PIN_GMI_WAIT_PI7,
695 TEGRA_PIN_GMI_ADV_N_PK0,
696 TEGRA_PIN_GMI_CLK_PK1,
697 TEGRA_PIN_GMI_CS2_N_PK3,
698 TEGRA_PIN_GMI_CS3_N_PK4,
699 TEGRA_PIN_GMI_CS4_N_PK2,
700 TEGRA_PIN_GMI_AD0_PG0,
701 TEGRA_PIN_GMI_AD1_PG1,
702 TEGRA_PIN_GMI_AD2_PG2,
703 TEGRA_PIN_GMI_AD3_PG3,
704 TEGRA_PIN_GMI_AD4_PG4,
705 TEGRA_PIN_GMI_AD5_PG5,
706 TEGRA_PIN_GMI_AD6_PG6,
707 TEGRA_PIN_GMI_AD7_PG7,
708 TEGRA_PIN_GMI_HIOW_N_PI0,
709 TEGRA_PIN_GMI_HIOR_N_PI1,
710};
711
712static const unsigned atd_pins[] = {
713 TEGRA_PIN_GMI_AD8_PH0,
714 TEGRA_PIN_GMI_AD9_PH1,
715 TEGRA_PIN_GMI_AD10_PH2,
716 TEGRA_PIN_GMI_AD11_PH3,
717};
718
719static const unsigned ate_pins[] = {
720 TEGRA_PIN_GMI_AD12_PH4,
721 TEGRA_PIN_GMI_AD13_PH5,
722 TEGRA_PIN_GMI_AD14_PH6,
723 TEGRA_PIN_GMI_AD15_PH7,
724};
725
726static const unsigned cdev1_pins[] = {
727 TEGRA_PIN_DAP_MCLK1_PW4,
728};
729
730static const unsigned cdev2_pins[] = {
731 TEGRA_PIN_DAP_MCLK2_PW5,
732};
733
734static const unsigned crtp_pins[] = {
735 TEGRA_PIN_CRT_HSYNC,
736 TEGRA_PIN_CRT_VSYNC,
737};
738
739static const unsigned csus_pins[] = {
740 TEGRA_PIN_VI_MCLK_PT1,
741};
742
743static const unsigned dap1_pins[] = {
744 TEGRA_PIN_DAP1_FS_PN0,
745 TEGRA_PIN_DAP1_DIN_PN1,
746 TEGRA_PIN_DAP1_DOUT_PN2,
747 TEGRA_PIN_DAP1_SCLK_PN3,
748};
749
750static const unsigned dap2_pins[] = {
751 TEGRA_PIN_DAP2_FS_PA2,
752 TEGRA_PIN_DAP2_SCLK_PA3,
753 TEGRA_PIN_DAP2_DIN_PA4,
754 TEGRA_PIN_DAP2_DOUT_PA5,
755};
756
757static const unsigned dap3_pins[] = {
758 TEGRA_PIN_DAP3_FS_PP0,
759 TEGRA_PIN_DAP3_DIN_PP1,
760 TEGRA_PIN_DAP3_DOUT_PP2,
761 TEGRA_PIN_DAP3_SCLK_PP3,
762};
763
764static const unsigned dap4_pins[] = {
765 TEGRA_PIN_DAP4_FS_PP4,
766 TEGRA_PIN_DAP4_DIN_PP5,
767 TEGRA_PIN_DAP4_DOUT_PP6,
768 TEGRA_PIN_DAP4_SCLK_PP7,
769};
770
771static const unsigned ddc_pins[] = {
772 TEGRA_PIN_DDC_SCL,
773 TEGRA_PIN_DDC_SDA,
774};
775
776static const unsigned dta_pins[] = {
777 TEGRA_PIN_VI_D0_PT4,
778 TEGRA_PIN_VI_D1_PD5,
779};
780
781static const unsigned dtb_pins[] = {
782 TEGRA_PIN_VI_D10_PT2,
783 TEGRA_PIN_VI_D11_PT3,
784};
785
786static const unsigned dtc_pins[] = {
787 TEGRA_PIN_VI_HSYNC_PD7,
788 TEGRA_PIN_VI_VSYNC_PD6,
789};
790
791static const unsigned dtd_pins[] = {
792 TEGRA_PIN_VI_PCLK_PT0,
793 TEGRA_PIN_VI_D2_PL0,
794 TEGRA_PIN_VI_D3_PL1,
795 TEGRA_PIN_VI_D4_PL2,
796 TEGRA_PIN_VI_D5_PL3,
797 TEGRA_PIN_VI_D6_PL4,
798 TEGRA_PIN_VI_D7_PL5,
799 TEGRA_PIN_VI_D8_PL6,
800 TEGRA_PIN_VI_D9_PL7,
801};
802
803static const unsigned dte_pins[] = {
804 TEGRA_PIN_VI_GP0_PBB1,
805 TEGRA_PIN_VI_GP3_PBB4,
806 TEGRA_PIN_VI_GP4_PBB5,
807 TEGRA_PIN_VI_GP5_PD2,
808 TEGRA_PIN_VI_GP6_PA0,
809};
810
811static const unsigned dtf_pins[] = {
812 TEGRA_PIN_CAM_I2C_SCL_PBB2,
813 TEGRA_PIN_CAM_I2C_SDA_PBB3,
814};
815
816static const unsigned gma_pins[] = {
817 TEGRA_PIN_GMI_AD20_PAA0,
818 TEGRA_PIN_GMI_AD21_PAA1,
819 TEGRA_PIN_GMI_AD22_PAA2,
820 TEGRA_PIN_GMI_AD23_PAA3,
821};
822
823static const unsigned gmb_pins[] = {
824 TEGRA_PIN_GMI_WP_N_PC7,
825};
826
827static const unsigned gmc_pins[] = {
828 TEGRA_PIN_GMI_AD16_PJ7,
829 TEGRA_PIN_GMI_AD17_PB0,
830 TEGRA_PIN_GMI_AD18_PB1,
831 TEGRA_PIN_GMI_AD19_PK7,
832};
833
834static const unsigned gmd_pins[] = {
835 TEGRA_PIN_GMI_CS0_N_PJ0,
836 TEGRA_PIN_GMI_CS1_N_PJ2,
837};
838
839static const unsigned gme_pins[] = {
840 TEGRA_PIN_GMI_AD24_PAA4,
841 TEGRA_PIN_GMI_AD25_PAA5,
842 TEGRA_PIN_GMI_AD26_PAA6,
843 TEGRA_PIN_GMI_AD27_PAA7,
844};
845
846static const unsigned gpu_pins[] = {
847 TEGRA_PIN_PU0,
848 TEGRA_PIN_PU1,
849 TEGRA_PIN_PU2,
850 TEGRA_PIN_PU3,
851 TEGRA_PIN_PU4,
852 TEGRA_PIN_PU5,
853 TEGRA_PIN_PU6,
854};
855
856static const unsigned gpu7_pins[] = {
857 TEGRA_PIN_JTAG_RTCK_PU7,
858};
859
860static const unsigned gpv_pins[] = {
861 TEGRA_PIN_PV4,
862 TEGRA_PIN_PV5,
863 TEGRA_PIN_PV6,
864};
865
866static const unsigned hdint_pins[] = {
867 TEGRA_PIN_HDMI_INT_N_PN7,
868};
869
870static const unsigned i2cp_pins[] = {
871 TEGRA_PIN_PWR_I2C_SCL_PZ6,
872 TEGRA_PIN_PWR_I2C_SDA_PZ7,
873};
874
875static const unsigned irrx_pins[] = {
876 TEGRA_PIN_UART2_RTS_N_PJ6,
877};
878
879static const unsigned irtx_pins[] = {
880 TEGRA_PIN_UART2_CTS_N_PJ5,
881};
882
883static const unsigned kbca_pins[] = {
884 TEGRA_PIN_KB_ROW0_PR0,
885 TEGRA_PIN_KB_ROW1_PR1,
886 TEGRA_PIN_KB_ROW2_PR2,
887};
888
889static const unsigned kbcb_pins[] = {
890 TEGRA_PIN_KB_ROW7_PR7,
891 TEGRA_PIN_KB_ROW8_PS0,
892 TEGRA_PIN_KB_ROW9_PS1,
893 TEGRA_PIN_KB_ROW10_PS2,
894 TEGRA_PIN_KB_ROW11_PS3,
895 TEGRA_PIN_KB_ROW12_PS4,
896 TEGRA_PIN_KB_ROW13_PS5,
897 TEGRA_PIN_KB_ROW14_PS6,
898 TEGRA_PIN_KB_ROW15_PS7,
899};
900
901static const unsigned kbcc_pins[] = {
902 TEGRA_PIN_KB_COL0_PQ0,
903 TEGRA_PIN_KB_COL1_PQ1,
904};
905
906static const unsigned kbcd_pins[] = {
907 TEGRA_PIN_KB_ROW3_PR3,
908 TEGRA_PIN_KB_ROW4_PR4,
909 TEGRA_PIN_KB_ROW5_PR5,
910 TEGRA_PIN_KB_ROW6_PR6,
911};
912
913static const unsigned kbce_pins[] = {
914 TEGRA_PIN_KB_COL7_PQ7,
915};
916
917static const unsigned kbcf_pins[] = {
918 TEGRA_PIN_KB_COL2_PQ2,
919 TEGRA_PIN_KB_COL3_PQ3,
920 TEGRA_PIN_KB_COL4_PQ4,
921 TEGRA_PIN_KB_COL5_PQ5,
922 TEGRA_PIN_KB_COL6_PQ6,
923};
924
925static const unsigned lcsn_pins[] = {
926 TEGRA_PIN_LCD_CS0_N_PN4,
927};
928
929static const unsigned ld0_pins[] = {
930 TEGRA_PIN_LCD_D0_PE0,
931};
932
933static const unsigned ld1_pins[] = {
934 TEGRA_PIN_LCD_D1_PE1,
935};
936
937static const unsigned ld2_pins[] = {
938 TEGRA_PIN_LCD_D2_PE2,
939};
940
941static const unsigned ld3_pins[] = {
942 TEGRA_PIN_LCD_D3_PE3,
943};
944
945static const unsigned ld4_pins[] = {
946 TEGRA_PIN_LCD_D4_PE4,
947};
948
949static const unsigned ld5_pins[] = {
950 TEGRA_PIN_LCD_D5_PE5,
951};
952
953static const unsigned ld6_pins[] = {
954 TEGRA_PIN_LCD_D6_PE6,
955};
956
957static const unsigned ld7_pins[] = {
958 TEGRA_PIN_LCD_D7_PE7,
959};
960
961static const unsigned ld8_pins[] = {
962 TEGRA_PIN_LCD_D8_PF0,
963};
964
965static const unsigned ld9_pins[] = {
966 TEGRA_PIN_LCD_D9_PF1,
967};
968
969static const unsigned ld10_pins[] = {
970 TEGRA_PIN_LCD_D10_PF2,
971};
972
973static const unsigned ld11_pins[] = {
974 TEGRA_PIN_LCD_D11_PF3,
975};
976
977static const unsigned ld12_pins[] = {
978 TEGRA_PIN_LCD_D12_PF4,
979};
980
981static const unsigned ld13_pins[] = {
982 TEGRA_PIN_LCD_D13_PF5,
983};
984
985static const unsigned ld14_pins[] = {
986 TEGRA_PIN_LCD_D14_PF6,
987};
988
989static const unsigned ld15_pins[] = {
990 TEGRA_PIN_LCD_D15_PF7,
991};
992
993static const unsigned ld16_pins[] = {
994 TEGRA_PIN_LCD_D16_PM0,
995};
996
997static const unsigned ld17_pins[] = {
998 TEGRA_PIN_LCD_D17_PM1,
999};
1000
1001static const unsigned ldc_pins[] = {
1002 TEGRA_PIN_LCD_DC0_PN6,
1003};
1004
1005static const unsigned ldi_pins[] = {
1006 TEGRA_PIN_LCD_D22_PM6,
1007};
1008
1009static const unsigned lhp0_pins[] = {
1010 TEGRA_PIN_LCD_D21_PM5,
1011};
1012
1013static const unsigned lhp1_pins[] = {
1014 TEGRA_PIN_LCD_D18_PM2,
1015};
1016
1017static const unsigned lhp2_pins[] = {
1018 TEGRA_PIN_LCD_D19_PM3,
1019};
1020
1021static const unsigned lhs_pins[] = {
1022 TEGRA_PIN_LCD_HSYNC_PJ3,
1023};
1024
1025static const unsigned lm0_pins[] = {
1026 TEGRA_PIN_LCD_CS1_N_PW0,
1027};
1028
1029static const unsigned lm1_pins[] = {
1030 TEGRA_PIN_LCD_M1_PW1,
1031};
1032
1033static const unsigned lpp_pins[] = {
1034 TEGRA_PIN_LCD_D23_PM7,
1035};
1036
1037static const unsigned lpw0_pins[] = {
1038 TEGRA_PIN_LCD_PWR0_PB2,
1039};
1040
1041static const unsigned lpw1_pins[] = {
1042 TEGRA_PIN_LCD_PWR1_PC1,
1043};
1044
1045static const unsigned lpw2_pins[] = {
1046 TEGRA_PIN_LCD_PWR2_PC6,
1047};
1048
1049static const unsigned lsc0_pins[] = {
1050 TEGRA_PIN_LCD_PCLK_PB3,
1051};
1052
1053static const unsigned lsc1_pins[] = {
1054 TEGRA_PIN_LCD_WR_N_PZ3,
1055};
1056
1057static const unsigned lsck_pins[] = {
1058 TEGRA_PIN_LCD_SCK_PZ4,
1059};
1060
1061static const unsigned lsda_pins[] = {
1062 TEGRA_PIN_LCD_SDOUT_PN5,
1063};
1064
1065static const unsigned lsdi_pins[] = {
1066 TEGRA_PIN_LCD_SDIN_PZ2,
1067};
1068
1069static const unsigned lspi_pins[] = {
1070 TEGRA_PIN_LCD_DE_PJ1,
1071};
1072
1073static const unsigned lvp0_pins[] = {
1074 TEGRA_PIN_LCD_DC1_PV7,
1075};
1076
1077static const unsigned lvp1_pins[] = {
1078 TEGRA_PIN_LCD_D20_PM4,
1079};
1080
1081static const unsigned lvs_pins[] = {
1082 TEGRA_PIN_LCD_VSYNC_PJ4,
1083};
1084
1085static const unsigned ls_pins[] = {
1086 TEGRA_PIN_LCD_PWR0_PB2,
1087 TEGRA_PIN_LCD_PWR1_PC1,
1088 TEGRA_PIN_LCD_PWR2_PC6,
1089 TEGRA_PIN_LCD_SDIN_PZ2,
1090 TEGRA_PIN_LCD_SDOUT_PN5,
1091 TEGRA_PIN_LCD_WR_N_PZ3,
1092 TEGRA_PIN_LCD_CS0_N_PN4,
1093 TEGRA_PIN_LCD_DC0_PN6,
1094 TEGRA_PIN_LCD_SCK_PZ4,
1095};
1096
1097static const unsigned lc_pins[] = {
1098 TEGRA_PIN_LCD_PCLK_PB3,
1099 TEGRA_PIN_LCD_DE_PJ1,
1100 TEGRA_PIN_LCD_HSYNC_PJ3,
1101 TEGRA_PIN_LCD_VSYNC_PJ4,
1102 TEGRA_PIN_LCD_CS1_N_PW0,
1103 TEGRA_PIN_LCD_M1_PW1,
1104 TEGRA_PIN_LCD_DC1_PV7,
1105 TEGRA_PIN_HDMI_INT_N_PN7,
1106};
1107
1108static const unsigned ld17_0_pins[] = {
1109 TEGRA_PIN_LCD_D0_PE0,
1110 TEGRA_PIN_LCD_D1_PE1,
1111 TEGRA_PIN_LCD_D2_PE2,
1112 TEGRA_PIN_LCD_D3_PE3,
1113 TEGRA_PIN_LCD_D4_PE4,
1114 TEGRA_PIN_LCD_D5_PE5,
1115 TEGRA_PIN_LCD_D6_PE6,
1116 TEGRA_PIN_LCD_D7_PE7,
1117 TEGRA_PIN_LCD_D8_PF0,
1118 TEGRA_PIN_LCD_D9_PF1,
1119 TEGRA_PIN_LCD_D10_PF2,
1120 TEGRA_PIN_LCD_D11_PF3,
1121 TEGRA_PIN_LCD_D12_PF4,
1122 TEGRA_PIN_LCD_D13_PF5,
1123 TEGRA_PIN_LCD_D14_PF6,
1124 TEGRA_PIN_LCD_D15_PF7,
1125 TEGRA_PIN_LCD_D16_PM0,
1126 TEGRA_PIN_LCD_D17_PM1,
1127};
1128
1129static const unsigned ld19_18_pins[] = {
1130 TEGRA_PIN_LCD_D18_PM2,
1131 TEGRA_PIN_LCD_D19_PM3,
1132};
1133
1134static const unsigned ld21_20_pins[] = {
1135 TEGRA_PIN_LCD_D20_PM4,
1136 TEGRA_PIN_LCD_D21_PM5,
1137};
1138
1139static const unsigned ld23_22_pins[] = {
1140 TEGRA_PIN_LCD_D22_PM6,
1141 TEGRA_PIN_LCD_D23_PM7,
1142};
1143
1144static const unsigned owc_pins[] = {
1145 TEGRA_PIN_OWC,
1146};
1147
1148static const unsigned pmc_pins[] = {
1149 TEGRA_PIN_LED_BLINK_PBB0,
1150 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1151 TEGRA_PIN_CORE_PWR_REQ,
1152 TEGRA_PIN_CPU_PWR_REQ,
1153 TEGRA_PIN_PWR_INT_N,
1154};
1155
1156static const unsigned pta_pins[] = {
1157 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1158 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1159};
1160
1161static const unsigned rm_pins[] = {
1162 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1163 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1164};
1165
1166static const unsigned sdb_pins[] = {
1167 TEGRA_PIN_SDIO3_CMD_PA7,
1168};
1169
1170static const unsigned sdc_pins[] = {
1171 TEGRA_PIN_SDIO3_DAT0_PB7,
1172 TEGRA_PIN_SDIO3_DAT1_PB6,
1173 TEGRA_PIN_SDIO3_DAT2_PB5,
1174 TEGRA_PIN_SDIO3_DAT3_PB4,
1175};
1176
1177static const unsigned sdd_pins[] = {
1178 TEGRA_PIN_SDIO3_CLK_PA6,
1179};
1180
1181static const unsigned sdio1_pins[] = {
1182 TEGRA_PIN_SDIO1_CLK_PZ0,
1183 TEGRA_PIN_SDIO1_CMD_PZ1,
1184 TEGRA_PIN_SDIO1_DAT0_PY7,
1185 TEGRA_PIN_SDIO1_DAT1_PY6,
1186 TEGRA_PIN_SDIO1_DAT2_PY5,
1187 TEGRA_PIN_SDIO1_DAT3_PY4,
1188};
1189
1190static const unsigned slxa_pins[] = {
1191 TEGRA_PIN_SDIO3_DAT4_PD1,
1192};
1193
1194static const unsigned slxc_pins[] = {
1195 TEGRA_PIN_SDIO3_DAT6_PD3,
1196};
1197
1198static const unsigned slxd_pins[] = {
1199 TEGRA_PIN_SDIO3_DAT7_PD4,
1200};
1201
1202static const unsigned slxk_pins[] = {
1203 TEGRA_PIN_SDIO3_DAT5_PD0,
1204};
1205
1206static const unsigned spdi_pins[] = {
1207 TEGRA_PIN_SPDIF_IN_PK6,
1208};
1209
1210static const unsigned spdo_pins[] = {
1211 TEGRA_PIN_SPDIF_OUT_PK5,
1212};
1213
1214static const unsigned spia_pins[] = {
1215 TEGRA_PIN_SPI2_MOSI_PX0,
1216};
1217
1218static const unsigned spib_pins[] = {
1219 TEGRA_PIN_SPI2_MISO_PX1,
1220};
1221
1222static const unsigned spic_pins[] = {
1223 TEGRA_PIN_SPI2_CS0_N_PX3,
1224 TEGRA_PIN_SPI2_SCK_PX2,
1225};
1226
1227static const unsigned spid_pins[] = {
1228 TEGRA_PIN_SPI1_MOSI_PX4,
1229};
1230
1231static const unsigned spie_pins[] = {
1232 TEGRA_PIN_SPI1_CS0_N_PX6,
1233 TEGRA_PIN_SPI1_SCK_PX5,
1234};
1235
1236static const unsigned spif_pins[] = {
1237 TEGRA_PIN_SPI1_MISO_PX7,
1238};
1239
1240static const unsigned spig_pins[] = {
1241 TEGRA_PIN_SPI2_CS1_N_PW2,
1242};
1243
1244static const unsigned spih_pins[] = {
1245 TEGRA_PIN_SPI2_CS2_N_PW3,
1246};
1247
1248static const unsigned uaa_pins[] = {
1249 TEGRA_PIN_ULPI_DATA0_PO1,
1250 TEGRA_PIN_ULPI_DATA1_PO2,
1251 TEGRA_PIN_ULPI_DATA2_PO3,
1252 TEGRA_PIN_ULPI_DATA3_PO4,
1253};
1254
1255static const unsigned uab_pins[] = {
1256 TEGRA_PIN_ULPI_DATA4_PO5,
1257 TEGRA_PIN_ULPI_DATA5_PO6,
1258 TEGRA_PIN_ULPI_DATA6_PO7,
1259 TEGRA_PIN_ULPI_DATA7_PO0,
1260};
1261
1262static const unsigned uac_pins[] = {
1263 TEGRA_PIN_PV0,
1264 TEGRA_PIN_PV1,
1265 TEGRA_PIN_PV2,
1266 TEGRA_PIN_PV3,
1267};
1268
1269static const unsigned ck32_pins[] = {
1270 TEGRA_PIN_CLK_32_K_IN,
1271};
1272
1273static const unsigned uad_pins[] = {
1274 TEGRA_PIN_UART2_RXD_PC3,
1275 TEGRA_PIN_UART2_TXD_PC2,
1276};
1277
1278static const unsigned uca_pins[] = {
1279 TEGRA_PIN_UART3_RXD_PW7,
1280 TEGRA_PIN_UART3_TXD_PW6,
1281};
1282
1283static const unsigned ucb_pins[] = {
1284 TEGRA_PIN_UART3_CTS_N_PA1,
1285 TEGRA_PIN_UART3_RTS_N_PC0,
1286};
1287
1288static const unsigned uda_pins[] = {
1289 TEGRA_PIN_ULPI_CLK_PY0,
1290 TEGRA_PIN_ULPI_DIR_PY1,
1291 TEGRA_PIN_ULPI_NXT_PY2,
1292 TEGRA_PIN_ULPI_STP_PY3,
1293};
1294
1295static const unsigned ddrc_pins[] = {
1296 TEGRA_PIN_DDR_COMP_PD,
1297 TEGRA_PIN_DDR_COMP_PU,
1298};
1299
1300static const unsigned pmca_pins[] = {
1301 TEGRA_PIN_LED_BLINK_PBB0,
1302};
1303
1304static const unsigned pmcb_pins[] = {
1305 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1306};
1307
1308static const unsigned pmcc_pins[] = {
1309 TEGRA_PIN_CORE_PWR_REQ,
1310};
1311
1312static const unsigned pmcd_pins[] = {
1313 TEGRA_PIN_CPU_PWR_REQ,
1314};
1315
1316static const unsigned pmce_pins[] = {
1317 TEGRA_PIN_PWR_INT_N,
1318};
1319
1320static const unsigned xm2c_pins[] = {
1321 TEGRA_PIN_DDR_A0,
1322 TEGRA_PIN_DDR_A1,
1323 TEGRA_PIN_DDR_A2,
1324 TEGRA_PIN_DDR_A3,
1325 TEGRA_PIN_DDR_A4,
1326 TEGRA_PIN_DDR_A5,
1327 TEGRA_PIN_DDR_A6,
1328 TEGRA_PIN_DDR_A7,
1329 TEGRA_PIN_DDR_A8,
1330 TEGRA_PIN_DDR_A9,
1331 TEGRA_PIN_DDR_A10,
1332 TEGRA_PIN_DDR_A11,
1333 TEGRA_PIN_DDR_A12,
1334 TEGRA_PIN_DDR_A13,
1335 TEGRA_PIN_DDR_A14,
1336 TEGRA_PIN_DDR_CAS_N,
1337 TEGRA_PIN_DDR_BA0,
1338 TEGRA_PIN_DDR_BA1,
1339 TEGRA_PIN_DDR_BA2,
1340 TEGRA_PIN_DDR_DQS0P,
1341 TEGRA_PIN_DDR_DQS0N,
1342 TEGRA_PIN_DDR_DQS1P,
1343 TEGRA_PIN_DDR_DQS1N,
1344 TEGRA_PIN_DDR_DQS2P,
1345 TEGRA_PIN_DDR_DQS2N,
1346 TEGRA_PIN_DDR_DQS3P,
1347 TEGRA_PIN_DDR_DQS3N,
1348 TEGRA_PIN_DDR_CS0_N,
1349 TEGRA_PIN_DDR_CS1_N,
1350 TEGRA_PIN_DDR_CKE0,
1351 TEGRA_PIN_DDR_CKE1,
1352 TEGRA_PIN_DDR_CLK,
1353 TEGRA_PIN_DDR_CLK_N,
1354 TEGRA_PIN_DDR_DM0,
1355 TEGRA_PIN_DDR_DM1,
1356 TEGRA_PIN_DDR_DM2,
1357 TEGRA_PIN_DDR_DM3,
1358 TEGRA_PIN_DDR_ODT,
1359 TEGRA_PIN_DDR_RAS_N,
1360 TEGRA_PIN_DDR_WE_N,
1361 TEGRA_PIN_DDR_QUSE0,
1362 TEGRA_PIN_DDR_QUSE1,
1363 TEGRA_PIN_DDR_QUSE2,
1364 TEGRA_PIN_DDR_QUSE3,
1365};
1366
1367static const unsigned xm2d_pins[] = {
1368 TEGRA_PIN_DDR_DQ0,
1369 TEGRA_PIN_DDR_DQ1,
1370 TEGRA_PIN_DDR_DQ2,
1371 TEGRA_PIN_DDR_DQ3,
1372 TEGRA_PIN_DDR_DQ4,
1373 TEGRA_PIN_DDR_DQ5,
1374 TEGRA_PIN_DDR_DQ6,
1375 TEGRA_PIN_DDR_DQ7,
1376 TEGRA_PIN_DDR_DQ8,
1377 TEGRA_PIN_DDR_DQ9,
1378 TEGRA_PIN_DDR_DQ10,
1379 TEGRA_PIN_DDR_DQ11,
1380 TEGRA_PIN_DDR_DQ12,
1381 TEGRA_PIN_DDR_DQ13,
1382 TEGRA_PIN_DDR_DQ14,
1383 TEGRA_PIN_DDR_DQ15,
1384 TEGRA_PIN_DDR_DQ16,
1385 TEGRA_PIN_DDR_DQ17,
1386 TEGRA_PIN_DDR_DQ18,
1387 TEGRA_PIN_DDR_DQ19,
1388 TEGRA_PIN_DDR_DQ20,
1389 TEGRA_PIN_DDR_DQ21,
1390 TEGRA_PIN_DDR_DQ22,
1391 TEGRA_PIN_DDR_DQ23,
1392 TEGRA_PIN_DDR_DQ24,
1393 TEGRA_PIN_DDR_DQ25,
1394 TEGRA_PIN_DDR_DQ26,
1395 TEGRA_PIN_DDR_DQ27,
1396 TEGRA_PIN_DDR_DQ28,
1397 TEGRA_PIN_DDR_DQ29,
1398 TEGRA_PIN_DDR_DQ30,
1399 TEGRA_PIN_DDR_DQ31,
1400};
1401
1402static const unsigned drive_ao1_pins[] = {
1403 TEGRA_PIN_SYS_RESET,
1404 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1405 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1406 TEGRA_PIN_KB_ROW0_PR0,
1407 TEGRA_PIN_KB_ROW1_PR1,
1408 TEGRA_PIN_KB_ROW2_PR2,
1409 TEGRA_PIN_KB_ROW3_PR3,
1410 TEGRA_PIN_KB_ROW4_PR4,
1411 TEGRA_PIN_KB_ROW5_PR5,
1412 TEGRA_PIN_KB_ROW6_PR6,
1413 TEGRA_PIN_KB_ROW7_PR7,
1414};
1415
1416static const unsigned drive_ao2_pins[] = {
1417 TEGRA_PIN_KB_ROW8_PS0,
1418 TEGRA_PIN_KB_ROW9_PS1,
1419 TEGRA_PIN_KB_ROW10_PS2,
1420 TEGRA_PIN_KB_ROW11_PS3,
1421 TEGRA_PIN_KB_ROW12_PS4,
1422 TEGRA_PIN_KB_ROW13_PS5,
1423 TEGRA_PIN_KB_ROW14_PS6,
1424 TEGRA_PIN_KB_ROW15_PS7,
1425 TEGRA_PIN_KB_COL0_PQ0,
1426 TEGRA_PIN_KB_COL1_PQ1,
1427 TEGRA_PIN_KB_COL2_PQ2,
1428 TEGRA_PIN_KB_COL3_PQ3,
1429 TEGRA_PIN_KB_COL4_PQ4,
1430 TEGRA_PIN_KB_COL5_PQ5,
1431 TEGRA_PIN_KB_COL6_PQ6,
1432 TEGRA_PIN_KB_COL7_PQ7,
1433 TEGRA_PIN_LED_BLINK_PBB0,
1434 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1435 TEGRA_PIN_CORE_PWR_REQ,
1436 TEGRA_PIN_CPU_PWR_REQ,
1437 TEGRA_PIN_PWR_INT_N,
1438 TEGRA_PIN_CLK_32_K_IN,
1439};
1440
1441static const unsigned drive_at1_pins[] = {
1442 TEGRA_PIN_GMI_IORDY_PI5,
1443 TEGRA_PIN_GMI_AD8_PH0,
1444 TEGRA_PIN_GMI_AD9_PH1,
1445 TEGRA_PIN_GMI_AD10_PH2,
1446 TEGRA_PIN_GMI_AD11_PH3,
1447 TEGRA_PIN_GMI_AD12_PH4,
1448 TEGRA_PIN_GMI_AD13_PH5,
1449 TEGRA_PIN_GMI_AD14_PH6,
1450 TEGRA_PIN_GMI_AD15_PH7,
1451 TEGRA_PIN_GMI_CS7_N_PI6,
1452 TEGRA_PIN_GMI_DPD_PT7,
1453 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1454 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1455};
1456
1457static const unsigned drive_at2_pins[] = {
1458 TEGRA_PIN_GMI_WAIT_PI7,
1459 TEGRA_PIN_GMI_ADV_N_PK0,
1460 TEGRA_PIN_GMI_CLK_PK1,
1461 TEGRA_PIN_GMI_CS6_N_PI3,
1462 TEGRA_PIN_GMI_CS5_N_PI2,
1463 TEGRA_PIN_GMI_CS4_N_PK2,
1464 TEGRA_PIN_GMI_CS3_N_PK4,
1465 TEGRA_PIN_GMI_CS2_N_PK3,
1466 TEGRA_PIN_GMI_AD0_PG0,
1467 TEGRA_PIN_GMI_AD1_PG1,
1468 TEGRA_PIN_GMI_AD2_PG2,
1469 TEGRA_PIN_GMI_AD3_PG3,
1470 TEGRA_PIN_GMI_AD4_PG4,
1471 TEGRA_PIN_GMI_AD5_PG5,
1472 TEGRA_PIN_GMI_AD6_PG6,
1473 TEGRA_PIN_GMI_AD7_PG7,
1474 TEGRA_PIN_GMI_HIOW_N_PI0,
1475 TEGRA_PIN_GMI_HIOR_N_PI1,
1476 TEGRA_PIN_GMI_RST_N_PI4,
1477};
1478
1479static const unsigned drive_cdev1_pins[] = {
1480 TEGRA_PIN_DAP_MCLK1_PW4,
1481};
1482
1483static const unsigned drive_cdev2_pins[] = {
1484 TEGRA_PIN_DAP_MCLK2_PW5,
1485};
1486
1487static const unsigned drive_csus_pins[] = {
1488 TEGRA_PIN_VI_MCLK_PT1,
1489};
1490
1491static const unsigned drive_dap1_pins[] = {
1492 TEGRA_PIN_DAP1_FS_PN0,
1493 TEGRA_PIN_DAP1_DIN_PN1,
1494 TEGRA_PIN_DAP1_DOUT_PN2,
1495 TEGRA_PIN_DAP1_SCLK_PN3,
1496 TEGRA_PIN_SPDIF_OUT_PK5,
1497 TEGRA_PIN_SPDIF_IN_PK6,
1498};
1499
1500static const unsigned drive_dap2_pins[] = {
1501 TEGRA_PIN_DAP2_FS_PA2,
1502 TEGRA_PIN_DAP2_SCLK_PA3,
1503 TEGRA_PIN_DAP2_DIN_PA4,
1504 TEGRA_PIN_DAP2_DOUT_PA5,
1505};
1506
1507static const unsigned drive_dap3_pins[] = {
1508 TEGRA_PIN_DAP3_FS_PP0,
1509 TEGRA_PIN_DAP3_DIN_PP1,
1510 TEGRA_PIN_DAP3_DOUT_PP2,
1511 TEGRA_PIN_DAP3_SCLK_PP3,
1512};
1513
1514static const unsigned drive_dap4_pins[] = {
1515 TEGRA_PIN_DAP4_FS_PP4,
1516 TEGRA_PIN_DAP4_DIN_PP5,
1517 TEGRA_PIN_DAP4_DOUT_PP6,
1518 TEGRA_PIN_DAP4_SCLK_PP7,
1519};
1520
1521static const unsigned drive_dbg_pins[] = {
1522 TEGRA_PIN_PU0,
1523 TEGRA_PIN_PU1,
1524 TEGRA_PIN_PU2,
1525 TEGRA_PIN_PU3,
1526 TEGRA_PIN_PU4,
1527 TEGRA_PIN_PU5,
1528 TEGRA_PIN_PU6,
1529 TEGRA_PIN_JTAG_RTCK_PU7,
1530 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1531 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1532 TEGRA_PIN_JTAG_TRST_N,
1533 TEGRA_PIN_JTAG_TDO,
1534 TEGRA_PIN_JTAG_TMS,
1535 TEGRA_PIN_JTAG_TCK,
1536 TEGRA_PIN_JTAG_TDI,
1537 TEGRA_PIN_TEST_MODE_EN,
1538};
1539
1540static const unsigned drive_lcd1_pins[] = {
1541 TEGRA_PIN_LCD_PWR1_PC1,
1542 TEGRA_PIN_LCD_PWR2_PC6,
1543 TEGRA_PIN_LCD_SDIN_PZ2,
1544 TEGRA_PIN_LCD_SDOUT_PN5,
1545 TEGRA_PIN_LCD_WR_N_PZ3,
1546 TEGRA_PIN_LCD_CS0_N_PN4,
1547 TEGRA_PIN_LCD_DC0_PN6,
1548 TEGRA_PIN_LCD_SCK_PZ4,
1549};
1550
1551static const unsigned drive_lcd2_pins[] = {
1552 TEGRA_PIN_LCD_PWR0_PB2,
1553 TEGRA_PIN_LCD_PCLK_PB3,
1554 TEGRA_PIN_LCD_DE_PJ1,
1555 TEGRA_PIN_LCD_HSYNC_PJ3,
1556 TEGRA_PIN_LCD_VSYNC_PJ4,
1557 TEGRA_PIN_LCD_D0_PE0,
1558 TEGRA_PIN_LCD_D1_PE1,
1559 TEGRA_PIN_LCD_D2_PE2,
1560 TEGRA_PIN_LCD_D3_PE3,
1561 TEGRA_PIN_LCD_D4_PE4,
1562 TEGRA_PIN_LCD_D5_PE5,
1563 TEGRA_PIN_LCD_D6_PE6,
1564 TEGRA_PIN_LCD_D7_PE7,
1565 TEGRA_PIN_LCD_D8_PF0,
1566 TEGRA_PIN_LCD_D9_PF1,
1567 TEGRA_PIN_LCD_D10_PF2,
1568 TEGRA_PIN_LCD_D11_PF3,
1569 TEGRA_PIN_LCD_D12_PF4,
1570 TEGRA_PIN_LCD_D13_PF5,
1571 TEGRA_PIN_LCD_D14_PF6,
1572 TEGRA_PIN_LCD_D15_PF7,
1573 TEGRA_PIN_LCD_D16_PM0,
1574 TEGRA_PIN_LCD_D17_PM1,
1575 TEGRA_PIN_LCD_D18_PM2,
1576 TEGRA_PIN_LCD_D19_PM3,
1577 TEGRA_PIN_LCD_D20_PM4,
1578 TEGRA_PIN_LCD_D21_PM5,
1579 TEGRA_PIN_LCD_D22_PM6,
1580 TEGRA_PIN_LCD_D23_PM7,
1581 TEGRA_PIN_LCD_CS1_N_PW0,
1582 TEGRA_PIN_LCD_M1_PW1,
1583 TEGRA_PIN_LCD_DC1_PV7,
1584 TEGRA_PIN_HDMI_INT_N_PN7,
1585};
1586
1587static const unsigned drive_sdmmc2_pins[] = {
1588 TEGRA_PIN_SDIO3_DAT4_PD1,
1589 TEGRA_PIN_SDIO3_DAT5_PD0,
1590 TEGRA_PIN_SDIO3_DAT6_PD3,
1591 TEGRA_PIN_SDIO3_DAT7_PD4,
1592};
1593
1594static const unsigned drive_sdmmc3_pins[] = {
1595 TEGRA_PIN_SDIO3_CLK_PA6,
1596 TEGRA_PIN_SDIO3_CMD_PA7,
1597 TEGRA_PIN_SDIO3_DAT0_PB7,
1598 TEGRA_PIN_SDIO3_DAT1_PB6,
1599 TEGRA_PIN_SDIO3_DAT2_PB5,
1600 TEGRA_PIN_SDIO3_DAT3_PB4,
1601 TEGRA_PIN_PV4,
1602 TEGRA_PIN_PV5,
1603 TEGRA_PIN_PV6,
1604};
1605
1606static const unsigned drive_spi_pins[] = {
1607 TEGRA_PIN_SPI2_MOSI_PX0,
1608 TEGRA_PIN_SPI2_MISO_PX1,
1609 TEGRA_PIN_SPI2_SCK_PX2,
1610 TEGRA_PIN_SPI2_CS0_N_PX3,
1611 TEGRA_PIN_SPI1_MOSI_PX4,
1612 TEGRA_PIN_SPI1_SCK_PX5,
1613 TEGRA_PIN_SPI1_CS0_N_PX6,
1614 TEGRA_PIN_SPI1_MISO_PX7,
1615 TEGRA_PIN_SPI2_CS1_N_PW2,
1616 TEGRA_PIN_SPI2_CS2_N_PW3,
1617};
1618
1619static const unsigned drive_uaa_pins[] = {
1620 TEGRA_PIN_ULPI_DATA0_PO1,
1621 TEGRA_PIN_ULPI_DATA1_PO2,
1622 TEGRA_PIN_ULPI_DATA2_PO3,
1623 TEGRA_PIN_ULPI_DATA3_PO4,
1624};
1625
1626static const unsigned drive_uab_pins[] = {
1627 TEGRA_PIN_ULPI_DATA4_PO5,
1628 TEGRA_PIN_ULPI_DATA5_PO6,
1629 TEGRA_PIN_ULPI_DATA6_PO7,
1630 TEGRA_PIN_ULPI_DATA7_PO0,
1631 TEGRA_PIN_PV0,
1632 TEGRA_PIN_PV1,
1633 TEGRA_PIN_PV2,
1634 TEGRA_PIN_PV3,
1635};
1636
1637static const unsigned drive_uart2_pins[] = {
1638 TEGRA_PIN_UART2_TXD_PC2,
1639 TEGRA_PIN_UART2_RXD_PC3,
1640 TEGRA_PIN_UART2_RTS_N_PJ6,
1641 TEGRA_PIN_UART2_CTS_N_PJ5,
1642};
1643
1644static const unsigned drive_uart3_pins[] = {
1645 TEGRA_PIN_UART3_TXD_PW6,
1646 TEGRA_PIN_UART3_RXD_PW7,
1647 TEGRA_PIN_UART3_RTS_N_PC0,
1648 TEGRA_PIN_UART3_CTS_N_PA1,
1649};
1650
1651static const unsigned drive_vi1_pins[] = {
1652 TEGRA_PIN_VI_D0_PT4,
1653 TEGRA_PIN_VI_D1_PD5,
1654 TEGRA_PIN_VI_D2_PL0,
1655 TEGRA_PIN_VI_D3_PL1,
1656 TEGRA_PIN_VI_D4_PL2,
1657 TEGRA_PIN_VI_D5_PL3,
1658 TEGRA_PIN_VI_D6_PL4,
1659 TEGRA_PIN_VI_D7_PL5,
1660 TEGRA_PIN_VI_D8_PL6,
1661 TEGRA_PIN_VI_D9_PL7,
1662 TEGRA_PIN_VI_D10_PT2,
1663 TEGRA_PIN_VI_D11_PT3,
1664 TEGRA_PIN_VI_PCLK_PT0,
1665 TEGRA_PIN_VI_VSYNC_PD6,
1666 TEGRA_PIN_VI_HSYNC_PD7,
1667};
1668
1669static const unsigned drive_vi2_pins[] = {
1670 TEGRA_PIN_VI_GP0_PBB1,
1671 TEGRA_PIN_CAM_I2C_SCL_PBB2,
1672 TEGRA_PIN_CAM_I2C_SDA_PBB3,
1673 TEGRA_PIN_VI_GP3_PBB4,
1674 TEGRA_PIN_VI_GP4_PBB5,
1675 TEGRA_PIN_VI_GP5_PD2,
1676 TEGRA_PIN_VI_GP6_PA0,
1677};
1678
1679static const unsigned drive_xm2a_pins[] = {
1680 TEGRA_PIN_DDR_A0,
1681 TEGRA_PIN_DDR_A1,
1682 TEGRA_PIN_DDR_A2,
1683 TEGRA_PIN_DDR_A3,
1684 TEGRA_PIN_DDR_A4,
1685 TEGRA_PIN_DDR_A5,
1686 TEGRA_PIN_DDR_A6,
1687 TEGRA_PIN_DDR_A7,
1688 TEGRA_PIN_DDR_A8,
1689 TEGRA_PIN_DDR_A9,
1690 TEGRA_PIN_DDR_A10,
1691 TEGRA_PIN_DDR_A11,
1692 TEGRA_PIN_DDR_A12,
1693 TEGRA_PIN_DDR_A13,
1694 TEGRA_PIN_DDR_A14,
1695 TEGRA_PIN_DDR_BA0,
1696 TEGRA_PIN_DDR_BA1,
1697 TEGRA_PIN_DDR_BA2,
1698 TEGRA_PIN_DDR_CS0_N,
1699 TEGRA_PIN_DDR_CS1_N,
1700 TEGRA_PIN_DDR_ODT,
1701 TEGRA_PIN_DDR_RAS_N,
1702 TEGRA_PIN_DDR_CAS_N,
1703 TEGRA_PIN_DDR_WE_N,
1704 TEGRA_PIN_DDR_CKE0,
1705 TEGRA_PIN_DDR_CKE1,
1706};
1707
1708static const unsigned drive_xm2c_pins[] = {
1709 TEGRA_PIN_DDR_DQS0P,
1710 TEGRA_PIN_DDR_DQS0N,
1711 TEGRA_PIN_DDR_DQS1P,
1712 TEGRA_PIN_DDR_DQS1N,
1713 TEGRA_PIN_DDR_DQS2P,
1714 TEGRA_PIN_DDR_DQS2N,
1715 TEGRA_PIN_DDR_DQS3P,
1716 TEGRA_PIN_DDR_DQS3N,
1717 TEGRA_PIN_DDR_QUSE0,
1718 TEGRA_PIN_DDR_QUSE1,
1719 TEGRA_PIN_DDR_QUSE2,
1720 TEGRA_PIN_DDR_QUSE3,
1721};
1722
1723static const unsigned drive_xm2d_pins[] = {
1724 TEGRA_PIN_DDR_DQ0,
1725 TEGRA_PIN_DDR_DQ1,
1726 TEGRA_PIN_DDR_DQ2,
1727 TEGRA_PIN_DDR_DQ3,
1728 TEGRA_PIN_DDR_DQ4,
1729 TEGRA_PIN_DDR_DQ5,
1730 TEGRA_PIN_DDR_DQ6,
1731 TEGRA_PIN_DDR_DQ7,
1732 TEGRA_PIN_DDR_DQ8,
1733 TEGRA_PIN_DDR_DQ9,
1734 TEGRA_PIN_DDR_DQ10,
1735 TEGRA_PIN_DDR_DQ11,
1736 TEGRA_PIN_DDR_DQ12,
1737 TEGRA_PIN_DDR_DQ13,
1738 TEGRA_PIN_DDR_DQ14,
1739 TEGRA_PIN_DDR_DQ15,
1740 TEGRA_PIN_DDR_DQ16,
1741 TEGRA_PIN_DDR_DQ17,
1742 TEGRA_PIN_DDR_DQ18,
1743 TEGRA_PIN_DDR_DQ19,
1744 TEGRA_PIN_DDR_DQ20,
1745 TEGRA_PIN_DDR_DQ21,
1746 TEGRA_PIN_DDR_DQ22,
1747 TEGRA_PIN_DDR_DQ23,
1748 TEGRA_PIN_DDR_DQ24,
1749 TEGRA_PIN_DDR_DQ25,
1750 TEGRA_PIN_DDR_DQ26,
1751 TEGRA_PIN_DDR_DQ27,
1752 TEGRA_PIN_DDR_DQ28,
1753 TEGRA_PIN_DDR_DQ29,
1754 TEGRA_PIN_DDR_DQ30,
1755 TEGRA_PIN_DDR_DQ31,
1756 TEGRA_PIN_DDR_DM0,
1757 TEGRA_PIN_DDR_DM1,
1758 TEGRA_PIN_DDR_DM2,
1759 TEGRA_PIN_DDR_DM3,
1760};
1761
1762static const unsigned drive_xm2clk_pins[] = {
1763 TEGRA_PIN_DDR_CLK,
1764 TEGRA_PIN_DDR_CLK_N,
1765};
1766
1767static const unsigned drive_sdio1_pins[] = {
1768 TEGRA_PIN_SDIO1_CLK_PZ0,
1769 TEGRA_PIN_SDIO1_CMD_PZ1,
1770 TEGRA_PIN_SDIO1_DAT0_PY7,
1771 TEGRA_PIN_SDIO1_DAT1_PY6,
1772 TEGRA_PIN_SDIO1_DAT2_PY5,
1773 TEGRA_PIN_SDIO1_DAT3_PY4,
1774};
1775
1776static const unsigned drive_crt_pins[] = {
1777 TEGRA_PIN_CRT_HSYNC,
1778 TEGRA_PIN_CRT_VSYNC,
1779};
1780
1781static const unsigned drive_ddc_pins[] = {
1782 TEGRA_PIN_DDC_SCL,
1783 TEGRA_PIN_DDC_SDA,
1784};
1785
1786static const unsigned drive_gma_pins[] = {
1787 TEGRA_PIN_GMI_AD20_PAA0,
1788 TEGRA_PIN_GMI_AD21_PAA1,
1789 TEGRA_PIN_GMI_AD22_PAA2,
1790 TEGRA_PIN_GMI_AD23_PAA3,
1791};
1792
1793static const unsigned drive_gmb_pins[] = {
1794 TEGRA_PIN_GMI_WP_N_PC7,
1795};
1796
1797static const unsigned drive_gmc_pins[] = {
1798 TEGRA_PIN_GMI_AD16_PJ7,
1799 TEGRA_PIN_GMI_AD17_PB0,
1800 TEGRA_PIN_GMI_AD18_PB1,
1801 TEGRA_PIN_GMI_AD19_PK7,
1802};
1803
1804static const unsigned drive_gmd_pins[] = {
1805 TEGRA_PIN_GMI_CS0_N_PJ0,
1806 TEGRA_PIN_GMI_CS1_N_PJ2,
1807};
1808
1809static const unsigned drive_gme_pins[] = {
1810 TEGRA_PIN_GMI_AD24_PAA4,
1811 TEGRA_PIN_GMI_AD25_PAA5,
1812 TEGRA_PIN_GMI_AD26_PAA6,
1813 TEGRA_PIN_GMI_AD27_PAA7,
1814};
1815
1816static const unsigned drive_owr_pins[] = {
1817 TEGRA_PIN_OWC,
1818};
1819
1820static const unsigned drive_uda_pins[] = {
1821 TEGRA_PIN_ULPI_CLK_PY0,
1822 TEGRA_PIN_ULPI_DIR_PY1,
1823 TEGRA_PIN_ULPI_NXT_PY2,
1824 TEGRA_PIN_ULPI_STP_PY3,
1825};
1826
1827enum tegra_mux {
1828 TEGRA_MUX_AHB_CLK,
1829 TEGRA_MUX_APB_CLK,
1830 TEGRA_MUX_AUDIO_SYNC,
1831 TEGRA_MUX_CRT,
1832 TEGRA_MUX_DAP1,
1833 TEGRA_MUX_DAP2,
1834 TEGRA_MUX_DAP3,
1835 TEGRA_MUX_DAP4,
1836 TEGRA_MUX_DAP5,
1837 TEGRA_MUX_DISPLAYA,
1838 TEGRA_MUX_DISPLAYB,
1839 TEGRA_MUX_EMC_TEST0_DLL,
1840 TEGRA_MUX_EMC_TEST1_DLL,
1841 TEGRA_MUX_GMI,
1842 TEGRA_MUX_GMI_INT,
1843 TEGRA_MUX_HDMI,
1844 TEGRA_MUX_I2CP,
1845 TEGRA_MUX_I2C1,
1846 TEGRA_MUX_I2C2,
1847 TEGRA_MUX_I2C3,
1848 TEGRA_MUX_IDE,
1849 TEGRA_MUX_IRDA,
1850 TEGRA_MUX_KBC,
1851 TEGRA_MUX_MIO,
1852 TEGRA_MUX_MIPI_HS,
1853 TEGRA_MUX_NAND,
1854 TEGRA_MUX_OSC,
1855 TEGRA_MUX_OWR,
1856 TEGRA_MUX_PCIE,
1857 TEGRA_MUX_PLLA_OUT,
1858 TEGRA_MUX_PLLC_OUT1,
1859 TEGRA_MUX_PLLM_OUT1,
1860 TEGRA_MUX_PLLP_OUT2,
1861 TEGRA_MUX_PLLP_OUT3,
1862 TEGRA_MUX_PLLP_OUT4,
1863 TEGRA_MUX_PWM,
1864 TEGRA_MUX_PWR_INTR,
1865 TEGRA_MUX_PWR_ON,
1866 TEGRA_MUX_RSVD1,
1867 TEGRA_MUX_RSVD2,
1868 TEGRA_MUX_RSVD3,
1869 TEGRA_MUX_RSVD4,
1870 TEGRA_MUX_RTCK,
1871 TEGRA_MUX_SDIO1,
1872 TEGRA_MUX_SDIO2,
1873 TEGRA_MUX_SDIO3,
1874 TEGRA_MUX_SDIO4,
1875 TEGRA_MUX_SFLASH,
1876 TEGRA_MUX_SPDIF,
1877 TEGRA_MUX_SPI1,
1878 TEGRA_MUX_SPI2,
1879 TEGRA_MUX_SPI2_ALT,
1880 TEGRA_MUX_SPI3,
1881 TEGRA_MUX_SPI4,
1882 TEGRA_MUX_TRACE,
1883 TEGRA_MUX_TWC,
1884 TEGRA_MUX_UARTA,
1885 TEGRA_MUX_UARTB,
1886 TEGRA_MUX_UARTC,
1887 TEGRA_MUX_UARTD,
1888 TEGRA_MUX_UARTE,
1889 TEGRA_MUX_ULPI,
1890 TEGRA_MUX_VI,
1891 TEGRA_MUX_VI_SENSOR_CLK,
1892 TEGRA_MUX_XIO,
1893};
1894
1895static const char * const ahb_clk_groups[] = {
1896 "cdev2",
1897};
1898
1899static const char * const apb_clk_groups[] = {
1900 "cdev2",
1901};
1902
1903static const char * const audio_sync_groups[] = {
1904 "cdev1",
1905};
1906
1907static const char * const crt_groups[] = {
1908 "crtp",
1909 "lm1",
1910};
1911
1912static const char * const dap1_groups[] = {
1913 "dap1",
1914};
1915
1916static const char * const dap2_groups[] = {
1917 "dap2",
1918};
1919
1920static const char * const dap3_groups[] = {
1921 "dap3",
1922};
1923
1924static const char * const dap4_groups[] = {
1925 "dap4",
1926};
1927
1928static const char * const dap5_groups[] = {
1929 "gme",
1930};
1931
1932static const char * const displaya_groups[] = {
1933 "lcsn",
1934 "ld0",
1935 "ld1",
1936 "ld10",
1937 "ld11",
1938 "ld12",
1939 "ld13",
1940 "ld14",
1941 "ld15",
1942 "ld16",
1943 "ld17",
1944 "ld2",
1945 "ld3",
1946 "ld4",
1947 "ld5",
1948 "ld6",
1949 "ld7",
1950 "ld8",
1951 "ld9",
1952 "ldc",
1953 "ldi",
1954 "lhp0",
1955 "lhp1",
1956 "lhp2",
1957 "lhs",
1958 "lm0",
1959 "lm1",
1960 "lpp",
1961 "lpw0",
1962 "lpw1",
1963 "lpw2",
1964 "lsc0",
1965 "lsc1",
1966 "lsck",
1967 "lsda",
1968 "lsdi",
1969 "lspi",
1970 "lvp0",
1971 "lvp1",
1972 "lvs",
1973};
1974
1975static const char * const displayb_groups[] = {
1976 "lcsn",
1977 "ld0",
1978 "ld1",
1979 "ld10",
1980 "ld11",
1981 "ld12",
1982 "ld13",
1983 "ld14",
1984 "ld15",
1985 "ld16",
1986 "ld17",
1987 "ld2",
1988 "ld3",
1989 "ld4",
1990 "ld5",
1991 "ld6",
1992 "ld7",
1993 "ld8",
1994 "ld9",
1995 "ldc",
1996 "ldi",
1997 "lhp0",
1998 "lhp1",
1999 "lhp2",
2000 "lhs",
2001 "lm0",
2002 "lm1",
2003 "lpp",
2004 "lpw0",
2005 "lpw1",
2006 "lpw2",
2007 "lsc0",
2008 "lsc1",
2009 "lsck",
2010 "lsda",
2011 "lsdi",
2012 "lspi",
2013 "lvp0",
2014 "lvp1",
2015 "lvs",
2016};
2017
2018static const char * const emc_test0_dll_groups[] = {
2019 "kbca",
2020};
2021
2022static const char * const emc_test1_dll_groups[] = {
2023 "kbcc",
2024};
2025
2026static const char * const gmi_groups[] = {
2027 "ata",
2028 "atb",
2029 "atc",
2030 "atd",
2031 "ate",
2032 "dap1",
2033 "dap2",
2034 "dap4",
2035 "gma",
2036 "gmb",
2037 "gmc",
2038 "gmd",
2039 "gme",
2040 "gpu",
2041 "irrx",
2042 "irtx",
2043 "pta",
2044 "spia",
2045 "spib",
2046 "spic",
2047 "spid",
2048 "spie",
2049 "uca",
2050 "ucb",
2051};
2052
2053static const char * const gmi_int_groups[] = {
2054 "gmb",
2055};
2056
2057static const char * const hdmi_groups[] = {
2058 "hdint",
2059 "lpw0",
2060 "lpw2",
2061 "lsc1",
2062 "lsck",
2063 "lsda",
2064 "lspi",
2065 "pta",
2066};
2067
2068static const char * const i2cp_groups[] = {
2069 "i2cp",
2070};
2071
2072static const char * const i2c1_groups[] = {
2073 "rm",
2074 "spdi",
2075 "spdo",
2076 "spig",
2077 "spih",
2078};
2079
2080static const char * const i2c2_groups[] = {
2081 "ddc",
2082 "pta",
2083};
2084
2085static const char * const i2c3_groups[] = {
2086 "dtf",
2087};
2088
2089static const char * const ide_groups[] = {
2090 "ata",
2091 "atb",
2092 "atc",
2093 "atd",
2094 "ate",
2095 "gmb",
2096};
2097
2098static const char * const irda_groups[] = {
2099 "uad",
2100};
2101
2102static const char * const kbc_groups[] = {
2103 "kbca",
2104 "kbcb",
2105 "kbcc",
2106 "kbcd",
2107 "kbce",
2108 "kbcf",
2109};
2110
2111static const char * const mio_groups[] = {
2112 "kbcb",
2113 "kbcd",
2114 "kbcf",
2115};
2116
2117static const char * const mipi_hs_groups[] = {
2118 "uaa",
2119 "uab",
2120};
2121
2122static const char * const nand_groups[] = {
2123 "ata",
2124 "atb",
2125 "atc",
2126 "atd",
2127 "ate",
2128 "gmb",
2129 "gmd",
2130 "kbca",
2131 "kbcb",
2132 "kbcc",
2133 "kbcd",
2134 "kbce",
2135 "kbcf",
2136};
2137
2138static const char * const osc_groups[] = {
2139 "cdev1",
2140 "cdev2",
2141};
2142
2143static const char * const owr_groups[] = {
2144 "kbce",
2145 "owc",
2146 "uac",
2147};
2148
2149static const char * const pcie_groups[] = {
2150 "gpv",
2151 "slxa",
2152 "slxk",
2153};
2154
2155static const char * const plla_out_groups[] = {
2156 "cdev1",
2157};
2158
2159static const char * const pllc_out1_groups[] = {
2160 "csus",
2161};
2162
2163static const char * const pllm_out1_groups[] = {
2164 "cdev1",
2165};
2166
2167static const char * const pllp_out2_groups[] = {
2168 "csus",
2169};
2170
2171static const char * const pllp_out3_groups[] = {
2172 "csus",
2173};
2174
2175static const char * const pllp_out4_groups[] = {
2176 "cdev2",
2177};
2178
2179static const char * const pwm_groups[] = {
2180 "gpu",
2181 "sdb",
2182 "sdc",
2183 "sdd",
2184 "ucb",
2185};
2186
2187static const char * const pwr_intr_groups[] = {
2188 "pmc",
2189};
2190
2191static const char * const pwr_on_groups[] = {
2192 "pmc",
2193};
2194
2195static const char * const rsvd1_groups[] = {
2196 "dta",
2197 "dtb",
2198 "dtc",
2199 "dtd",
2200 "dte",
2201 "gmd",
2202 "gme",
2203};
2204
2205static const char * const rsvd2_groups[] = {
2206 "crtp",
2207 "dap1",
2208 "dap3",
2209 "dap4",
2210 "ddc",
2211 "dtb",
2212 "dtc",
2213 "dte",
2214 "dtf",
2215 "gpu7",
2216 "gpv",
2217 "hdint",
2218 "i2cp",
2219 "owc",
2220 "rm",
2221 "sdio1",
2222 "spdi",
2223 "spdo",
2224 "uac",
2225 "uca",
2226 "uda",
2227};
2228
2229static const char * const rsvd3_groups[] = {
2230 "crtp",
2231 "dap2",
2232 "dap3",
2233 "ddc",
2234 "gpu7",
2235 "gpv",
2236 "hdint",
2237 "i2cp",
2238 "ld17",
2239 "ldc",
2240 "ldi",
2241 "lhp0",
2242 "lhp1",
2243 "lhp2",
2244 "lm1",
2245 "lpp",
2246 "lpw1",
2247 "lvp0",
2248 "lvp1",
2249 "owc",
2250 "pmc",
2251 "rm",
2252 "uac",
2253};
2254
2255static const char * const rsvd4_groups[] = {
2256 "ata",
2257 "ate",
2258 "crtp",
2259 "dap3",
2260 "dap4",
2261 "ddc",
2262 "dta",
2263 "dtc",
2264 "dtd",
2265 "dtf",
2266 "gpu",
2267 "gpu7",
2268 "gpv",
2269 "hdint",
2270 "i2cp",
2271 "kbce",
2272 "lcsn",
2273 "ld0",
2274 "ld1",
2275 "ld2",
2276 "ld3",
2277 "ld4",
2278 "ld5",
2279 "ld6",
2280 "ld7",
2281 "ld8",
2282 "ld9",
2283 "ld10",
2284 "ld11",
2285 "ld12",
2286 "ld13",
2287 "ld14",
2288 "ld15",
2289 "ld16",
2290 "ld17",
2291 "ldc",
2292 "ldi",
2293 "lhp0",
2294 "lhp1",
2295 "lhp2",
2296 "lhs",
2297 "lm0",
2298 "lpp",
2299 "lpw1",
2300 "lsc0",
2301 "lsdi",
2302 "lvp0",
2303 "lvp1",
2304 "lvs",
2305 "owc",
2306 "pmc",
2307 "pta",
2308 "rm",
2309 "spif",
2310 "uac",
2311 "uca",
2312 "ucb",
2313};
2314
2315static const char * const rtck_groups[] = {
2316 "gpu7",
2317};
2318
2319static const char * const sdio1_groups[] = {
2320 "sdio1",
2321};
2322
2323static const char * const sdio2_groups[] = {
2324 "dap1",
2325 "dta",
2326 "dtd",
2327 "kbca",
2328 "kbcb",
2329 "kbcd",
2330 "spdi",
2331 "spdo",
2332};
2333
2334static const char * const sdio3_groups[] = {
2335 "sdb",
2336 "sdc",
2337 "sdd",
2338 "slxa",
2339 "slxc",
2340 "slxd",
2341 "slxk",
2342};
2343
2344static const char * const sdio4_groups[] = {
2345 "atb",
2346 "atc",
2347 "atd",
2348 "gma",
2349 "gme",
2350};
2351
2352static const char * const sflash_groups[] = {
2353 "gmc",
2354 "gmd",
2355};
2356
2357static const char * const spdif_groups[] = {
2358 "slxc",
2359 "slxd",
2360 "spdi",
2361 "spdo",
2362 "uad",
2363};
2364
2365static const char * const spi1_groups[] = {
2366 "dtb",
2367 "dte",
2368 "spia",
2369 "spib",
2370 "spic",
2371 "spid",
2372 "spie",
2373 "spif",
2374 "uda",
2375};
2376
2377static const char * const spi2_groups[] = {
2378 "sdb",
2379 "slxa",
2380 "slxc",
2381 "slxd",
2382 "slxk",
2383 "spia",
2384 "spib",
2385 "spic",
2386 "spid",
2387 "spie",
2388 "spif",
2389 "spig",
2390 "spih",
2391 "uab",
2392};
2393
2394static const char * const spi2_alt_groups[] = {
2395 "spid",
2396 "spie",
2397 "spig",
2398 "spih",
2399};
2400
2401static const char * const spi3_groups[] = {
2402 "gma",
2403 "lcsn",
2404 "lm0",
2405 "lpw0",
2406 "lpw2",
2407 "lsc1",
2408 "lsck",
2409 "lsda",
2410 "lsdi",
2411 "sdc",
2412 "sdd",
2413 "spia",
2414 "spib",
2415 "spic",
2416 "spif",
2417 "spig",
2418 "spih",
2419 "uaa",
2420};
2421
2422static const char * const spi4_groups[] = {
2423 "gmc",
2424 "irrx",
2425 "irtx",
2426 "slxa",
2427 "slxc",
2428 "slxd",
2429 "slxk",
2430 "uad",
2431};
2432
2433static const char * const trace_groups[] = {
2434 "kbcc",
2435 "kbcf",
2436};
2437
2438static const char * const twc_groups[] = {
2439 "dap2",
2440 "sdc",
2441};
2442
2443static const char * const uarta_groups[] = {
2444 "gpu",
2445 "irrx",
2446 "irtx",
2447 "sdb",
2448 "sdd",
2449 "sdio1",
2450 "uaa",
2451 "uab",
2452 "uad",
2453};
2454
2455static const char * const uartb_groups[] = {
2456 "irrx",
2457 "irtx",
2458};
2459
2460static const char * const uartc_groups[] = {
2461 "uca",
2462 "ucb",
2463};
2464
2465static const char * const uartd_groups[] = {
2466 "gmc",
2467 "uda",
2468};
2469
2470static const char * const uarte_groups[] = {
2471 "gma",
2472 "sdio1",
2473};
2474
2475static const char * const ulpi_groups[] = {
2476 "uaa",
2477 "uab",
2478 "uda",
2479};
2480
2481static const char * const vi_groups[] = {
2482 "dta",
2483 "dtb",
2484 "dtc",
2485 "dtd",
2486 "dte",
2487 "dtf",
2488};
2489
2490static const char * const vi_sensor_clk_groups[] = {
2491 "csus",
2492};
2493
2494static const char * const xio_groups[] = {
2495 "ld0",
2496 "ld1",
2497 "ld10",
2498 "ld11",
2499 "ld12",
2500 "ld13",
2501 "ld14",
2502 "ld15",
2503 "ld16",
2504 "ld2",
2505 "ld3",
2506 "ld4",
2507 "ld5",
2508 "ld6",
2509 "ld7",
2510 "ld8",
2511 "ld9",
2512 "lhs",
2513 "lsc0",
2514 "lspi",
2515 "lvs",
2516};
2517
2518#define FUNCTION(fname) \
2519 { \
2520 .name = #fname, \
2521 .groups = fname##_groups, \
2522 .ngroups = ARRAY_SIZE(fname##_groups), \
2523 }
2524
2525static const struct tegra_function tegra20_functions[] = {
2526 FUNCTION(ahb_clk),
2527 FUNCTION(apb_clk),
2528 FUNCTION(audio_sync),
2529 FUNCTION(crt),
2530 FUNCTION(dap1),
2531 FUNCTION(dap2),
2532 FUNCTION(dap3),
2533 FUNCTION(dap4),
2534 FUNCTION(dap5),
2535 FUNCTION(displaya),
2536 FUNCTION(displayb),
2537 FUNCTION(emc_test0_dll),
2538 FUNCTION(emc_test1_dll),
2539 FUNCTION(gmi),
2540 FUNCTION(gmi_int),
2541 FUNCTION(hdmi),
2542 FUNCTION(i2cp),
2543 FUNCTION(i2c1),
2544 FUNCTION(i2c2),
2545 FUNCTION(i2c3),
2546 FUNCTION(ide),
2547 FUNCTION(irda),
2548 FUNCTION(kbc),
2549 FUNCTION(mio),
2550 FUNCTION(mipi_hs),
2551 FUNCTION(nand),
2552 FUNCTION(osc),
2553 FUNCTION(owr),
2554 FUNCTION(pcie),
2555 FUNCTION(plla_out),
2556 FUNCTION(pllc_out1),
2557 FUNCTION(pllm_out1),
2558 FUNCTION(pllp_out2),
2559 FUNCTION(pllp_out3),
2560 FUNCTION(pllp_out4),
2561 FUNCTION(pwm),
2562 FUNCTION(pwr_intr),
2563 FUNCTION(pwr_on),
2564 FUNCTION(rsvd1),
2565 FUNCTION(rsvd2),
2566 FUNCTION(rsvd3),
2567 FUNCTION(rsvd4),
2568 FUNCTION(rtck),
2569 FUNCTION(sdio1),
2570 FUNCTION(sdio2),
2571 FUNCTION(sdio3),
2572 FUNCTION(sdio4),
2573 FUNCTION(sflash),
2574 FUNCTION(spdif),
2575 FUNCTION(spi1),
2576 FUNCTION(spi2),
2577 FUNCTION(spi2_alt),
2578 FUNCTION(spi3),
2579 FUNCTION(spi4),
2580 FUNCTION(trace),
2581 FUNCTION(twc),
2582 FUNCTION(uarta),
2583 FUNCTION(uartb),
2584 FUNCTION(uartc),
2585 FUNCTION(uartd),
2586 FUNCTION(uarte),
2587 FUNCTION(ulpi),
2588 FUNCTION(vi),
2589 FUNCTION(vi_sensor_clk),
2590 FUNCTION(xio),
2591};
2592
2593#define TRISTATE_REG_A 0x14
2594#define PIN_MUX_CTL_REG_A 0x80
2595#define PULLUPDOWN_REG_A 0xa0
2596#define PINGROUP_REG_A 0x868
2597
2598/* Pin group with mux control, and typically tri-state and pull-up/down too */
2599#define MUX_PG(pg_name, f0, f1, f2, f3, f_safe, \
2600 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
2601 { \
2602 .name = #pg_name, \
2603 .pins = pg_name##_pins, \
2604 .npins = ARRAY_SIZE(pg_name##_pins), \
2605 .funcs = { \
2606 TEGRA_MUX_ ## f0, \
2607 TEGRA_MUX_ ## f1, \
2608 TEGRA_MUX_ ## f2, \
2609 TEGRA_MUX_ ## f3, \
2610 }, \
2611 .func_safe = TEGRA_MUX_ ## f_safe, \
2612 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
2613 .mux_bank = 1, \
2614 .mux_bit = mux_b, \
2615 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2616 .pupd_bank = 2, \
2617 .pupd_bit = pupd_b, \
2618 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
2619 .tri_bank = 0, \
2620 .tri_bit = tri_b, \
2621 .einput_reg = -1, \
2622 .odrain_reg = -1, \
2623 .lock_reg = -1, \
2624 .ioreset_reg = -1, \
2625 .drv_reg = -1, \
2626 }
2627
2628/* Pin groups with only pull up and pull down control */
2629#define PULL_PG(pg_name, pupd_r, pupd_b) \
2630 { \
2631 .name = #pg_name, \
2632 .pins = pg_name##_pins, \
2633 .npins = ARRAY_SIZE(pg_name##_pins), \
2634 .mux_reg = -1, \
2635 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2636 .pupd_bank = 2, \
2637 .pupd_bit = pupd_b, \
2638 .tri_reg = -1, \
2639 .einput_reg = -1, \
2640 .odrain_reg = -1, \
2641 .lock_reg = -1, \
2642 .ioreset_reg = -1, \
2643 .drv_reg = -1, \
2644 }
2645
2646/* Pin groups for drive strength registers (configurable version) */
2647#define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2648 drvdn_b, drvup_b, \
2649 slwr_b, slwr_w, slwf_b, slwf_w) \
2650 { \
2651 .name = "drive_" #pg_name, \
2652 .pins = drive_##pg_name##_pins, \
2653 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2654 .mux_reg = -1, \
2655 .pupd_reg = -1, \
2656 .tri_reg = -1, \
2657 .einput_reg = -1, \
2658 .odrain_reg = -1, \
2659 .lock_reg = -1, \
2660 .ioreset_reg = -1, \
2661 .drv_reg = ((r) - PINGROUP_REG_A), \
2662 .drv_bank = 3, \
2663 .hsm_bit = hsm_b, \
2664 .schmitt_bit = schmitt_b, \
2665 .lpmd_bit = lpmd_b, \
2666 .drvdn_bit = drvdn_b, \
2667 .drvdn_width = 5, \
2668 .drvup_bit = drvup_b, \
2669 .drvup_width = 5, \
2670 .slwr_bit = slwr_b, \
2671 .slwr_width = slwr_w, \
2672 .slwf_bit = slwf_b, \
2673 .slwf_width = slwf_w, \
2674 }
2675
2676/* Pin groups for drive strength registers (simple version) */
2677#define DRV_PG(pg_name, r) \
2678 DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
2679
2680static const struct tegra_pingroup tegra20_groups[] = {
2681 /* name, f0, f1, f2, f3, f_safe, tri r/b, mux r/b, pupd r/b */
2682 MUX_PG(ata, IDE, NAND, GMI, RSVD4, IDE, 0x14, 0, 0x80, 24, 0xa0, 0),
2683 MUX_PG(atb, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xa0, 2),
2684 MUX_PG(atc, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xa0, 4),
2685 MUX_PG(atd, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xa0, 6),
2686 MUX_PG(ate, IDE, NAND, GMI, RSVD4, IDE, 0x18, 25, 0x80, 12, 0xa0, 8),
2687 MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xa8, 0),
2688 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xa8, 2),
2689 MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, RSVD2, 0x20, 14, 0x98, 20, 0xa4, 24),
2690 MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xac, 24),
2691 MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xa0, 10),
2692 MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, DAP2, 0x14, 8, 0x88, 22, 0xa0, 12),
2693 MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, DAP3, 0x14, 9, 0x88, 24, 0xa0, 14),
2694 MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, DAP4, 0x14, 10, 0x88, 26, 0xa0, 16),
2695 MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
2696 MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
2697 MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xa0, 20),
2698 MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, RSVD1, 0x14, 13, 0x84, 26, 0xa0, 22),
2699 MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, RSVD1, 0x14, 14, 0x84, 28, 0xa0, 24),
2700 MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xa0, 26),
2701 MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
2702 MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xb0, 20),
2703 MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xb0, 22),
2704 MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xb0, 24),
2705 MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xb0, 26),
2706 MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8c, 0, 0xa8, 24),
2707 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2708 MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x20, 11, 0x98, 28, 0xa4, 6),
2709 MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, PCIE, 0x14, 17, 0x8c, 2, 0xa0, 30),
2710 MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, HDMI, 0x1c, 23, 0x84, 4, -1, -1),
2711 MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
2712 MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xa8, 22),
2713 MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xa8, 20),
2714 MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xa4, 8),
2715 MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xa4, 10),
2716 MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xa4, 12),
2717 MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xa4, 14),
2718 MUX_PG(kbce, KBC, NAND, OWR, RSVD4, KBC, 0x14, 26, 0x80, 28, 0xb0, 2),
2719 MUX_PG(kbcf, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xb0, 0),
2720 MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
2721 MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
2722 MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
2723 MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
2724 MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
2725 MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
2726 MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
2727 MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
2728 MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
2729 MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
2730 MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
2731 MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
2732 MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
2733 MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
2734 MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
2735 MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
2736 MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
2737 MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
2738 MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
2739 MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
2740 MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
2741 MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
2742 MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
2743 MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
2744 MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
2745 MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
2746 MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, RSVD3, 0x1c, 25, 0x90, 28, -1, -1),
2747 MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
2748 MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, -1, -1),
2749 MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
2750 MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, -1, -1),
2751 MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
2752 MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 28, 0x90, 20, -1, -1),
2753 MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 29, 0x90, 16, -1, -1),
2754 MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, -1, -1),
2755 MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, DISPLAYA, 0x20, 2, 0x90, 6, -1, -1),
2756 MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, -1, -1),
2757 MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
2758 MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
2759 MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
2760 MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, OWR, 0x14, 31, 0x84, 8, 0xb0, 30),
2761 MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
2762 MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
2763 MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
2764 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8c, 10, -1, -1),
2765 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8c, 12, 0xac, 28),
2766 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8c, 14, 0xac, 30),
2767 MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xb0, 18),
2768 MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xa4, 22),
2769 MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xa4, 26),
2770 MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xa4, 28),
2771 MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xa4, 30),
2772 MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 8, 0x8c, 8, 0xa4, 16),
2773 MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 9, 0x8c, 6, 0xa4, 18),
2774 MUX_PG(spia, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
2775 MUX_PG(spib, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
2776 MUX_PG(spic, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
2777 MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
2778 MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
2779 MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
2780 MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 16, 0x8c, 18, 0xa8, 16),
2781 MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 17, 0x8c, 16, 0xa8, 18),
2782 MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xac, 0),
2783 MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xac, 2),
2784 MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
2785 MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xac, 6),
2786 MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
2787 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
2788 MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xb0, 16),
2789 /* pg_name, pupd_r/b */
2790 PULL_PG(ck32, 0xb0, 14),
2791 PULL_PG(ddrc, 0xac, 26),
2792 PULL_PG(pmca, 0xb0, 4),
2793 PULL_PG(pmcb, 0xb0, 6),
2794 PULL_PG(pmcc, 0xb0, 8),
2795 PULL_PG(pmcd, 0xb0, 10),
2796 PULL_PG(pmce, 0xb0, 12),
2797 PULL_PG(xm2c, 0xa8, 30),
2798 PULL_PG(xm2d, 0xa8, 28),
2799 PULL_PG(ls, 0xac, 20),
2800 PULL_PG(lc, 0xac, 22),
2801 PULL_PG(ld17_0, 0xac, 12),
2802 PULL_PG(ld19_18, 0xac, 14),
2803 PULL_PG(ld21_20, 0xac, 16),
2804 PULL_PG(ld23_22, 0xac, 18),
2805 /* pg_name, r */
2806 DRV_PG(ao1, 0x868),
2807 DRV_PG(ao2, 0x86c),
2808 DRV_PG(at1, 0x870),
2809 DRV_PG(at2, 0x874),
2810 DRV_PG(cdev1, 0x878),
2811 DRV_PG(cdev2, 0x87c),
2812 DRV_PG(csus, 0x880),
2813 DRV_PG(dap1, 0x884),
2814 DRV_PG(dap2, 0x888),
2815 DRV_PG(dap3, 0x88c),
2816 DRV_PG(dap4, 0x890),
2817 DRV_PG(dbg, 0x894),
2818 DRV_PG(lcd1, 0x898),
2819 DRV_PG(lcd2, 0x89c),
2820 DRV_PG(sdmmc2, 0x8a0),
2821 DRV_PG(sdmmc3, 0x8a4),
2822 DRV_PG(spi, 0x8a8),
2823 DRV_PG(uaa, 0x8ac),
2824 DRV_PG(uab, 0x8b0),
2825 DRV_PG(uart2, 0x8b4),
2826 DRV_PG(uart3, 0x8b8),
2827 DRV_PG(vi1, 0x8bc),
2828 DRV_PG(vi2, 0x8c0),
2829 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
2830 DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
2831 DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
2832 DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
2833 DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
2834 /* pg_name, r */
2835 DRV_PG(sdio1, 0x8e0),
2836 DRV_PG(crt, 0x8ec),
2837 DRV_PG(ddc, 0x8f0),
2838 DRV_PG(gma, 0x8f4),
2839 DRV_PG(gmb, 0x8f8),
2840 DRV_PG(gmc, 0x8fc),
2841 DRV_PG(gmd, 0x900),
2842 DRV_PG(gme, 0x904),
2843 DRV_PG(owr, 0x908),
2844 DRV_PG(uda, 0x90c),
2845};
2846
2847static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2848 .ngpios = NUM_GPIOS,
2849 .pins = tegra20_pins,
2850 .npins = ARRAY_SIZE(tegra20_pins),
2851 .functions = tegra20_functions,
2852 .nfunctions = ARRAY_SIZE(tegra20_functions),
2853 .groups = tegra20_groups,
2854 .ngroups = ARRAY_SIZE(tegra20_groups),
2855};
2856
2857void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
2858{
2859 *soc = &tegra20_pinctrl;
2860}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 17:14:56 -0500