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-rw-r--r--drivers/pcmcia/m8xx_pcmcia.c1290
1 files changed, 1290 insertions, 0 deletions
diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c
new file mode 100644
index 000000000000..f8bed87cf2f1
--- /dev/null
+++ b/drivers/pcmcia/m8xx_pcmcia.c
@@ -0,0 +1,1290 @@
1/*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
12 *
13 * "The ExCA standard specifies that socket controllers should provide
14 * two IO and five memory windows per socket, which can be independently
15 * configured and positioned in the host address space and mapped to
16 * arbitrary segments of card address space. " - David A Hinds. 1999
17 *
18 * This controller does _not_ meet the ExCA standard.
19 *
20 * m8xx pcmcia controller brief info:
21 * + 8 windows (attrib, mem, i/o)
22 * + up to two slots (SLOT_A and SLOT_B)
23 * + inputpins, outputpins, event and mask registers.
24 * - no offset register. sigh.
25 *
26 * Because of the lacking offset register we must map the whole card.
27 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
28 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
29 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
30 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
31 * They are maximum 64KByte each...
32 */
33
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/types.h>
37#include <linux/fcntl.h>
38#include <linux/string.h>
39
40#include <asm/io.h>
41#include <asm/bitops.h>
42#include <asm/segment.h>
43#include <asm/system.h>
44
45#include <linux/kernel.h>
46#include <linux/errno.h>
47#include <linux/sched.h>
48#include <linux/slab.h>
49#include <linux/timer.h>
50#include <linux/ioport.h>
51#include <linux/delay.h>
52#include <linux/interrupt.h>
53
54#include <asm/mpc8xx.h>
55#include <asm/8xx_immap.h>
56#include <asm/irq.h>
57
58#include <pcmcia/version.h>
59#include <pcmcia/cs_types.h>
60#include <pcmcia/cs.h>
61#include <pcmcia/ss.h>
62
63#ifdef PCMCIA_DEBUG
64static int pc_debug = PCMCIA_DEBUG;
65module_param(pc_debug, int, 0);
66#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
67#else
68#define dprintk(args...)
69#endif
70
71#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
72#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
73
74static const char *version = "Version 0.06, Aug 2005";
75MODULE_LICENSE("Dual MPL/GPL");
76
77#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
78
79/* The RPX series use SLOT_B */
80#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
81#define CONFIG_PCMCIA_SLOT_B
82#define CONFIG_BD_IS_MHZ
83#endif
84
85/* The ADS board use SLOT_A */
86#ifdef CONFIG_ADS
87#define CONFIG_PCMCIA_SLOT_A
88#define CONFIG_BD_IS_MHZ
89#endif
90
91/* The FADS series are a mess */
92#ifdef CONFIG_FADS
93#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
94#define CONFIG_PCMCIA_SLOT_A
95#else
96#define CONFIG_PCMCIA_SLOT_B
97#endif
98#endif
99
100/* Cyclades ACS uses both slots */
101#ifdef CONFIG_PRxK
102#define CONFIG_PCMCIA_SLOT_A
103#define CONFIG_PCMCIA_SLOT_B
104#endif
105
106#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
107
108#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
109
110#define PCMCIA_SOCKETS_NO 2
111/* We have only 8 windows, dualsocket support will be limited. */
112#define PCMCIA_MEM_WIN_NO 2
113#define PCMCIA_IO_WIN_NO 2
114#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
115
116#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
117
118#define PCMCIA_SOCKETS_NO 1
119/* full support for one slot */
120#define PCMCIA_MEM_WIN_NO 5
121#define PCMCIA_IO_WIN_NO 2
122
123/* define _slot_ to be able to optimize macros */
124
125#ifdef CONFIG_PCMCIA_SLOT_A
126#define _slot_ 0
127#define PCMCIA_SLOT_MSG "SLOT_A"
128#else
129#define _slot_ 1
130#define PCMCIA_SLOT_MSG "SLOT_B"
131#endif
132
133#else
134#error m8xx_pcmcia: Bad configuration!
135#endif
136
137/* ------------------------------------------------------------------------- */
138
139#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
140#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
141#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
142
143#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
144
145/* ------------------------------------------------------------------------- */
146
147/* 2.4.x and newer has this always in HZ */
148#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
149
150static int pcmcia_schlvl = PCMCIA_SCHLVL;
151
152static spinlock_t events_lock = SPIN_LOCK_UNLOCKED;
153
154
155#define PCMCIA_SOCKET_KEY_5V 1
156#define PCMCIA_SOCKET_KEY_LV 2
157
158/* look up table for pgcrx registers */
159static u32 *m8xx_pgcrx[2] = {
160 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
161 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
162};
163
164/*
165 * This structure is used to address each window in the PCMCIA controller.
166 *
167 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
168 * after pcmcia_win[n]...
169 */
170
171struct pcmcia_win {
172 u32 br;
173 u32 or;
174};
175
176/*
177 * For some reason the hardware guys decided to make both slots share
178 * some registers.
179 *
180 * Could someone invent object oriented hardware ?
181 *
182 * The macros are used to get the right bit from the registers.
183 * SLOT_A : slot = 0
184 * SLOT_B : slot = 1
185 */
186
187#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
188#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
189#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
190#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
191
192#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
193#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
194#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
195#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
196#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
197#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
198#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
199#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
200#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
201#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
202#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
203
204#define M8XX_PCMCIA_POR_VALID 0x00000001
205#define M8XX_PCMCIA_POR_WRPROT 0x00000002
206#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
207#define M8XX_PCMCIA_POR_IO 0x00000018
208#define M8XX_PCMCIA_POR_16BIT 0x00000040
209
210#define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
211
212#define M8XX_PGCRX_CXOE 0x00000080
213#define M8XX_PGCRX_CXRESET 0x00000040
214
215/* we keep one lookup table per socket to check flags */
216
217#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
218
219struct event_table {
220 u32 regbit;
221 u32 eventbit;
222};
223
224struct socket_info {
225 void (*handler)(void *info, u32 events);
226 void *info;
227
228 u32 slot;
229
230 socket_state_t state;
231 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
232 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
233 struct event_table events[PCMCIA_EVENTS_MAX];
234 struct pcmcia_socket socket;
235};
236
237static struct socket_info socket[PCMCIA_SOCKETS_NO];
238
239/*
240 * Search this table to see if the windowsize is
241 * supported...
242 */
243
244#define M8XX_SIZES_NO 32
245
246static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
247{
248 0x00000001, 0x00000002, 0x00000008, 0x00000004,
249 0x00000080, 0x00000040, 0x00000010, 0x00000020,
250 0x00008000, 0x00004000, 0x00001000, 0x00002000,
251 0x00000100, 0x00000200, 0x00000800, 0x00000400,
252
253 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
254 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
255 0x00010000, 0x00020000, 0x00080000, 0x00040000,
256 0x00800000, 0x00400000, 0x00100000, 0x00200000
257};
258
259/* ------------------------------------------------------------------------- */
260
261static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs);
262
263#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
264
265/* ------------------------------------------------------------------------- */
266/* board specific stuff: */
267/* voltage_set(), hardware_enable() and hardware_disable() */
268/* ------------------------------------------------------------------------- */
269/* RPX Boards from Embedded Planet */
270
271#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
272
273/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
274 * SYPCR is write once only, therefore must the slowest memory be faster
275 * than the bus monitor or we will get a machine check due to the bus timeout.
276 */
277
278#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
279
280#undef PCMCIA_BMT_LIMIT
281#define PCMCIA_BMT_LIMIT (6*8)
282
283static int voltage_set(int slot, int vcc, int vpp)
284{
285 u32 reg = 0;
286
287 switch(vcc) {
288 case 0: break;
289 case 33:
290 reg |= BCSR1_PCVCTL4;
291 break;
292 case 50:
293 reg |= BCSR1_PCVCTL5;
294 break;
295 default:
296 return 1;
297 }
298
299 switch(vpp) {
300 case 0: break;
301 case 33:
302 case 50:
303 if(vcc == vpp)
304 reg |= BCSR1_PCVCTL6;
305 else
306 return 1;
307 break;
308 case 120:
309 reg |= BCSR1_PCVCTL7;
310 default:
311 return 1;
312 }
313
314 if(!((vcc == 50) || (vcc == 0)))
315 return 1;
316
317 /* first, turn off all power */
318
319 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
320
321 /* enable new powersettings */
322
323 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
324
325 return 0;
326}
327
328#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
329#define hardware_enable(_slot_) /* No hardware to enable */
330#define hardware_disable(_slot_) /* No hardware to disable */
331
332#endif /* CONFIG_RPXCLASSIC */
333
334/* FADS Boards from Motorola */
335
336#if defined(CONFIG_FADS)
337
338#define PCMCIA_BOARD_MSG "FADS"
339
340static int voltage_set(int slot, int vcc, int vpp)
341{
342 u32 reg = 0;
343
344 switch(vcc) {
345 case 0:
346 break;
347 case 33:
348 reg |= BCSR1_PCCVCC0;
349 break;
350 case 50:
351 reg |= BCSR1_PCCVCC1;
352 break;
353 default:
354 return 1;
355 }
356
357 switch(vpp) {
358 case 0:
359 break;
360 case 33:
361 case 50:
362 if(vcc == vpp)
363 reg |= BCSR1_PCCVPP1;
364 else
365 return 1;
366 break;
367 case 120:
368 if ((vcc == 33) || (vcc == 50))
369 reg |= BCSR1_PCCVPP0;
370 else
371 return 1;
372 default:
373 return 1;
374 }
375
376 /* first, turn off all power */
377 out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
378
379 /* enable new powersettings */
380 out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg);
381
382 return 0;
383}
384
385#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
386
387static void hardware_enable(int slot)
388{
389 out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN);
390}
391
392static void hardware_disable(int slot)
393{
394 out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN);
395}
396
397#endif
398
399/* ------------------------------------------------------------------------- */
400/* Motorola MBX860 */
401
402#if defined(CONFIG_MBX)
403
404#define PCMCIA_BOARD_MSG "MBX"
405
406static int voltage_set(int slot, int vcc, int vpp)
407{
408 u8 reg = 0;
409
410 switch(vcc) {
411 case 0:
412 break;
413 case 33:
414 reg |= CSR2_VCC_33;
415 break;
416 case 50:
417 reg |= CSR2_VCC_50;
418 break;
419 default:
420 return 1;
421 }
422
423 switch(vpp) {
424 case 0:
425 break;
426 case 33:
427 case 50:
428 if(vcc == vpp)
429 reg |= CSR2_VPP_VCC;
430 else
431 return 1;
432 break;
433 case 120:
434 if ((vcc == 33) || (vcc == 50))
435 reg |= CSR2_VPP_12;
436 else
437 return 1;
438 default:
439 return 1;
440 }
441
442 /* first, turn off all power */
443 out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
444
445 /* enable new powersettings */
446 out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg);
447
448 return 0;
449}
450
451#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
452#define hardware_enable(_slot_) /* No hardware to enable */
453#define hardware_disable(_slot_) /* No hardware to disable */
454
455#endif /* CONFIG_MBX */
456
457#if defined(CONFIG_PRxK)
458#include <asm/cpld.h>
459extern volatile fpga_pc_regs *fpga_pc;
460
461#define PCMCIA_BOARD_MSG "MPC855T"
462
463static int voltage_set(int slot, int vcc, int vpp)
464{
465 u8 reg = 0;
466 u8 regread;
467 cpld_regs *ccpld = get_cpld();
468
469 switch(vcc) {
470 case 0:
471 break;
472 case 33:
473 reg |= PCMCIA_VCC_33;
474 break;
475 case 50:
476 reg |= PCMCIA_VCC_50;
477 break;
478 default:
479 return 1;
480 }
481
482 switch(vpp) {
483 case 0:
484 break;
485 case 33:
486 case 50:
487 if(vcc == vpp)
488 reg |= PCMCIA_VPP_VCC;
489 else
490 return 1;
491 break;
492 case 120:
493 if ((vcc == 33) || (vcc == 50))
494 reg |= PCMCIA_VPP_12;
495 else
496 return 1;
497 default:
498 return 1;
499 }
500
501 reg = reg >> (slot << 2);
502 regread = in_8(&ccpld->fpga_pc_ctl);
503 if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
504 /* enable new powersettings */
505 regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
506 out_8(&ccpld->fpga_pc_ctl, reg | regread);
507 msleep(100);
508 }
509
510 return 0;
511}
512
513#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
514#define hardware_enable(_slot_) /* No hardware to enable */
515#define hardware_disable(_slot_) /* No hardware to disable */
516
517#endif /* CONFIG_PRxK */
518
519static void m8xx_shutdown(void)
520{
521 u32 m, i;
522 struct pcmcia_win *w;
523
524 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
525 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
526
527 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
528 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
529
530 /* turn off interrupt and disable CxOE */
531 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
532
533 /* turn off memory windows */
534 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
535 out_be32(&w->or, 0); /* set to not valid */
536 w++;
537 }
538
539 /* turn off voltage */
540 voltage_set(i, 0, 0);
541
542 /* disable external hardware */
543 hardware_disable(i);
544 }
545
546 free_irq(pcmcia_schlvl, NULL);
547}
548
549/* copied from tcic.c */
550
551static int m8xx_drv_suspend(struct device *dev, pm_message_t state, u32 level)
552{
553 int ret = 0;
554 if (level == SUSPEND_SAVE_STATE)
555 ret = pcmcia_socket_dev_suspend(dev, state);
556 return ret;
557}
558
559static int m8xx_drv_resume(struct device *dev, u32 level)
560{
561 int ret = 0;
562 if (level == RESUME_RESTORE_STATE)
563 ret = pcmcia_socket_dev_resume(dev);
564 return ret;
565}
566
567static struct device_driver m8xx_driver = {
568 .name = "m8xx-pcmcia",
569 .bus = &platform_bus_type,
570 .suspend = m8xx_drv_suspend,
571 .resume = m8xx_drv_resume,
572};
573
574static struct platform_device m8xx_device = {
575 .name = "m8xx-pcmcia",
576 .id = 0,
577};
578
579static u32 pending_events[PCMCIA_SOCKETS_NO];
580static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED;
581
582static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs)
583{
584 struct socket_info *s;
585 struct event_table *e;
586 unsigned int i, events, pscr, pipr, per;
587
588 dprintk("Interrupt!\n");
589 /* get interrupt sources */
590
591 pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
592 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
593 per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
594
595 for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
596 s = &socket[i];
597 e = &s->events[0];
598 events = 0;
599
600 while(e->regbit) {
601 if(pscr & e->regbit)
602 events |= e->eventbit;
603
604 e++;
605 }
606
607 /*
608 * report only if both card detect signals are the same
609 * not too nice done,
610 * we depend on that CD2 is the bit to the left of CD1...
611 */
612 if(events & SS_DETECT)
613 if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
614 (pipr & M8XX_PCMCIA_CD1(i)))
615 {
616 events &= ~SS_DETECT;
617 }
618
619#ifdef PCMCIA_GLITCHY_CD
620 /*
621 * I've experienced CD problems with my ADS board.
622 * We make an extra check to see if there was a
623 * real change of Card detection.
624 */
625
626 if((events & SS_DETECT) &&
627 ((pipr &
628 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
629 (s->state.Vcc | s->state.Vpp)) {
630 events &= ~SS_DETECT;
631 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
632 (pipr & (M8XX_PCMCIA_CD2(i)
633 | M8XX_PCMCIA_CD1(i))));*/
634 }
635#endif
636
637 /* call the handler */
638
639 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
640 "pipr = 0x%08x\n",
641 i, events, pscr, pipr);
642
643 if(events) {
644 spin_lock(&pending_event_lock);
645 pending_events[i] |= events;
646 spin_unlock(&pending_event_lock);
647 /*
648 * Turn off RDY_L bits in the PER mask on
649 * CD interrupt receival.
650 *
651 * They can generate bad interrupts on the
652 * ACS4,8,16,32. - marcelo
653 */
654 per &= ~M8XX_PCMCIA_RDY_L(0);
655 per &= ~M8XX_PCMCIA_RDY_L(1);
656
657 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
658
659 if (events)
660 pcmcia_parse_events(&socket[i].socket, events);
661 }
662 }
663
664 /* clear the interrupt sources */
665 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
666
667 dprintk("Interrupt done.\n");
668
669 return IRQ_HANDLED;
670}
671
672static u32 m8xx_get_graycode(u32 size)
673{
674 u32 k;
675
676 for(k = 0; k < M8XX_SIZES_NO; k++)
677 if(m8xx_size_to_gray[k] == size)
678 break;
679
680 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
681 k = -1;
682
683 return k;
684}
685
686static u32 m8xx_get_speed(u32 ns, u32 is_io)
687{
688 u32 reg, clocks, psst, psl, psht;
689
690 if(!ns) {
691
692 /*
693 * We get called with IO maps setup to 0ns
694 * if not specified by the user.
695 * They should be 255ns.
696 */
697
698 if(is_io)
699 ns = 255;
700 else
701 ns = 100; /* fast memory if 0 */
702 }
703
704 /*
705 * In PSST, PSL, PSHT fields we tell the controller
706 * timing parameters in CLKOUT clock cycles.
707 * CLKOUT is the same as GCLK2_50.
708 */
709
710/* how we want to adjust the timing - in percent */
711
712#define ADJ 180 /* 80 % longer accesstime - to be sure */
713
714 clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
715 clocks = (clocks * ADJ) / (100*1000);
716 if(clocks >= PCMCIA_BMT_LIMIT) {
717 printk( "Max access time limit reached\n");
718 clocks = PCMCIA_BMT_LIMIT-1;
719 }
720
721 psst = clocks / 7; /* setup time */
722 psht = clocks / 7; /* hold time */
723 psl = (clocks * 5) / 7; /* strobe length */
724
725 psst += clocks - (psst + psht + psl);
726
727 reg = psst << 12;
728 reg |= psl << 7;
729 reg |= psht << 16;
730
731 return reg;
732}
733
734static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
735{
736 int lsock = container_of(sock, struct socket_info, socket)->slot;
737 struct socket_info *s = &socket[lsock];
738 unsigned int pipr, reg;
739
740 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
741
742 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
743 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
744 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
745
746 if (s->state.flags & SS_IOCARD)
747 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
748 else {
749 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
750 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
751 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
752 }
753
754 if (s->state.Vcc | s->state.Vpp)
755 *value |= SS_POWERON;
756
757 /*
758 * Voltage detection:
759 * This driver only supports 16-Bit pc-cards.
760 * Cardbus is not handled here.
761 *
762 * To determine what voltage to use we must read the VS1 and VS2 pin.
763 * Depending on what socket type is present,
764 * different combinations mean different things.
765 *
766 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
767 *
768 * 5V 5V, LV* NC NC 5V only 5V (if available)
769 *
770 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
771 *
772 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
773 *
774 * LV* 5V - - shall not fit into socket
775 *
776 * LV* LV* GND NC 3.3V only 3.3V
777 *
778 * LV* LV* NC GND x.xV x.xV (if avail.)
779 *
780 * LV* LV* GND GND 3.3 or x.xV as low as possible
781 *
782 * *LV means Low Voltage
783 *
784 *
785 * That gives us the following table:
786 *
787 * Socket VS1 VS2 Voltage
788 *
789 * 5V NC NC 5V
790 * 5V NC GND none (should not be possible)
791 * 5V GND NC >= 3.3V
792 * 5V GND GND >= x.xV
793 *
794 * LV NC NC 5V (if available)
795 * LV NC GND x.xV (if available)
796 * LV GND NC 3.3V
797 * LV GND GND >= x.xV
798 *
799 * So, how do I determine if I have a 5V or a LV
800 * socket on my board? Look at the socket!
801 *
802 *
803 * Socket with 5V key:
804 * ++--------------------------------------------+
805 * || |
806 * || ||
807 * || ||
808 * | |
809 * +---------------------------------------------+
810 *
811 * Socket with LV key:
812 * ++--------------------------------------------+
813 * || |
814 * | ||
815 * | ||
816 * | |
817 * +---------------------------------------------+
818 *
819 *
820 * With other words - LV only cards does not fit
821 * into the 5V socket!
822 */
823
824 /* read out VS1 and VS2 */
825
826 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
827 >> M8XX_PCMCIA_VS_SHIFT(lsock);
828
829 if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
830 switch(reg) {
831 case 1:
832 *value |= SS_3VCARD;
833 break; /* GND, NC - 3.3V only */
834 case 2:
835 *value |= SS_XVCARD;
836 break; /* NC. GND - x.xV only */
837 };
838 }
839
840 dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
841 return 0;
842}
843
844static int m8xx_get_socket(struct pcmcia_socket *sock, socket_state_t *state)
845{
846 int lsock = container_of(sock, struct socket_info, socket)->slot;
847 *state = socket[lsock].state; /* copy the whole structure */
848
849 dprintk("GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
850 "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags,
851 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
852 return 0;
853}
854
855static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
856{
857 int lsock = container_of(sock, struct socket_info, socket)->slot;
858 struct socket_info *s = &socket[lsock];
859 struct event_table *e;
860 unsigned int reg;
861 unsigned long flags;
862
863 dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
864 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
865 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
866
867 /* First, set voltage - bail out if invalid */
868 if(voltage_set(lsock, state->Vcc, state->Vpp))
869 return -EINVAL;
870
871 /* Take care of reset... */
872 if(state->flags & SS_RESET)
873 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
874 else
875 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
876
877 /* ... and output enable. */
878
879 /* The CxOE signal is connected to a 74541 on the ADS.
880 I guess most other boards used the ADS as a reference.
881 I tried to control the CxOE signal with SS_OUTPUT_ENA,
882 but the reset signal seems connected via the 541.
883 If the CxOE is left high are some signals tristated and
884 no pullups are present -> the cards act wierd.
885 So right now the buffers are enabled if the power is on. */
886
887 if(state->Vcc || state->Vpp)
888 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
889 else
890 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
891
892 /*
893 * We'd better turn off interrupts before
894 * we mess with the events-table..
895 */
896
897 spin_lock_irqsave(&events_lock, flags);
898
899 /*
900 * Play around with the interrupt mask to be able to
901 * give the events the generic pcmcia driver wants us to.
902 */
903
904 e = &s->events[0];
905 reg = 0;
906
907 if(state->csc_mask & SS_DETECT) {
908 e->eventbit = SS_DETECT;
909 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
910 | M8XX_PCMCIA_CD1(lsock));
911 e++;
912 }
913 if(state->flags & SS_IOCARD) {
914 /*
915 * I/O card
916 */
917 if(state->csc_mask & SS_STSCHG) {
918 e->eventbit = SS_STSCHG;
919 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
920 e++;
921 }
922 /*
923 * If io_irq is non-zero we should enable irq.
924 */
925 if(state->io_irq) {
926 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
927 /*
928 * Strange thing here:
929 * The manual does not tell us which interrupt
930 * the sources generate.
931 * Anyhow, I found out that RDY_L generates IREQLVL.
932 *
933 * We use level triggerd interrupts, and they don't
934 * have to be cleared in PSCR in the interrupt handler.
935 */
936 reg |= M8XX_PCMCIA_RDY_L(lsock);
937 }
938 else
939 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
940 }
941 else {
942 /*
943 * Memory card
944 */
945 if(state->csc_mask & SS_BATDEAD) {
946 e->eventbit = SS_BATDEAD;
947 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
948 e++;
949 }
950 if(state->csc_mask & SS_BATWARN) {
951 e->eventbit = SS_BATWARN;
952 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
953 e++;
954 }
955 /* What should I trigger on - low/high,raise,fall? */
956 if(state->csc_mask & SS_READY) {
957 e->eventbit = SS_READY;
958 reg |= e->regbit = 0; //??
959 e++;
960 }
961 }
962
963 e->regbit = 0; /* terminate list */
964
965 /*
966 * Clear the status changed .
967 * Port A and Port B share the same port.
968 * Writing ones will clear the bits.
969 */
970
971 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
972
973 /*
974 * Write the mask.
975 * Port A and Port B share the same port.
976 * Need for read-modify-write.
977 * Ones will enable the interrupt.
978 */
979
980 /*
981 reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
982 & M8XX_PCMCIA_MASK(lsock);
983 */
984
985 reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
986 (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
987
988 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
989
990 spin_unlock_irqrestore(&events_lock, flags);
991
992 /* copy the struct and modify the copy */
993
994 s->state = *state;
995
996 return 0;
997}
998
999static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
1000{
1001 int lsock = container_of(sock, struct socket_info, socket)->slot;
1002
1003 struct socket_info *s = &socket[lsock];
1004 struct pcmcia_win *w;
1005 unsigned int reg, winnr;
1006
1007#define M8XX_SIZE (io->stop - io->start + 1)
1008#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
1009
1010 dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
1011 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
1012 io->speed, io->start, io->stop);
1013
1014 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
1015 || (io->stop > 0xffff) || (io->stop < io->start))
1016 return -EINVAL;
1017
1018 if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
1019 return -EINVAL;
1020
1021 if(io->flags & MAP_ACTIVE) {
1022
1023 dprintk( "io->flags & MAP_ACTIVE\n");
1024
1025 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1026 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1027
1028 /* setup registers */
1029
1030 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1031 w += winnr;
1032
1033 out_be32(&w->or, 0); /* turn off window first */
1034 out_be32(&w->br, M8XX_BASE);
1035
1036 reg <<= 27;
1037 reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
1038
1039 reg |= m8xx_get_speed(io->speed, 1);
1040
1041 if(io->flags & MAP_WRPROT)
1042 reg |= M8XX_PCMCIA_POR_WRPROT;
1043
1044 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/
1045 if(io->flags & MAP_16BIT)
1046 reg |= M8XX_PCMCIA_POR_16BIT;
1047
1048 if(io->flags & MAP_ACTIVE)
1049 reg |= M8XX_PCMCIA_POR_VALID;
1050
1051 out_be32(&w->or, reg);
1052
1053 dprintk("Socket %u: Mapped io window %u at %#8.8x, "
1054 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1055 } else {
1056 /* shutdown IO window */
1057 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1058 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1059
1060 /* setup registers */
1061
1062 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1063 w += winnr;
1064
1065 out_be32(&w->or, 0); /* turn off window */
1066 out_be32(&w->br, 0); /* turn off base address */
1067
1068 dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
1069 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1070 }
1071
1072 /* copy the struct and modify the copy */
1073 s->io_win[io->map] = *io;
1074 s->io_win[io->map].flags &= (MAP_WRPROT
1075 | MAP_16BIT
1076 | MAP_ACTIVE);
1077 dprintk("SetIOMap exit\n");
1078
1079 return 0;
1080}
1081
1082static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
1083{
1084 int lsock = container_of(sock, struct socket_info, socket)->slot;
1085 struct socket_info *s = &socket[lsock];
1086 struct pcmcia_win *w;
1087 struct pccard_mem_map *old;
1088 unsigned int reg, winnr;
1089
1090 dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
1091 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1092 mem->speed, mem->static_start, mem->card_start);
1093
1094 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1095// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1096 || (mem->card_start >= 0x04000000)
1097 || (mem->static_start & 0xfff) /* 4KByte resolution */
1098 || (mem->card_start & 0xfff))
1099 return -EINVAL;
1100
1101 if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1102 printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1103 return -EINVAL;
1104 }
1105 reg <<= 27;
1106
1107 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1108
1109 /* Setup the window in the pcmcia controller */
1110
1111 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1112 w += winnr;
1113
1114 reg |= lsock << 2;
1115
1116 reg |= m8xx_get_speed(mem->speed, 0);
1117
1118 if(mem->flags & MAP_ATTRIB)
1119 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1120
1121 if(mem->flags & MAP_WRPROT)
1122 reg |= M8XX_PCMCIA_POR_WRPROT;
1123
1124 if(mem->flags & MAP_16BIT)
1125 reg |= M8XX_PCMCIA_POR_16BIT;
1126
1127 if(mem->flags & MAP_ACTIVE)
1128 reg |= M8XX_PCMCIA_POR_VALID;
1129
1130 out_be32(&w->or, reg);
1131
1132 dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
1133 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1134
1135 if(mem->flags & MAP_ACTIVE) {
1136 /* get the new base address */
1137 mem->static_start = PCMCIA_MEM_WIN_BASE +
1138 (PCMCIA_MEM_WIN_SIZE * winnr)
1139 + mem->card_start;
1140 }
1141
1142 dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1143 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1144 mem->speed, mem->static_start, mem->card_start);
1145
1146 /* copy the struct and modify the copy */
1147
1148 old = &s->mem_win[mem->map];
1149
1150 *old = *mem;
1151 old->flags &= (MAP_ATTRIB
1152 | MAP_WRPROT
1153 | MAP_16BIT
1154 | MAP_ACTIVE);
1155
1156 return 0;
1157}
1158
1159static int m8xx_sock_init(struct pcmcia_socket *sock)
1160{
1161 int i;
1162 pccard_io_map io = { 0, 0, 0, 0, 1 };
1163 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1164
1165 dprintk( "sock_init(%d)\n", s);
1166
1167 m8xx_set_socket(sock, &dead_socket);
1168 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1169 io.map = i;
1170 m8xx_set_io_map(sock, &io);
1171 }
1172 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1173 mem.map = i;
1174 m8xx_set_mem_map(sock, &mem);
1175 }
1176
1177 return 0;
1178
1179}
1180
1181static int m8xx_suspend(struct pcmcia_socket *sock)
1182{
1183 return m8xx_set_socket(sock, &dead_socket);
1184}
1185
1186static struct pccard_operations m8xx_services = {
1187 .init = m8xx_sock_init,
1188 .suspend = m8xx_suspend,
1189 .get_status = m8xx_get_status,
1190 .get_socket = m8xx_get_socket,
1191 .set_socket = m8xx_set_socket,
1192 .set_io_map = m8xx_set_io_map,
1193 .set_mem_map = m8xx_set_mem_map,
1194};
1195
1196static int __init m8xx_init(void)
1197{
1198 struct pcmcia_win *w;
1199 unsigned int i,m;
1200
1201 pcmcia_info("%s\n", version);
1202
1203 if (driver_register(&m8xx_driver))
1204 return -1;
1205
1206 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1207 " with IRQ %u.\n", pcmcia_schlvl);
1208
1209 /* Configure Status change interrupt */
1210
1211 if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
1212 "m8xx_pcmcia", NULL)) {
1213 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1214 pcmcia_schlvl);
1215 return -1;
1216 }
1217
1218 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
1219
1220 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
1221 M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
1222
1223 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
1224 in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
1225 ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
1226
1227/* connect interrupt and disable CxOE */
1228
1229 out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
1230 out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
1231
1232/* intialize the fixed memory windows */
1233
1234 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
1235 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1236 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1237 (PCMCIA_MEM_WIN_SIZE
1238 * (m + i * PCMCIA_MEM_WIN_NO)));
1239
1240 out_be32(&w->or, 0); /* set to not valid */
1241
1242 w++;
1243 }
1244 }
1245
1246/* turn off voltage */
1247 voltage_set(0, 0, 0);
1248 voltage_set(1, 0, 0);
1249
1250/* Enable external hardware */
1251 hardware_enable(0);
1252 hardware_enable(1);
1253
1254 platform_device_register(&m8xx_device);
1255
1256 for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
1257 socket[i].slot = i;
1258 socket[i].socket.owner = THIS_MODULE;
1259 socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1260 socket[i].socket.irq_mask = 0x000;
1261 socket[i].socket.map_size = 0x1000;
1262 socket[i].socket.io_offset = 0;
1263 socket[i].socket.pci_irq = i ? 7 : 9;
1264 socket[i].socket.ops = &m8xx_services;
1265 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
1266 socket[i].socket.cb_dev = NULL;
1267 socket[i].socket.dev.dev = &m8xx_device.dev;
1268 }
1269
1270 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1271 pcmcia_register_socket(&socket[i].socket);
1272
1273 return 0;
1274}
1275
1276static void __exit m8xx_exit(void)
1277{
1278 int i;
1279
1280 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1281 pcmcia_unregister_socket(&socket[i].socket);
1282
1283 m8xx_shutdown();
1284
1285 platform_device_unregister(&m8xx_device);
1286 driver_unregister(&m8xx_driver);
1287}
1288
1289module_init(m8xx_init);
1290module_exit(m8xx_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 18:38:54 -0500