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path: root/drivers/pcmcia/au1000_generic.h
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Diffstat (limited to 'drivers/pcmcia/au1000_generic.h')
-rw-r--r--drivers/pcmcia/au1000_generic.h27
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h
index 1e467bb54077..a53ef5902518 100644
--- a/drivers/pcmcia/au1000_generic.h
+++ b/drivers/pcmcia/au1000_generic.h
@@ -26,7 +26,6 @@
26#include <pcmcia/cs_types.h> 26#include <pcmcia/cs_types.h>
27#include <pcmcia/cs.h> 27#include <pcmcia/cs.h>
28#include <pcmcia/ss.h> 28#include <pcmcia/ss.h>
29#include <pcmcia/bulkmem.h>
30#include <pcmcia/cistpl.h> 29#include <pcmcia/cistpl.h>
31#include "cs_internal.h" 30#include "cs_internal.h"
32 31
@@ -34,9 +33,9 @@
34#define AU1000_PCMCIA_IO_SPEED (255) 33#define AU1000_PCMCIA_IO_SPEED (255)
35#define AU1000_PCMCIA_MEM_SPEED (300) 34#define AU1000_PCMCIA_MEM_SPEED (300)
36 35
37#define AU1X_SOCK0_IO 0xF00000000 36#define AU1X_SOCK0_IO 0xF00000000ULL
38#define AU1X_SOCK0_PHYS_ATTR 0xF40000000 37#define AU1X_SOCK0_PHYS_ATTR 0xF40000000ULL
39#define AU1X_SOCK0_PHYS_MEM 0xF80000000 38#define AU1X_SOCK0_PHYS_MEM 0xF80000000ULL
40/* pseudo 32 bit phys addresses, which get fixed up to the 39/* pseudo 32 bit phys addresses, which get fixed up to the
41 * real 36 bit address in fixup_bigphys_addr() */ 40 * real 36 bit address in fixup_bigphys_addr() */
42#define AU1X_SOCK0_PSEUDO_PHYS_ATTR 0xF4000000 41#define AU1X_SOCK0_PSEUDO_PHYS_ATTR 0xF4000000
@@ -45,16 +44,20 @@
45/* pcmcia socket 1 needs external glue logic so the memory map 44/* pcmcia socket 1 needs external glue logic so the memory map
46 * differs from board to board. 45 * differs from board to board.
47 */ 46 */
48#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_PB1200) 47#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || \
49#define AU1X_SOCK1_IO 0xF08000000 48 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) || \
50#define AU1X_SOCK1_PHYS_ATTR 0xF48000000 49 defined(CONFIG_MIPS_PB1200)
51#define AU1X_SOCK1_PHYS_MEM 0xF88000000 50#define AU1X_SOCK1_IO 0xF08000000ULL
51#define AU1X_SOCK1_PHYS_ATTR 0xF48000000ULL
52#define AU1X_SOCK1_PHYS_MEM 0xF88000000ULL
52#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4800000 53#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4800000
53#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8800000 54#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8800000
54#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) || defined(CONFIG_MIPS_DB1200) 55#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
55#define AU1X_SOCK1_IO 0xF04000000 56 defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) || \
56#define AU1X_SOCK1_PHYS_ATTR 0xF44000000 57 defined(CONFIG_MIPS_DB1200)
57#define AU1X_SOCK1_PHYS_MEM 0xF84000000 58#define AU1X_SOCK1_IO 0xF04000000ULL
59#define AU1X_SOCK1_PHYS_ATTR 0xF44000000ULL
60#define AU1X_SOCK1_PHYS_MEM 0xF84000000ULL
58#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4400000 61#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4400000
59#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8400000 62#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8400000
60#endif 63#endif