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-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/access.c18
-rw-r--r--drivers/pci/bus.c6
-rw-r--r--drivers/pci/dmar.c7
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c7
-rw-r--r--drivers/pci/hotplug/pcihp_slot.c45
-rw-r--r--drivers/pci/intel-iommu.c243
-rw-r--r--drivers/pci/iov.c1
-rw-r--r--drivers/pci/iova.c12
-rw-r--r--drivers/pci/pci-acpi.c2
-rw-r--r--drivers/pci/pci-driver.c4
-rw-r--r--drivers/pci/pci-sysfs.c62
-rw-r--r--drivers/pci/pci.c450
-rw-r--r--drivers/pci/pci.h42
-rw-r--r--drivers/pci/pcie/aer/aer_inject.c2
-rw-r--r--drivers/pci/pcie/aer/aerdrv.h9
-rw-r--r--drivers/pci/pcie/aspm.c21
-rw-r--r--drivers/pci/probe.c45
-rw-r--r--drivers/pci/quirks.c23
-rw-r--r--drivers/pci/remove.c2
-rw-r--r--drivers/pci/setup-bus.c140
21 files changed, 956 insertions, 186 deletions
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c85f744270a5..094308e41be5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_X86_VISWS) += setup-irq.o
51obj-$(CONFIG_MN10300) += setup-bus.o 51obj-$(CONFIG_MN10300) += setup-bus.o
52obj-$(CONFIG_MICROBLAZE) += setup-bus.o 52obj-$(CONFIG_MICROBLAZE) += setup-bus.o
53obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o 53obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o
54obj-$(CONFIG_SPARC_LEON) += setup-bus.o setup-irq.o
54 55
55# 56#
56# ACPI Related PCI FW Functions 57# ACPI Related PCI FW Functions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 531bc697d800..fdaa42aac7c6 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -143,33 +143,41 @@ static noinline void pci_wait_ucfg(struct pci_dev *dev)
143 __remove_wait_queue(&pci_ucfg_wait, &wait); 143 __remove_wait_queue(&pci_ucfg_wait, &wait);
144} 144}
145 145
146/* Returns 0 on success, negative values indicate error. */
146#define PCI_USER_READ_CONFIG(size,type) \ 147#define PCI_USER_READ_CONFIG(size,type) \
147int pci_user_read_config_##size \ 148int pci_user_read_config_##size \
148 (struct pci_dev *dev, int pos, type *val) \ 149 (struct pci_dev *dev, int pos, type *val) \
149{ \ 150{ \
150 int ret = 0; \ 151 int ret = 0; \
151 u32 data = -1; \ 152 u32 data = -1; \
152 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 153 if (PCI_##size##_BAD) \
154 return -EINVAL; \
153 raw_spin_lock_irq(&pci_lock); \ 155 raw_spin_lock_irq(&pci_lock); \
154 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ 156 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
155 ret = dev->bus->ops->read(dev->bus, dev->devfn, \ 157 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
156 pos, sizeof(type), &data); \ 158 pos, sizeof(type), &data); \
157 raw_spin_unlock_irq(&pci_lock); \ 159 raw_spin_unlock_irq(&pci_lock); \
158 *val = (type)data; \ 160 *val = (type)data; \
161 if (ret > 0) \
162 ret = -EINVAL; \
159 return ret; \ 163 return ret; \
160} 164}
161 165
166/* Returns 0 on success, negative values indicate error. */
162#define PCI_USER_WRITE_CONFIG(size,type) \ 167#define PCI_USER_WRITE_CONFIG(size,type) \
163int pci_user_write_config_##size \ 168int pci_user_write_config_##size \
164 (struct pci_dev *dev, int pos, type val) \ 169 (struct pci_dev *dev, int pos, type val) \
165{ \ 170{ \
166 int ret = -EIO; \ 171 int ret = -EIO; \
167 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 172 if (PCI_##size##_BAD) \
173 return -EINVAL; \
168 raw_spin_lock_irq(&pci_lock); \ 174 raw_spin_lock_irq(&pci_lock); \
169 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ 175 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
170 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 176 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
171 pos, sizeof(type), val); \ 177 pos, sizeof(type), val); \
172 raw_spin_unlock_irq(&pci_lock); \ 178 raw_spin_unlock_irq(&pci_lock); \
179 if (ret > 0) \
180 ret = -EINVAL; \
173 return ret; \ 181 return ret; \
174} 182}
175 183
@@ -197,6 +205,8 @@ struct pci_vpd_pci22 {
197 * This code has to spin since there is no other notification from the PCI 205 * This code has to spin since there is no other notification from the PCI
198 * hardware. Since the VPD is often implemented by serial attachment to an 206 * hardware. Since the VPD is often implemented by serial attachment to an
199 * EEPROM, it may take many milliseconds to complete. 207 * EEPROM, it may take many milliseconds to complete.
208 *
209 * Returns 0 on success, negative values indicate error.
200 */ 210 */
201static int pci_vpd_pci22_wait(struct pci_dev *dev) 211static int pci_vpd_pci22_wait(struct pci_dev *dev)
202{ 212{
@@ -212,7 +222,7 @@ static int pci_vpd_pci22_wait(struct pci_dev *dev)
212 for (;;) { 222 for (;;) {
213 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, 223 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
214 &status); 224 &status);
215 if (ret) 225 if (ret < 0)
216 return ret; 226 return ret;
217 227
218 if ((status & PCI_VPD_ADDR_F) == vpd->flag) { 228 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
@@ -324,6 +334,8 @@ static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count
324 vpd->busy = true; 334 vpd->busy = true;
325 vpd->flag = 0; 335 vpd->flag = 0;
326 ret = pci_vpd_pci22_wait(dev); 336 ret = pci_vpd_pci22_wait(dev);
337 if (ret < 0)
338 break;
327 339
328 pos += sizeof(u32); 340 pos += sizeof(u32);
329 } 341 }
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 69546e9213dd..1e2ad92a4752 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -163,12 +163,6 @@ int pci_bus_add_child(struct pci_bus *bus)
163 163
164 bus->is_added = 1; 164 bus->is_added = 1;
165 165
166 retval = device_create_file(&bus->dev, &dev_attr_cpuaffinity);
167 if (retval)
168 return retval;
169
170 retval = device_create_file(&bus->dev, &dev_attr_cpulistaffinity);
171
172 /* Create legacy_io and legacy_mem files for this bus */ 166 /* Create legacy_io and legacy_mem files for this bus */
173 pci_create_legacy_files(bus); 167 pci_create_legacy_files(bus);
174 168
diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c
index 12e02bf92c4a..3dc9befa5aec 100644
--- a/drivers/pci/dmar.c
+++ b/drivers/pci/dmar.c
@@ -698,12 +698,7 @@ int __init detect_intel_iommu(void)
698 { 698 {
699#ifdef CONFIG_INTR_REMAP 699#ifdef CONFIG_INTR_REMAP
700 struct acpi_table_dmar *dmar; 700 struct acpi_table_dmar *dmar;
701 /* 701
702 * for now we will disable dma-remapping when interrupt
703 * remapping is enabled.
704 * When support for queued invalidation for IOTLB invalidation
705 * is added, we will not need this any more.
706 */
707 dmar = (struct acpi_table_dmar *) dmar_tbl; 702 dmar = (struct acpi_table_dmar *) dmar_tbl;
708 if (ret && cpu_has_x2apic && dmar->flags & 0x1) 703 if (ret && cpu_has_x2apic && dmar->flags & 0x1)
709 printk(KERN_INFO 704 printk(KERN_INFO
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 2f67e9bc2f96..a70fa89f76fd 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -827,6 +827,13 @@ static int __ref enable_device(struct acpiphp_slot *slot)
827 acpiphp_set_hpp_values(bus); 827 acpiphp_set_hpp_values(bus);
828 acpiphp_set_acpi_region(slot); 828 acpiphp_set_acpi_region(slot);
829 pci_enable_bridges(bus); 829 pci_enable_bridges(bus);
830
831 list_for_each_entry(dev, &bus->devices, bus_list) {
832 /* Assume that newly added devices are powered on already. */
833 if (!dev->is_added)
834 dev->current_state = PCI_D0;
835 }
836
830 pci_bus_add_devices(bus); 837 pci_bus_add_devices(bus);
831 838
832 list_for_each_entry(func, &slot->funcs, sibling) { 839 list_for_each_entry(func, &slot->funcs, sibling) {
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
index 80b461c98557..749fdf070319 100644
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ b/drivers/pci/hotplug/pcihp_slot.c
@@ -158,6 +158,47 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
158 */ 158 */
159} 159}
160 160
161/* Program PCIE MaxPayload setting on device: ensure parent maxpayload <= device */
162static int pci_set_payload(struct pci_dev *dev)
163{
164 int pos, ppos;
165 u16 pctl, psz;
166 u16 dctl, dsz, dcap, dmax;
167 struct pci_dev *parent;
168
169 parent = dev->bus->self;
170 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
171 if (!pos)
172 return 0;
173
174 /* Read Device MaxPayload capability and setting */
175 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &dctl);
176 pci_read_config_word(dev, pos + PCI_EXP_DEVCAP, &dcap);
177 dsz = (dctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
178 dmax = (dcap & PCI_EXP_DEVCAP_PAYLOAD);
179
180 /* Read Parent MaxPayload setting */
181 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP);
182 if (!ppos)
183 return 0;
184 pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
185 psz = (pctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
186
187 /* If parent payload > device max payload -> error
188 * If parent payload > device payload -> set speed
189 * If parent payload <= device payload -> do nothing
190 */
191 if (psz > dmax)
192 return -1;
193 else if (psz > dsz) {
194 dev_info(&dev->dev, "Setting MaxPayload to %d\n", 128 << psz);
195 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
196 (dctl & ~PCI_EXP_DEVCTL_PAYLOAD) +
197 (psz << 5));
198 }
199 return 0;
200}
201
161void pci_configure_slot(struct pci_dev *dev) 202void pci_configure_slot(struct pci_dev *dev)
162{ 203{
163 struct pci_dev *cdev; 204 struct pci_dev *cdev;
@@ -169,6 +210,10 @@ void pci_configure_slot(struct pci_dev *dev)
169 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) 210 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
170 return; 211 return;
171 212
213 ret = pci_set_payload(dev);
214 if (ret)
215 dev_warn(&dev->dev, "could not set device max payload\n");
216
172 memset(&hpp, 0, sizeof(hpp)); 217 memset(&hpp, 0, sizeof(hpp));
173 ret = pci_get_hp_params(dev, &hpp); 218 ret = pci_get_hp_params(dev, &hpp);
174 if (ret) 219 if (ret)
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index d552d2c77844..f02c34d26d1b 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -39,6 +39,7 @@
39#include <linux/syscore_ops.h> 39#include <linux/syscore_ops.h>
40#include <linux/tboot.h> 40#include <linux/tboot.h>
41#include <linux/dmi.h> 41#include <linux/dmi.h>
42#include <linux/pci-ats.h>
42#include <asm/cacheflush.h> 43#include <asm/cacheflush.h>
43#include <asm/iommu.h> 44#include <asm/iommu.h>
44#include "pci.h" 45#include "pci.h"
@@ -46,6 +47,8 @@
46#define ROOT_SIZE VTD_PAGE_SIZE 47#define ROOT_SIZE VTD_PAGE_SIZE
47#define CONTEXT_SIZE VTD_PAGE_SIZE 48#define CONTEXT_SIZE VTD_PAGE_SIZE
48 49
50#define IS_BRIDGE_HOST_DEVICE(pdev) \
51 ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
49#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) 52#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
50#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) 53#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
51#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) 54#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
@@ -115,6 +118,11 @@ static inline unsigned long align_to_level(unsigned long pfn, int level)
115 return (pfn + level_size(level) - 1) & level_mask(level); 118 return (pfn + level_size(level) - 1) & level_mask(level);
116} 119}
117 120
121static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
122{
123 return 1 << ((lvl - 1) * LEVEL_STRIDE);
124}
125
118/* VT-d pages must always be _smaller_ than MM pages. Otherwise things 126/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
119 are never going to work. */ 127 are never going to work. */
120static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) 128static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
@@ -142,6 +150,12 @@ static void __init check_tylersburg_isoch(void);
142static int rwbf_quirk; 150static int rwbf_quirk;
143 151
144/* 152/*
153 * set to 1 to panic kernel if can't successfully enable VT-d
154 * (used when kernel is launched w/ TXT)
155 */
156static int force_on = 0;
157
158/*
145 * 0: Present 159 * 0: Present
146 * 1-11: Reserved 160 * 1-11: Reserved
147 * 12-63: Context Ptr (12 - (haw-1)) 161 * 12-63: Context Ptr (12 - (haw-1))
@@ -337,6 +351,9 @@ struct dmar_domain {
337 int iommu_coherency;/* indicate coherency of iommu access */ 351 int iommu_coherency;/* indicate coherency of iommu access */
338 int iommu_snooping; /* indicate snooping control feature*/ 352 int iommu_snooping; /* indicate snooping control feature*/
339 int iommu_count; /* reference count of iommu */ 353 int iommu_count; /* reference count of iommu */
354 int iommu_superpage;/* Level of superpages supported:
355 0 == 4KiB (no superpages), 1 == 2MiB,
356 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
340 spinlock_t iommu_lock; /* protect iommu set in domain */ 357 spinlock_t iommu_lock; /* protect iommu set in domain */
341 u64 max_addr; /* maximum mapped address */ 358 u64 max_addr; /* maximum mapped address */
342}; 359};
@@ -386,6 +403,7 @@ int dmar_disabled = 1;
386static int dmar_map_gfx = 1; 403static int dmar_map_gfx = 1;
387static int dmar_forcedac; 404static int dmar_forcedac;
388static int intel_iommu_strict; 405static int intel_iommu_strict;
406static int intel_iommu_superpage = 1;
389 407
390#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) 408#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
391static DEFINE_SPINLOCK(device_domain_lock); 409static DEFINE_SPINLOCK(device_domain_lock);
@@ -416,6 +434,10 @@ static int __init intel_iommu_setup(char *str)
416 printk(KERN_INFO 434 printk(KERN_INFO
417 "Intel-IOMMU: disable batched IOTLB flush\n"); 435 "Intel-IOMMU: disable batched IOTLB flush\n");
418 intel_iommu_strict = 1; 436 intel_iommu_strict = 1;
437 } else if (!strncmp(str, "sp_off", 6)) {
438 printk(KERN_INFO
439 "Intel-IOMMU: disable supported super page\n");
440 intel_iommu_superpage = 0;
419 } 441 }
420 442
421 str += strcspn(str, ","); 443 str += strcspn(str, ",");
@@ -554,11 +576,32 @@ static void domain_update_iommu_snooping(struct dmar_domain *domain)
554 } 576 }
555} 577}
556 578
579static void domain_update_iommu_superpage(struct dmar_domain *domain)
580{
581 int i, mask = 0xf;
582
583 if (!intel_iommu_superpage) {
584 domain->iommu_superpage = 0;
585 return;
586 }
587
588 domain->iommu_superpage = 4; /* 1TiB */
589
590 for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
591 mask |= cap_super_page_val(g_iommus[i]->cap);
592 if (!mask) {
593 break;
594 }
595 }
596 domain->iommu_superpage = fls(mask);
597}
598
557/* Some capabilities may be different across iommus */ 599/* Some capabilities may be different across iommus */
558static void domain_update_iommu_cap(struct dmar_domain *domain) 600static void domain_update_iommu_cap(struct dmar_domain *domain)
559{ 601{
560 domain_update_iommu_coherency(domain); 602 domain_update_iommu_coherency(domain);
561 domain_update_iommu_snooping(domain); 603 domain_update_iommu_snooping(domain);
604 domain_update_iommu_superpage(domain);
562} 605}
563 606
564static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) 607static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
@@ -688,23 +731,31 @@ out:
688} 731}
689 732
690static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, 733static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
691 unsigned long pfn) 734 unsigned long pfn, int large_level)
692{ 735{
693 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; 736 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
694 struct dma_pte *parent, *pte = NULL; 737 struct dma_pte *parent, *pte = NULL;
695 int level = agaw_to_level(domain->agaw); 738 int level = agaw_to_level(domain->agaw);
696 int offset; 739 int offset, target_level;
697 740
698 BUG_ON(!domain->pgd); 741 BUG_ON(!domain->pgd);
699 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width); 742 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
700 parent = domain->pgd; 743 parent = domain->pgd;
701 744
745 /* Search pte */
746 if (!large_level)
747 target_level = 1;
748 else
749 target_level = large_level;
750
702 while (level > 0) { 751 while (level > 0) {
703 void *tmp_page; 752 void *tmp_page;
704 753
705 offset = pfn_level_offset(pfn, level); 754 offset = pfn_level_offset(pfn, level);
706 pte = &parent[offset]; 755 pte = &parent[offset];
707 if (level == 1) 756 if (!large_level && (pte->val & DMA_PTE_LARGE_PAGE))
757 break;
758 if (level == target_level)
708 break; 759 break;
709 760
710 if (!dma_pte_present(pte)) { 761 if (!dma_pte_present(pte)) {
@@ -732,10 +783,11 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
732 return pte; 783 return pte;
733} 784}
734 785
786
735/* return address's pte at specific level */ 787/* return address's pte at specific level */
736static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, 788static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
737 unsigned long pfn, 789 unsigned long pfn,
738 int level) 790 int level, int *large_page)
739{ 791{
740 struct dma_pte *parent, *pte = NULL; 792 struct dma_pte *parent, *pte = NULL;
741 int total = agaw_to_level(domain->agaw); 793 int total = agaw_to_level(domain->agaw);
@@ -748,8 +800,16 @@ static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
748 if (level == total) 800 if (level == total)
749 return pte; 801 return pte;
750 802
751 if (!dma_pte_present(pte)) 803 if (!dma_pte_present(pte)) {
804 *large_page = total;
752 break; 805 break;
806 }
807
808 if (pte->val & DMA_PTE_LARGE_PAGE) {
809 *large_page = total;
810 return pte;
811 }
812
753 parent = phys_to_virt(dma_pte_addr(pte)); 813 parent = phys_to_virt(dma_pte_addr(pte));
754 total--; 814 total--;
755 } 815 }
@@ -762,6 +822,7 @@ static void dma_pte_clear_range(struct dmar_domain *domain,
762 unsigned long last_pfn) 822 unsigned long last_pfn)
763{ 823{
764 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; 824 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
825 unsigned int large_page = 1;
765 struct dma_pte *first_pte, *pte; 826 struct dma_pte *first_pte, *pte;
766 827
767 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); 828 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
@@ -770,14 +831,15 @@ static void dma_pte_clear_range(struct dmar_domain *domain,
770 831
771 /* we don't need lock here; nobody else touches the iova range */ 832 /* we don't need lock here; nobody else touches the iova range */
772 do { 833 do {
773 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1); 834 large_page = 1;
835 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
774 if (!pte) { 836 if (!pte) {
775 start_pfn = align_to_level(start_pfn + 1, 2); 837 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
776 continue; 838 continue;
777 } 839 }
778 do { 840 do {
779 dma_clear_pte(pte); 841 dma_clear_pte(pte);
780 start_pfn++; 842 start_pfn += lvl_to_nr_pages(large_page);
781 pte++; 843 pte++;
782 } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); 844 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
783 845
@@ -797,6 +859,7 @@ static void dma_pte_free_pagetable(struct dmar_domain *domain,
797 int total = agaw_to_level(domain->agaw); 859 int total = agaw_to_level(domain->agaw);
798 int level; 860 int level;
799 unsigned long tmp; 861 unsigned long tmp;
862 int large_page = 2;
800 863
801 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); 864 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
802 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); 865 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
@@ -812,7 +875,10 @@ static void dma_pte_free_pagetable(struct dmar_domain *domain,
812 return; 875 return;
813 876
814 do { 877 do {
815 first_pte = pte = dma_pfn_level_pte(domain, tmp, level); 878 large_page = level;
879 first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
880 if (large_page > level)
881 level = large_page + 1;
816 if (!pte) { 882 if (!pte) {
817 tmp = align_to_level(tmp + 1, level + 1); 883 tmp = align_to_level(tmp + 1, level + 1);
818 continue; 884 continue;
@@ -1396,6 +1462,7 @@ static int domain_init(struct dmar_domain *domain, int guest_width)
1396 else 1462 else
1397 domain->iommu_snooping = 0; 1463 domain->iommu_snooping = 0;
1398 1464
1465 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1399 domain->iommu_count = 1; 1466 domain->iommu_count = 1;
1400 domain->nid = iommu->node; 1467 domain->nid = iommu->node;
1401 1468
@@ -1416,6 +1483,10 @@ static void domain_exit(struct dmar_domain *domain)
1416 if (!domain) 1483 if (!domain)
1417 return; 1484 return;
1418 1485
1486 /* Flush any lazy unmaps that may reference this domain */
1487 if (!intel_iommu_strict)
1488 flush_unmaps_timeout(0);
1489
1419 domain_remove_dev_info(domain); 1490 domain_remove_dev_info(domain);
1420 /* destroy iovas */ 1491 /* destroy iovas */
1421 put_iova_domain(&domain->iovad); 1492 put_iova_domain(&domain->iovad);
@@ -1647,6 +1718,34 @@ static inline unsigned long aligned_nrpages(unsigned long host_addr,
1647 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; 1718 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1648} 1719}
1649 1720
1721/* Return largest possible superpage level for a given mapping */
1722static inline int hardware_largepage_caps(struct dmar_domain *domain,
1723 unsigned long iov_pfn,
1724 unsigned long phy_pfn,
1725 unsigned long pages)
1726{
1727 int support, level = 1;
1728 unsigned long pfnmerge;
1729
1730 support = domain->iommu_superpage;
1731
1732 /* To use a large page, the virtual *and* physical addresses
1733 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1734 of them will mean we have to use smaller pages. So just
1735 merge them and check both at once. */
1736 pfnmerge = iov_pfn | phy_pfn;
1737
1738 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1739 pages >>= VTD_STRIDE_SHIFT;
1740 if (!pages)
1741 break;
1742 pfnmerge >>= VTD_STRIDE_SHIFT;
1743 level++;
1744 support--;
1745 }
1746 return level;
1747}
1748
1650static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, 1749static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1651 struct scatterlist *sg, unsigned long phys_pfn, 1750 struct scatterlist *sg, unsigned long phys_pfn,
1652 unsigned long nr_pages, int prot) 1751 unsigned long nr_pages, int prot)
@@ -1655,6 +1754,8 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1655 phys_addr_t uninitialized_var(pteval); 1754 phys_addr_t uninitialized_var(pteval);
1656 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; 1755 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1657 unsigned long sg_res; 1756 unsigned long sg_res;
1757 unsigned int largepage_lvl = 0;
1758 unsigned long lvl_pages = 0;
1658 1759
1659 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); 1760 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1660 1761
@@ -1670,7 +1771,7 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1670 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; 1771 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1671 } 1772 }
1672 1773
1673 while (nr_pages--) { 1774 while (nr_pages > 0) {
1674 uint64_t tmp; 1775 uint64_t tmp;
1675 1776
1676 if (!sg_res) { 1777 if (!sg_res) {
@@ -1678,11 +1779,21 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1678 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; 1779 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1679 sg->dma_length = sg->length; 1780 sg->dma_length = sg->length;
1680 pteval = page_to_phys(sg_page(sg)) | prot; 1781 pteval = page_to_phys(sg_page(sg)) | prot;
1782 phys_pfn = pteval >> VTD_PAGE_SHIFT;
1681 } 1783 }
1784
1682 if (!pte) { 1785 if (!pte) {
1683 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn); 1786 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1787
1788 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
1684 if (!pte) 1789 if (!pte)
1685 return -ENOMEM; 1790 return -ENOMEM;
1791 /* It is large page*/
1792 if (largepage_lvl > 1)
1793 pteval |= DMA_PTE_LARGE_PAGE;
1794 else
1795 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
1796
1686 } 1797 }
1687 /* We don't need lock here, nobody else 1798 /* We don't need lock here, nobody else
1688 * touches the iova range 1799 * touches the iova range
@@ -1698,16 +1809,38 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1698 } 1809 }
1699 WARN_ON(1); 1810 WARN_ON(1);
1700 } 1811 }
1812
1813 lvl_pages = lvl_to_nr_pages(largepage_lvl);
1814
1815 BUG_ON(nr_pages < lvl_pages);
1816 BUG_ON(sg_res < lvl_pages);
1817
1818 nr_pages -= lvl_pages;
1819 iov_pfn += lvl_pages;
1820 phys_pfn += lvl_pages;
1821 pteval += lvl_pages * VTD_PAGE_SIZE;
1822 sg_res -= lvl_pages;
1823
1824 /* If the next PTE would be the first in a new page, then we
1825 need to flush the cache on the entries we've just written.
1826 And then we'll need to recalculate 'pte', so clear it and
1827 let it get set again in the if (!pte) block above.
1828
1829 If we're done (!nr_pages) we need to flush the cache too.
1830
1831 Also if we've been setting superpages, we may need to
1832 recalculate 'pte' and switch back to smaller pages for the
1833 end of the mapping, if the trailing size is not enough to
1834 use another superpage (i.e. sg_res < lvl_pages). */
1701 pte++; 1835 pte++;
1702 if (!nr_pages || first_pte_in_page(pte)) { 1836 if (!nr_pages || first_pte_in_page(pte) ||
1837 (largepage_lvl > 1 && sg_res < lvl_pages)) {
1703 domain_flush_cache(domain, first_pte, 1838 domain_flush_cache(domain, first_pte,
1704 (void *)pte - (void *)first_pte); 1839 (void *)pte - (void *)first_pte);
1705 pte = NULL; 1840 pte = NULL;
1706 } 1841 }
1707 iov_pfn++; 1842
1708 pteval += VTD_PAGE_SIZE; 1843 if (!sg_res && nr_pages)
1709 sg_res--;
1710 if (!sg_res)
1711 sg = sg_next(sg); 1844 sg = sg_next(sg);
1712 } 1845 }
1713 return 0; 1846 return 0;
@@ -2015,7 +2148,7 @@ static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2015 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) 2148 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2016 return 0; 2149 return 0;
2017 return iommu_prepare_identity_map(pdev, rmrr->base_address, 2150 return iommu_prepare_identity_map(pdev, rmrr->base_address,
2018 rmrr->end_address + 1); 2151 rmrr->end_address);
2019} 2152}
2020 2153
2021#ifdef CONFIG_DMAR_FLOPPY_WA 2154#ifdef CONFIG_DMAR_FLOPPY_WA
@@ -2029,7 +2162,7 @@ static inline void iommu_prepare_isa(void)
2029 return; 2162 return;
2030 2163
2031 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); 2164 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2032 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024); 2165 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
2033 2166
2034 if (ret) 2167 if (ret)
2035 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " 2168 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
@@ -2105,10 +2238,10 @@ static int identity_mapping(struct pci_dev *pdev)
2105 if (likely(!iommu_identity_mapping)) 2238 if (likely(!iommu_identity_mapping))
2106 return 0; 2239 return 0;
2107 2240
2241 info = pdev->dev.archdata.iommu;
2242 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2243 return (info->domain == si_domain);
2108 2244
2109 list_for_each_entry(info, &si_domain->devices, link)
2110 if (info->dev == pdev)
2111 return 1;
2112 return 0; 2245 return 0;
2113} 2246}
2114 2247
@@ -2186,8 +2319,19 @@ static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2186 * Assume that they will -- if they turn out not to be, then we can 2319 * Assume that they will -- if they turn out not to be, then we can
2187 * take them out of the 1:1 domain later. 2320 * take them out of the 1:1 domain later.
2188 */ 2321 */
2189 if (!startup) 2322 if (!startup) {
2190 return pdev->dma_mask > DMA_BIT_MASK(32); 2323 /*
2324 * If the device's dma_mask is less than the system's memory
2325 * size then this is not a candidate for identity mapping.
2326 */
2327 u64 dma_mask = pdev->dma_mask;
2328
2329 if (pdev->dev.coherent_dma_mask &&
2330 pdev->dev.coherent_dma_mask < dma_mask)
2331 dma_mask = pdev->dev.coherent_dma_mask;
2332
2333 return dma_mask >= dma_get_required_mask(&pdev->dev);
2334 }
2191 2335
2192 return 1; 2336 return 1;
2193} 2337}
@@ -2202,6 +2346,9 @@ static int __init iommu_prepare_static_identity_mapping(int hw)
2202 return -EFAULT; 2346 return -EFAULT;
2203 2347
2204 for_each_pci_dev(pdev) { 2348 for_each_pci_dev(pdev) {
2349 /* Skip Host/PCI Bridge devices */
2350 if (IS_BRIDGE_HOST_DEVICE(pdev))
2351 continue;
2205 if (iommu_should_identity_map(pdev, 1)) { 2352 if (iommu_should_identity_map(pdev, 1)) {
2206 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n", 2353 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2207 hw ? "hardware" : "software", pci_name(pdev)); 2354 hw ? "hardware" : "software", pci_name(pdev));
@@ -2217,7 +2364,7 @@ static int __init iommu_prepare_static_identity_mapping(int hw)
2217 return 0; 2364 return 0;
2218} 2365}
2219 2366
2220static int __init init_dmars(int force_on) 2367static int __init init_dmars(void)
2221{ 2368{
2222 struct dmar_drhd_unit *drhd; 2369 struct dmar_drhd_unit *drhd;
2223 struct dmar_rmrr_unit *rmrr; 2370 struct dmar_rmrr_unit *rmrr;
@@ -2591,8 +2738,7 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2591 iommu = domain_get_iommu(domain); 2738 iommu = domain_get_iommu(domain);
2592 size = aligned_nrpages(paddr, size); 2739 size = aligned_nrpages(paddr, size);
2593 2740
2594 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), 2741 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
2595 pdev->dma_mask);
2596 if (!iova) 2742 if (!iova)
2597 goto error; 2743 goto error;
2598 2744
@@ -3117,7 +3263,17 @@ static int init_iommu_hw(void)
3117 if (iommu->qi) 3263 if (iommu->qi)
3118 dmar_reenable_qi(iommu); 3264 dmar_reenable_qi(iommu);
3119 3265
3120 for_each_active_iommu(iommu, drhd) { 3266 for_each_iommu(iommu, drhd) {
3267 if (drhd->ignored) {
3268 /*
3269 * we always have to disable PMRs or DMA may fail on
3270 * this device
3271 */
3272 if (force_on)
3273 iommu_disable_protect_mem_regions(iommu);
3274 continue;
3275 }
3276
3121 iommu_flush_write_buffer(iommu); 3277 iommu_flush_write_buffer(iommu);
3122 3278
3123 iommu_set_root_entry(iommu); 3279 iommu_set_root_entry(iommu);
@@ -3126,7 +3282,8 @@ static int init_iommu_hw(void)
3126 DMA_CCMD_GLOBAL_INVL); 3282 DMA_CCMD_GLOBAL_INVL);
3127 iommu->flush.flush_iotlb(iommu, 0, 0, 0, 3283 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3128 DMA_TLB_GLOBAL_FLUSH); 3284 DMA_TLB_GLOBAL_FLUSH);
3129 iommu_enable_translation(iommu); 3285 if (iommu_enable_translation(iommu))
3286 return 1;
3130 iommu_disable_protect_mem_regions(iommu); 3287 iommu_disable_protect_mem_regions(iommu);
3131 } 3288 }
3132 3289
@@ -3193,7 +3350,10 @@ static void iommu_resume(void)
3193 unsigned long flag; 3350 unsigned long flag;
3194 3351
3195 if (init_iommu_hw()) { 3352 if (init_iommu_hw()) {
3196 WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); 3353 if (force_on)
3354 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3355 else
3356 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3197 return; 3357 return;
3198 } 3358 }
3199 3359
@@ -3228,7 +3388,7 @@ static void __init init_iommu_pm_ops(void)
3228} 3388}
3229 3389
3230#else 3390#else
3231static inline int init_iommu_pm_ops(void) { } 3391static inline void init_iommu_pm_ops(void) {}
3232#endif /* CONFIG_PM */ 3392#endif /* CONFIG_PM */
3233 3393
3234/* 3394/*
@@ -3270,7 +3430,6 @@ static struct notifier_block device_nb = {
3270int __init intel_iommu_init(void) 3430int __init intel_iommu_init(void)
3271{ 3431{
3272 int ret = 0; 3432 int ret = 0;
3273 int force_on = 0;
3274 3433
3275 /* VT-d is required for a TXT/tboot launch, so enforce that */ 3434 /* VT-d is required for a TXT/tboot launch, so enforce that */
3276 force_on = tboot_force_iommu(); 3435 force_on = tboot_force_iommu();
@@ -3308,7 +3467,7 @@ int __init intel_iommu_init(void)
3308 3467
3309 init_no_remapping_devices(); 3468 init_no_remapping_devices();
3310 3469
3311 ret = init_dmars(force_on); 3470 ret = init_dmars();
3312 if (ret) { 3471 if (ret) {
3313 if (force_on) 3472 if (force_on)
3314 panic("tboot: Failed to initialize DMARs\n"); 3473 panic("tboot: Failed to initialize DMARs\n");
@@ -3379,8 +3538,8 @@ static void domain_remove_one_dev_info(struct dmar_domain *domain,
3379 spin_lock_irqsave(&device_domain_lock, flags); 3538 spin_lock_irqsave(&device_domain_lock, flags);
3380 list_for_each_safe(entry, tmp, &domain->devices) { 3539 list_for_each_safe(entry, tmp, &domain->devices) {
3381 info = list_entry(entry, struct device_domain_info, link); 3540 info = list_entry(entry, struct device_domain_info, link);
3382 /* No need to compare PCI domain; it has to be the same */ 3541 if (info->segment == pci_domain_nr(pdev->bus) &&
3383 if (info->bus == pdev->bus->number && 3542 info->bus == pdev->bus->number &&
3384 info->devfn == pdev->devfn) { 3543 info->devfn == pdev->devfn) {
3385 list_del(&info->link); 3544 list_del(&info->link);
3386 list_del(&info->global); 3545 list_del(&info->global);
@@ -3418,10 +3577,13 @@ static void domain_remove_one_dev_info(struct dmar_domain *domain,
3418 domain_update_iommu_cap(domain); 3577 domain_update_iommu_cap(domain);
3419 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); 3578 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3420 3579
3421 spin_lock_irqsave(&iommu->lock, tmp_flags); 3580 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3422 clear_bit(domain->id, iommu->domain_ids); 3581 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
3423 iommu->domains[domain->id] = NULL; 3582 spin_lock_irqsave(&iommu->lock, tmp_flags);
3424 spin_unlock_irqrestore(&iommu->lock, tmp_flags); 3583 clear_bit(domain->id, iommu->domain_ids);
3584 iommu->domains[domain->id] = NULL;
3585 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
3586 }
3425 } 3587 }
3426 3588
3427 spin_unlock_irqrestore(&device_domain_lock, flags); 3589 spin_unlock_irqrestore(&device_domain_lock, flags);
@@ -3504,6 +3666,7 @@ static int md_domain_init(struct dmar_domain *domain, int guest_width)
3504 domain->iommu_count = 0; 3666 domain->iommu_count = 0;
3505 domain->iommu_coherency = 0; 3667 domain->iommu_coherency = 0;
3506 domain->iommu_snooping = 0; 3668 domain->iommu_snooping = 0;
3669 domain->iommu_superpage = 0;
3507 domain->max_addr = 0; 3670 domain->max_addr = 0;
3508 domain->nid = -1; 3671 domain->nid = -1;
3509 3672
@@ -3719,7 +3882,7 @@ static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3719 struct dma_pte *pte; 3882 struct dma_pte *pte;
3720 u64 phys = 0; 3883 u64 phys = 0;
3721 3884
3722 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT); 3885 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
3723 if (pte) 3886 if (pte)
3724 phys = dma_pte_addr(pte); 3887 phys = dma_pte_addr(pte);
3725 3888
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 553d8ee55c1c..42fae4776515 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -13,6 +13,7 @@
13#include <linux/mutex.h> 13#include <linux/mutex.h>
14#include <linux/string.h> 14#include <linux/string.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/pci-ats.h>
16#include "pci.h" 17#include "pci.h"
17 18
18#define VIRTFN_ID_LEN 16 19#define VIRTFN_ID_LEN 16
diff --git a/drivers/pci/iova.c b/drivers/pci/iova.c
index 9606e599a475..c5c274ab5c5a 100644
--- a/drivers/pci/iova.c
+++ b/drivers/pci/iova.c
@@ -63,8 +63,16 @@ __cached_rbnode_delete_update(struct iova_domain *iovad, struct iova *free)
63 curr = iovad->cached32_node; 63 curr = iovad->cached32_node;
64 cached_iova = container_of(curr, struct iova, node); 64 cached_iova = container_of(curr, struct iova, node);
65 65
66 if (free->pfn_lo >= cached_iova->pfn_lo) 66 if (free->pfn_lo >= cached_iova->pfn_lo) {
67 iovad->cached32_node = rb_next(&free->node); 67 struct rb_node *node = rb_next(&free->node);
68 struct iova *iova = container_of(node, struct iova, node);
69
70 /* only cache if it's below 32bit pfn */
71 if (node && iova->pfn_lo < iovad->dma_32bit_pfn)
72 iovad->cached32_node = node;
73 else
74 iovad->cached32_node = NULL;
75 }
68} 76}
69 77
70/* Computes the padding size required, to make the 78/* Computes the padding size required, to make the
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 7c3b18e78cee..d36f41ea8cbf 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -195,6 +195,8 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
195 return PCI_D2; 195 return PCI_D2;
196 case ACPI_STATE_D3: 196 case ACPI_STATE_D3:
197 return PCI_D3hot; 197 return PCI_D3hot;
198 case ACPI_STATE_D3_COLD:
199 return PCI_D3cold;
198 } 200 }
199 return PCI_POWER_ERROR; 201 return PCI_POWER_ERROR;
200} 202}
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 135df164a4c1..46767c53917a 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -624,7 +624,7 @@ static int pci_pm_prepare(struct device *dev)
624 * system from the sleep state, we'll have to prevent it from signaling 624 * system from the sleep state, we'll have to prevent it from signaling
625 * wake-up. 625 * wake-up.
626 */ 626 */
627 pm_runtime_resume(dev); 627 pm_runtime_get_sync(dev);
628 628
629 if (drv && drv->pm && drv->pm->prepare) 629 if (drv && drv->pm && drv->pm->prepare)
630 error = drv->pm->prepare(dev); 630 error = drv->pm->prepare(dev);
@@ -638,6 +638,8 @@ static void pci_pm_complete(struct device *dev)
638 638
639 if (drv && drv->pm && drv->pm->complete) 639 if (drv && drv->pm && drv->pm->complete)
640 drv->pm->complete(dev); 640 drv->pm->complete(dev);
641
642 pm_runtime_put_sync(dev);
641} 643}
642 644
643#else /* !CONFIG_PM_SLEEP */ 645#else /* !CONFIG_PM_SLEEP */
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index f8deb3e380a2..7bcf12adced7 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -108,6 +108,40 @@ static ssize_t local_cpulist_show(struct device *dev,
108 return len; 108 return len;
109} 109}
110 110
111/*
112 * PCI Bus Class Devices
113 */
114static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
115 int type,
116 struct device_attribute *attr,
117 char *buf)
118{
119 int ret;
120 const struct cpumask *cpumask;
121
122 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
123 ret = type ?
124 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
125 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
126 buf[ret++] = '\n';
127 buf[ret] = '\0';
128 return ret;
129}
130
131static inline ssize_t pci_bus_show_cpumaskaffinity(struct device *dev,
132 struct device_attribute *attr,
133 char *buf)
134{
135 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
136}
137
138static inline ssize_t pci_bus_show_cpulistaffinity(struct device *dev,
139 struct device_attribute *attr,
140 char *buf)
141{
142 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
143}
144
111/* show resources */ 145/* show resources */
112static ssize_t 146static ssize_t
113resource_show(struct device * dev, struct device_attribute *attr, char * buf) 147resource_show(struct device * dev, struct device_attribute *attr, char * buf)
@@ -318,6 +352,25 @@ remove_store(struct device *dev, struct device_attribute *dummy,
318 count = ret; 352 count = ret;
319 return count; 353 return count;
320} 354}
355
356static ssize_t
357dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
358 const char *buf, size_t count)
359{
360 unsigned long val;
361 struct pci_bus *bus = to_pci_bus(dev);
362
363 if (strict_strtoul(buf, 0, &val) < 0)
364 return -EINVAL;
365
366 if (val) {
367 mutex_lock(&pci_remove_rescan_mutex);
368 pci_rescan_bus(bus);
369 mutex_unlock(&pci_remove_rescan_mutex);
370 }
371 return count;
372}
373
321#endif 374#endif
322 375
323struct device_attribute pci_dev_attrs[] = { 376struct device_attribute pci_dev_attrs[] = {
@@ -347,6 +400,15 @@ struct device_attribute pci_dev_attrs[] = {
347 __ATTR_NULL, 400 __ATTR_NULL,
348}; 401};
349 402
403struct device_attribute pcibus_dev_attrs[] = {
404#ifdef CONFIG_HOTPLUG
405 __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store),
406#endif
407 __ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL),
408 __ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL),
409 __ATTR_NULL,
410};
411
350static ssize_t 412static ssize_t
351boot_vga_show(struct device *dev, struct device_attribute *attr, char *buf) 413boot_vga_show(struct device *dev, struct device_attribute *attr, char *buf)
352{ 414{
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 2472e7177b4b..692671b11667 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -830,7 +830,7 @@ static int pci_save_pcie_state(struct pci_dev *dev)
830 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 830 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
831 return -ENOMEM; 831 return -ENOMEM;
832 } 832 }
833 cap = (u16 *)&save_state->data[0]; 833 cap = (u16 *)&save_state->cap.data[0];
834 834
835 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 835 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
836 836
@@ -863,7 +863,7 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
864 if (!save_state || pos <= 0) 864 if (!save_state || pos <= 0)
865 return; 865 return;
866 cap = (u16 *)&save_state->data[0]; 866 cap = (u16 *)&save_state->cap.data[0];
867 867
868 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 868 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
869 869
@@ -899,7 +899,8 @@ static int pci_save_pcix_state(struct pci_dev *dev)
899 return -ENOMEM; 899 return -ENOMEM;
900 } 900 }
901 901
902 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); 902 pci_read_config_word(dev, pos + PCI_X_CMD,
903 (u16 *)save_state->cap.data);
903 904
904 return 0; 905 return 0;
905} 906}
@@ -914,7 +915,7 @@ static void pci_restore_pcix_state(struct pci_dev *dev)
914 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 915 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
915 if (!save_state || pos <= 0) 916 if (!save_state || pos <= 0)
916 return; 917 return;
917 cap = (u16 *)&save_state->data[0]; 918 cap = (u16 *)&save_state->cap.data[0];
918 919
919 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 920 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
920} 921}
@@ -975,6 +976,104 @@ void pci_restore_state(struct pci_dev *dev)
975 dev->state_saved = false; 976 dev->state_saved = false;
976} 977}
977 978
979struct pci_saved_state {
980 u32 config_space[16];
981 struct pci_cap_saved_data cap[0];
982};
983
984/**
985 * pci_store_saved_state - Allocate and return an opaque struct containing
986 * the device saved state.
987 * @dev: PCI device that we're dealing with
988 *
989 * Rerturn NULL if no state or error.
990 */
991struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
992{
993 struct pci_saved_state *state;
994 struct pci_cap_saved_state *tmp;
995 struct pci_cap_saved_data *cap;
996 struct hlist_node *pos;
997 size_t size;
998
999 if (!dev->state_saved)
1000 return NULL;
1001
1002 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1003
1004 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1005 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1006
1007 state = kzalloc(size, GFP_KERNEL);
1008 if (!state)
1009 return NULL;
1010
1011 memcpy(state->config_space, dev->saved_config_space,
1012 sizeof(state->config_space));
1013
1014 cap = state->cap;
1015 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1016 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1017 memcpy(cap, &tmp->cap, len);
1018 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1019 }
1020 /* Empty cap_save terminates list */
1021
1022 return state;
1023}
1024EXPORT_SYMBOL_GPL(pci_store_saved_state);
1025
1026/**
1027 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1028 * @dev: PCI device that we're dealing with
1029 * @state: Saved state returned from pci_store_saved_state()
1030 */
1031int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1032{
1033 struct pci_cap_saved_data *cap;
1034
1035 dev->state_saved = false;
1036
1037 if (!state)
1038 return 0;
1039
1040 memcpy(dev->saved_config_space, state->config_space,
1041 sizeof(state->config_space));
1042
1043 cap = state->cap;
1044 while (cap->size) {
1045 struct pci_cap_saved_state *tmp;
1046
1047 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1048 if (!tmp || tmp->cap.size != cap->size)
1049 return -EINVAL;
1050
1051 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1052 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1053 sizeof(struct pci_cap_saved_data) + cap->size);
1054 }
1055
1056 dev->state_saved = true;
1057 return 0;
1058}
1059EXPORT_SYMBOL_GPL(pci_load_saved_state);
1060
1061/**
1062 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1063 * and free the memory allocated for it.
1064 * @dev: PCI device that we're dealing with
1065 * @state: Pointer to saved state returned from pci_store_saved_state()
1066 */
1067int pci_load_and_free_saved_state(struct pci_dev *dev,
1068 struct pci_saved_state **state)
1069{
1070 int ret = pci_load_saved_state(dev, *state);
1071 kfree(*state);
1072 *state = NULL;
1073 return ret;
1074}
1075EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1076
978static int do_pci_enable_device(struct pci_dev *dev, int bars) 1077static int do_pci_enable_device(struct pci_dev *dev, int bars)
979{ 1078{
980 int err; 1079 int err;
@@ -1771,7 +1870,8 @@ static int pci_add_cap_save_buffer(
1771 if (!save_state) 1870 if (!save_state)
1772 return -ENOMEM; 1871 return -ENOMEM;
1773 1872
1774 save_state->cap_nr = cap; 1873 save_state->cap.cap_nr = cap;
1874 save_state->cap.size = size;
1775 pci_add_saved_cap(dev, save_state); 1875 pci_add_saved_cap(dev, save_state);
1776 1876
1777 return 0; 1877 return 0;
@@ -1834,6 +1934,300 @@ void pci_enable_ari(struct pci_dev *dev)
1834 bridge->ari_enabled = 1; 1934 bridge->ari_enabled = 1;
1835} 1935}
1836 1936
1937/**
1938 * pci_enable_ido - enable ID-based ordering on a device
1939 * @dev: the PCI device
1940 * @type: which types of IDO to enable
1941 *
1942 * Enable ID-based ordering on @dev. @type can contain the bits
1943 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1944 * which types of transactions are allowed to be re-ordered.
1945 */
1946void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1947{
1948 int pos;
1949 u16 ctrl;
1950
1951 pos = pci_pcie_cap(dev);
1952 if (!pos)
1953 return;
1954
1955 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1956 if (type & PCI_EXP_IDO_REQUEST)
1957 ctrl |= PCI_EXP_IDO_REQ_EN;
1958 if (type & PCI_EXP_IDO_COMPLETION)
1959 ctrl |= PCI_EXP_IDO_CMP_EN;
1960 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1961}
1962EXPORT_SYMBOL(pci_enable_ido);
1963
1964/**
1965 * pci_disable_ido - disable ID-based ordering on a device
1966 * @dev: the PCI device
1967 * @type: which types of IDO to disable
1968 */
1969void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1970{
1971 int pos;
1972 u16 ctrl;
1973
1974 if (!pci_is_pcie(dev))
1975 return;
1976
1977 pos = pci_pcie_cap(dev);
1978 if (!pos)
1979 return;
1980
1981 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1982 if (type & PCI_EXP_IDO_REQUEST)
1983 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1984 if (type & PCI_EXP_IDO_COMPLETION)
1985 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1986 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1987}
1988EXPORT_SYMBOL(pci_disable_ido);
1989
1990/**
1991 * pci_enable_obff - enable optimized buffer flush/fill
1992 * @dev: PCI device
1993 * @type: type of signaling to use
1994 *
1995 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
1996 * signaling if possible, falling back to message signaling only if
1997 * WAKE# isn't supported. @type should indicate whether the PCIe link
1998 * be brought out of L0s or L1 to send the message. It should be either
1999 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2000 *
2001 * If your device can benefit from receiving all messages, even at the
2002 * power cost of bringing the link back up from a low power state, use
2003 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2004 * preferred type).
2005 *
2006 * RETURNS:
2007 * Zero on success, appropriate error number on failure.
2008 */
2009int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2010{
2011 int pos;
2012 u32 cap;
2013 u16 ctrl;
2014 int ret;
2015
2016 if (!pci_is_pcie(dev))
2017 return -ENOTSUPP;
2018
2019 pos = pci_pcie_cap(dev);
2020 if (!pos)
2021 return -ENOTSUPP;
2022
2023 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2024 if (!(cap & PCI_EXP_OBFF_MASK))
2025 return -ENOTSUPP; /* no OBFF support at all */
2026
2027 /* Make sure the topology supports OBFF as well */
2028 if (dev->bus) {
2029 ret = pci_enable_obff(dev->bus->self, type);
2030 if (ret)
2031 return ret;
2032 }
2033
2034 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2035 if (cap & PCI_EXP_OBFF_WAKE)
2036 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2037 else {
2038 switch (type) {
2039 case PCI_EXP_OBFF_SIGNAL_L0:
2040 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2041 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2042 break;
2043 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2044 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2045 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2046 break;
2047 default:
2048 WARN(1, "bad OBFF signal type\n");
2049 return -ENOTSUPP;
2050 }
2051 }
2052 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2053
2054 return 0;
2055}
2056EXPORT_SYMBOL(pci_enable_obff);
2057
2058/**
2059 * pci_disable_obff - disable optimized buffer flush/fill
2060 * @dev: PCI device
2061 *
2062 * Disable OBFF on @dev.
2063 */
2064void pci_disable_obff(struct pci_dev *dev)
2065{
2066 int pos;
2067 u16 ctrl;
2068
2069 if (!pci_is_pcie(dev))
2070 return;
2071
2072 pos = pci_pcie_cap(dev);
2073 if (!pos)
2074 return;
2075
2076 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2077 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2078 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2079}
2080EXPORT_SYMBOL(pci_disable_obff);
2081
2082/**
2083 * pci_ltr_supported - check whether a device supports LTR
2084 * @dev: PCI device
2085 *
2086 * RETURNS:
2087 * True if @dev supports latency tolerance reporting, false otherwise.
2088 */
2089bool pci_ltr_supported(struct pci_dev *dev)
2090{
2091 int pos;
2092 u32 cap;
2093
2094 if (!pci_is_pcie(dev))
2095 return false;
2096
2097 pos = pci_pcie_cap(dev);
2098 if (!pos)
2099 return false;
2100
2101 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2102
2103 return cap & PCI_EXP_DEVCAP2_LTR;
2104}
2105EXPORT_SYMBOL(pci_ltr_supported);
2106
2107/**
2108 * pci_enable_ltr - enable latency tolerance reporting
2109 * @dev: PCI device
2110 *
2111 * Enable LTR on @dev if possible, which means enabling it first on
2112 * upstream ports.
2113 *
2114 * RETURNS:
2115 * Zero on success, errno on failure.
2116 */
2117int pci_enable_ltr(struct pci_dev *dev)
2118{
2119 int pos;
2120 u16 ctrl;
2121 int ret;
2122
2123 if (!pci_ltr_supported(dev))
2124 return -ENOTSUPP;
2125
2126 pos = pci_pcie_cap(dev);
2127 if (!pos)
2128 return -ENOTSUPP;
2129
2130 /* Only primary function can enable/disable LTR */
2131 if (PCI_FUNC(dev->devfn) != 0)
2132 return -EINVAL;
2133
2134 /* Enable upstream ports first */
2135 if (dev->bus) {
2136 ret = pci_enable_ltr(dev->bus->self);
2137 if (ret)
2138 return ret;
2139 }
2140
2141 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2142 ctrl |= PCI_EXP_LTR_EN;
2143 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2144
2145 return 0;
2146}
2147EXPORT_SYMBOL(pci_enable_ltr);
2148
2149/**
2150 * pci_disable_ltr - disable latency tolerance reporting
2151 * @dev: PCI device
2152 */
2153void pci_disable_ltr(struct pci_dev *dev)
2154{
2155 int pos;
2156 u16 ctrl;
2157
2158 if (!pci_ltr_supported(dev))
2159 return;
2160
2161 pos = pci_pcie_cap(dev);
2162 if (!pos)
2163 return;
2164
2165 /* Only primary function can enable/disable LTR */
2166 if (PCI_FUNC(dev->devfn) != 0)
2167 return;
2168
2169 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2170 ctrl &= ~PCI_EXP_LTR_EN;
2171 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2172}
2173EXPORT_SYMBOL(pci_disable_ltr);
2174
2175static int __pci_ltr_scale(int *val)
2176{
2177 int scale = 0;
2178
2179 while (*val > 1023) {
2180 *val = (*val + 31) / 32;
2181 scale++;
2182 }
2183 return scale;
2184}
2185
2186/**
2187 * pci_set_ltr - set LTR latency values
2188 * @dev: PCI device
2189 * @snoop_lat_ns: snoop latency in nanoseconds
2190 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2191 *
2192 * Figure out the scale and set the LTR values accordingly.
2193 */
2194int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2195{
2196 int pos, ret, snoop_scale, nosnoop_scale;
2197 u16 val;
2198
2199 if (!pci_ltr_supported(dev))
2200 return -ENOTSUPP;
2201
2202 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2203 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2204
2205 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2206 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2207 return -EINVAL;
2208
2209 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2210 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2211 return -EINVAL;
2212
2213 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2214 if (!pos)
2215 return -ENOTSUPP;
2216
2217 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2218 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2219 if (ret != 4)
2220 return -EIO;
2221
2222 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2223 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2224 if (ret != 4)
2225 return -EIO;
2226
2227 return 0;
2228}
2229EXPORT_SYMBOL(pci_set_ltr);
2230
1837static int pci_acs_enable; 2231static int pci_acs_enable;
1838 2232
1839/** 2233/**
@@ -2479,6 +2873,21 @@ clear:
2479 return 0; 2873 return 0;
2480} 2874}
2481 2875
2876/**
2877 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2878 * @dev: Device to reset.
2879 * @probe: If set, only check if the device can be reset this way.
2880 *
2881 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2882 * unset, it will be reinitialized internally when going from PCI_D3hot to
2883 * PCI_D0. If that's the case and the device is not in a low-power state
2884 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2885 *
2886 * NOTE: This causes the caller to sleep for twice the device power transition
2887 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2888 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2889 * Moreover, only devices in D0 can be reset by this function.
2890 */
2482static int pci_pm_reset(struct pci_dev *dev, int probe) 2891static int pci_pm_reset(struct pci_dev *dev, int probe)
2483{ 2892{
2484 u16 csr; 2893 u16 csr;
@@ -2862,11 +3271,11 @@ void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2862} 3271}
2863 3272
2864static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 3273static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2865 unsigned int command_bits, bool change_bridge) 3274 unsigned int command_bits, u32 flags)
2866{ 3275{
2867 if (arch_set_vga_state) 3276 if (arch_set_vga_state)
2868 return arch_set_vga_state(dev, decode, command_bits, 3277 return arch_set_vga_state(dev, decode, command_bits,
2869 change_bridge); 3278 flags);
2870 return 0; 3279 return 0;
2871} 3280}
2872 3281
@@ -2875,31 +3284,34 @@ static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2875 * @dev: the PCI device 3284 * @dev: the PCI device
2876 * @decode: true = enable decoding, false = disable decoding 3285 * @decode: true = enable decoding, false = disable decoding
2877 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 3286 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2878 * @change_bridge: traverse ancestors and change bridges 3287 * @flags: traverse ancestors and change bridges
3288 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
2879 */ 3289 */
2880int pci_set_vga_state(struct pci_dev *dev, bool decode, 3290int pci_set_vga_state(struct pci_dev *dev, bool decode,
2881 unsigned int command_bits, bool change_bridge) 3291 unsigned int command_bits, u32 flags)
2882{ 3292{
2883 struct pci_bus *bus; 3293 struct pci_bus *bus;
2884 struct pci_dev *bridge; 3294 struct pci_dev *bridge;
2885 u16 cmd; 3295 u16 cmd;
2886 int rc; 3296 int rc;
2887 3297
2888 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); 3298 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
2889 3299
2890 /* ARCH specific VGA enables */ 3300 /* ARCH specific VGA enables */
2891 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge); 3301 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
2892 if (rc) 3302 if (rc)
2893 return rc; 3303 return rc;
2894 3304
2895 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3305 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
2896 if (decode == true) 3306 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2897 cmd |= command_bits; 3307 if (decode == true)
2898 else 3308 cmd |= command_bits;
2899 cmd &= ~command_bits; 3309 else
2900 pci_write_config_word(dev, PCI_COMMAND, cmd); 3310 cmd &= ~command_bits;
3311 pci_write_config_word(dev, PCI_COMMAND, cmd);
3312 }
2901 3313
2902 if (change_bridge == false) 3314 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
2903 return 0; 3315 return 0;
2904 3316
2905 bus = dev->bus; 3317 bus = dev->bus;
@@ -3071,6 +3483,8 @@ static int __init pci_setup(char *str)
3071 pci_no_msi(); 3483 pci_no_msi();
3072 } else if (!strcmp(str, "noaer")) { 3484 } else if (!strcmp(str, "noaer")) {
3073 pci_no_aer(); 3485 pci_no_aer();
3486 } else if (!strncmp(str, "realloc", 7)) {
3487 pci_realloc();
3074 } else if (!strcmp(str, "nodomains")) { 3488 } else if (!strcmp(str, "nodomains")) {
3075 pci_no_domains(); 3489 pci_no_domains();
3076 } else if (!strncmp(str, "cbiosize=", 9)) { 3490 } else if (!strncmp(str, "cbiosize=", 9)) {
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index a6ec200fe5ee..3a39bf1f1e2c 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -146,6 +146,8 @@ static inline void pci_no_msi(void) { }
146static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } 146static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
147#endif 147#endif
148 148
149extern void pci_realloc(void);
150
149static inline int pci_no_d1d2(struct pci_dev *dev) 151static inline int pci_no_d1d2(struct pci_dev *dev)
150{ 152{
151 unsigned int parent_dstates = 0; 153 unsigned int parent_dstates = 0;
@@ -156,8 +158,7 @@ static inline int pci_no_d1d2(struct pci_dev *dev)
156 158
157} 159}
158extern struct device_attribute pci_dev_attrs[]; 160extern struct device_attribute pci_dev_attrs[];
159extern struct device_attribute dev_attr_cpuaffinity; 161extern struct device_attribute pcibus_dev_attrs[];
160extern struct device_attribute dev_attr_cpulistaffinity;
161#ifdef CONFIG_HOTPLUG 162#ifdef CONFIG_HOTPLUG
162extern struct bus_attribute pci_bus_attrs[]; 163extern struct bus_attribute pci_bus_attrs[];
163#else 164#else
@@ -250,15 +251,6 @@ struct pci_sriov {
250 u8 __iomem *mstate; /* VF Migration State Array */ 251 u8 __iomem *mstate; /* VF Migration State Array */
251}; 252};
252 253
253/* Address Translation Service */
254struct pci_ats {
255 int pos; /* capability position */
256 int stu; /* Smallest Translation Unit */
257 int qdep; /* Invalidate Queue Depth */
258 int ref_cnt; /* Physical Function reference count */
259 unsigned int is_enabled:1; /* Enable bit is set */
260};
261
262#ifdef CONFIG_PCI_IOV 254#ifdef CONFIG_PCI_IOV
263extern int pci_iov_init(struct pci_dev *dev); 255extern int pci_iov_init(struct pci_dev *dev);
264extern void pci_iov_release(struct pci_dev *dev); 256extern void pci_iov_release(struct pci_dev *dev);
@@ -269,19 +261,6 @@ extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
269extern void pci_restore_iov_state(struct pci_dev *dev); 261extern void pci_restore_iov_state(struct pci_dev *dev);
270extern int pci_iov_bus_range(struct pci_bus *bus); 262extern int pci_iov_bus_range(struct pci_bus *bus);
271 263
272extern int pci_enable_ats(struct pci_dev *dev, int ps);
273extern void pci_disable_ats(struct pci_dev *dev);
274extern int pci_ats_queue_depth(struct pci_dev *dev);
275/**
276 * pci_ats_enabled - query the ATS status
277 * @dev: the PCI device
278 *
279 * Returns 1 if ATS capability is enabled, or 0 if not.
280 */
281static inline int pci_ats_enabled(struct pci_dev *dev)
282{
283 return dev->ats && dev->ats->is_enabled;
284}
285#else 264#else
286static inline int pci_iov_init(struct pci_dev *dev) 265static inline int pci_iov_init(struct pci_dev *dev)
287{ 266{
@@ -304,21 +283,6 @@ static inline int pci_iov_bus_range(struct pci_bus *bus)
304 return 0; 283 return 0;
305} 284}
306 285
307static inline int pci_enable_ats(struct pci_dev *dev, int ps)
308{
309 return -ENODEV;
310}
311static inline void pci_disable_ats(struct pci_dev *dev)
312{
313}
314static inline int pci_ats_queue_depth(struct pci_dev *dev)
315{
316 return -ENODEV;
317}
318static inline int pci_ats_enabled(struct pci_dev *dev)
319{
320 return 0;
321}
322#endif /* CONFIG_PCI_IOV */ 286#endif /* CONFIG_PCI_IOV */
323 287
324static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 288static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index f62079ff06dd..95489cd9a555 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -326,7 +326,7 @@ static int aer_inject(struct aer_error_inj *einj)
326 unsigned long flags; 326 unsigned long flags;
327 unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn); 327 unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
328 int pos_cap_err, rp_pos_cap_err; 328 int pos_cap_err, rp_pos_cap_err;
329 u32 sever, cor_mask, uncor_mask, cor_mask_orig, uncor_mask_orig; 329 u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
330 int ret = 0; 330 int ret = 0;
331 331
332 dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn); 332 dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn);
diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h
index 3eb77080366a..94a7598eb262 100644
--- a/drivers/pci/pcie/aer/aerdrv.h
+++ b/drivers/pci/pcie/aer/aerdrv.h
@@ -114,15 +114,6 @@ extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
114extern void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info); 114extern void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info);
115extern irqreturn_t aer_irq(int irq, void *context); 115extern irqreturn_t aer_irq(int irq, void *context);
116 116
117#ifdef CONFIG_ACPI
118extern int aer_osc_setup(struct pcie_device *pciedev);
119#else
120static inline int aer_osc_setup(struct pcie_device *pciedev)
121{
122 return 0;
123}
124#endif
125
126#ifdef CONFIG_ACPI_APEI 117#ifdef CONFIG_ACPI_APEI
127extern int pcie_aer_get_firmware_first(struct pci_dev *pci_dev); 118extern int pcie_aer_get_firmware_first(struct pci_dev *pci_dev);
128#else 119#else
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index eee09f756ec9..6892601fc76f 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -608,7 +608,7 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
608 * the BIOS's expectation, we'll do so once pci_enable_device() is 608 * the BIOS's expectation, we'll do so once pci_enable_device() is
609 * called. 609 * called.
610 */ 610 */
611 if (aspm_policy != POLICY_POWERSAVE) { 611 if (aspm_policy != POLICY_POWERSAVE || aspm_clear_state) {
612 pcie_config_aspm_path(link); 612 pcie_config_aspm_path(link);
613 pcie_set_clkpm(link, policy_to_clkpm_state(link)); 613 pcie_set_clkpm(link, policy_to_clkpm_state(link));
614 } 614 }
@@ -734,7 +734,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
734 * pci_disable_link_state - disable pci device's link state, so the link will 734 * pci_disable_link_state - disable pci device's link state, so the link will
735 * never enter specific states 735 * never enter specific states
736 */ 736 */
737void pci_disable_link_state(struct pci_dev *pdev, int state) 737static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
738{ 738{
739 struct pci_dev *parent = pdev->bus->self; 739 struct pci_dev *parent = pdev->bus->self;
740 struct pcie_link_state *link; 740 struct pcie_link_state *link;
@@ -747,7 +747,8 @@ void pci_disable_link_state(struct pci_dev *pdev, int state)
747 if (!parent || !parent->link_state) 747 if (!parent || !parent->link_state)
748 return; 748 return;
749 749
750 down_read(&pci_bus_sem); 750 if (sem)
751 down_read(&pci_bus_sem);
751 mutex_lock(&aspm_lock); 752 mutex_lock(&aspm_lock);
752 link = parent->link_state; 753 link = parent->link_state;
753 if (state & PCIE_LINK_STATE_L0S) 754 if (state & PCIE_LINK_STATE_L0S)
@@ -761,7 +762,19 @@ void pci_disable_link_state(struct pci_dev *pdev, int state)
761 pcie_set_clkpm(link, 0); 762 pcie_set_clkpm(link, 0);
762 } 763 }
763 mutex_unlock(&aspm_lock); 764 mutex_unlock(&aspm_lock);
764 up_read(&pci_bus_sem); 765 if (sem)
766 up_read(&pci_bus_sem);
767}
768
769void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
770{
771 __pci_disable_link_state(pdev, state, false);
772}
773EXPORT_SYMBOL(pci_disable_link_state_locked);
774
775void pci_disable_link_state(struct pci_dev *pdev, int state)
776{
777 __pci_disable_link_state(pdev, state, true);
765} 778}
766EXPORT_SYMBOL(pci_disable_link_state); 779EXPORT_SYMBOL(pci_disable_link_state);
767 780
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 44cbbbaa499d..bafb3c3d4a89 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -43,43 +43,6 @@ int no_pci_devices(void)
43EXPORT_SYMBOL(no_pci_devices); 43EXPORT_SYMBOL(no_pci_devices);
44 44
45/* 45/*
46 * PCI Bus Class Devices
47 */
48static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
49 int type,
50 struct device_attribute *attr,
51 char *buf)
52{
53 int ret;
54 const struct cpumask *cpumask;
55
56 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
57 ret = type?
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
60 buf[ret++] = '\n';
61 buf[ret] = '\0';
62 return ret;
63}
64
65static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
67 char *buf)
68{
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
70}
71
72static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
74 char *buf)
75{
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
77}
78
79DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
81
82/*
83 * PCI Bus Class 46 * PCI Bus Class
84 */ 47 */
85static void release_pcibus_dev(struct device *dev) 48static void release_pcibus_dev(struct device *dev)
@@ -95,6 +58,7 @@ static void release_pcibus_dev(struct device *dev)
95static struct class pcibus_class = { 58static struct class pcibus_class = {
96 .name = "pci_bus", 59 .name = "pci_bus",
97 .dev_release = &release_pcibus_dev, 60 .dev_release = &release_pcibus_dev,
61 .dev_attrs = pcibus_dev_attrs,
98}; 62};
99 63
100static int __init pcibus_class_init(void) 64static int __init pcibus_class_init(void)
@@ -204,7 +168,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
204 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 168 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
205 if (type == pci_bar_io) { 169 if (type == pci_bar_io) {
206 l &= PCI_BASE_ADDRESS_IO_MASK; 170 l &= PCI_BASE_ADDRESS_IO_MASK;
207 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; 171 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
208 } else { 172 } else {
209 l &= PCI_BASE_ADDRESS_MEM_MASK; 173 l &= PCI_BASE_ADDRESS_MEM_MASK;
210 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 174 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
@@ -1455,9 +1419,6 @@ struct pci_bus * pci_create_bus(struct device *parent,
1455 error = device_register(&b->dev); 1419 error = device_register(&b->dev);
1456 if (error) 1420 if (error)
1457 goto class_dev_reg_err; 1421 goto class_dev_reg_err;
1458 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1459 if (error)
1460 goto dev_create_file_err;
1461 1422
1462 /* Create legacy_io and legacy_mem files for this bus */ 1423 /* Create legacy_io and legacy_mem files for this bus */
1463 pci_create_legacy_files(b); 1424 pci_create_legacy_files(b);
@@ -1468,8 +1429,6 @@ struct pci_bus * pci_create_bus(struct device *parent,
1468 1429
1469 return b; 1430 return b;
1470 1431
1471dev_create_file_err:
1472 device_unregister(&b->dev);
1473class_dev_reg_err: 1432class_dev_reg_err:
1474 device_unregister(dev); 1433 device_unregister(dev);
1475dev_reg_err: 1434dev_reg_err:
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 5129ed6d8fa7..02145e9697a9 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -606,7 +606,7 @@ static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
606 } 606 }
607 607
608 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 608 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
609 if (enable & ICH4_GPIO_EN) { 609 if (enable & ICH6_GPIO_EN) {
610 pci_read_config_dword(dev, ICH6_GPIOBASE, &region); 610 pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
611 region &= PCI_BASE_ADDRESS_IO_MASK; 611 region &= PCI_BASE_ADDRESS_IO_MASK;
612 if (region >= PCIBIOS_MIN_IO) 612 if (region >= PCIBIOS_MIN_IO)
@@ -681,7 +681,7 @@ static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
681/* ICH7-10 has the same common LPC generic IO decode registers */ 681/* ICH7-10 has the same common LPC generic IO decode registers */
682static void __devinit quirk_ich7_lpc(struct pci_dev *dev) 682static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
683{ 683{
684 /* We share the common ACPI/DPIO decode with ICH6 */ 684 /* We share the common ACPI/GPIO decode with ICH6 */
685 ich6_lpc_acpi_gpio(dev); 685 ich6_lpc_acpi_gpio(dev);
686 686
687 /* And have 4 ICH7+ generic decodes */ 687 /* And have 4 ICH7+ generic decodes */
@@ -2349,8 +2349,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2349 */ 2349 */
2350static void __devinit nvenet_msi_disable(struct pci_dev *dev) 2350static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2351{ 2351{
2352 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") || 2352 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2353 dmi_name_in_vendors("P5N32-E SLI")) { 2353
2354 if (board_name &&
2355 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2356 strstr(board_name, "P5N32-E SLI"))) {
2354 dev_info(&dev->dev, 2357 dev_info(&dev->dev,
2355 "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2358 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2356 dev->no_msi = 1; 2359 dev->no_msi = 1;
@@ -2758,6 +2761,8 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2758} 2761}
2759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2762DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2760DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2763DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2764DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2765DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2761#endif /*CONFIG_MMC_RICOH_MMC*/ 2766#endif /*CONFIG_MMC_RICOH_MMC*/
2762 2767
2763#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP) 2768#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
@@ -2784,6 +2789,16 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2784DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2789DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2785#endif 2790#endif
2786 2791
2792static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2793{
2794 /* TI 816x devices do not have class code set when in PCIe boot mode */
2795 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2796 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2797 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2798 }
2799}
2800DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2801
2787static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2802static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2788 struct pci_fixup *end) 2803 struct pci_fixup *end)
2789{ 2804{
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 176615e7231f..7f87beed35ac 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -73,8 +73,6 @@ void pci_remove_bus(struct pci_bus *pci_bus)
73 return; 73 return;
74 74
75 pci_remove_legacy_files(pci_bus); 75 pci_remove_legacy_files(pci_bus);
76 device_remove_file(&pci_bus->dev, &dev_attr_cpuaffinity);
77 device_remove_file(&pci_bus->dev, &dev_attr_cpulistaffinity);
78 device_unregister(&pci_bus->dev); 76 device_unregister(&pci_bus->dev);
79} 77}
80EXPORT_SYMBOL(pci_remove_bus); 78EXPORT_SYMBOL(pci_remove_bus);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index a806cb321d2e..9995842e45b5 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -47,6 +47,13 @@ struct resource_list_x {
47 (head)->next = NULL; \ 47 (head)->next = NULL; \
48} while (0) 48} while (0)
49 49
50int pci_realloc_enable = 0;
51#define pci_realloc_enabled() pci_realloc_enable
52void pci_realloc(void)
53{
54 pci_realloc_enable = 1;
55}
56
50/** 57/**
51 * add_to_list() - add a new resource tracker to the list 58 * add_to_list() - add a new resource tracker to the list
52 * @head: Head of the list 59 * @head: Head of the list
@@ -991,30 +998,147 @@ static void pci_bus_dump_resources(struct pci_bus *bus)
991 } 998 }
992} 999}
993 1000
1001static int __init pci_bus_get_depth(struct pci_bus *bus)
1002{
1003 int depth = 0;
1004 struct pci_dev *dev;
1005
1006 list_for_each_entry(dev, &bus->devices, bus_list) {
1007 int ret;
1008 struct pci_bus *b = dev->subordinate;
1009 if (!b)
1010 continue;
1011
1012 ret = pci_bus_get_depth(b);
1013 if (ret + 1 > depth)
1014 depth = ret + 1;
1015 }
1016
1017 return depth;
1018}
1019static int __init pci_get_max_depth(void)
1020{
1021 int depth = 0;
1022 struct pci_bus *bus;
1023
1024 list_for_each_entry(bus, &pci_root_buses, node) {
1025 int ret;
1026
1027 ret = pci_bus_get_depth(bus);
1028 if (ret > depth)
1029 depth = ret;
1030 }
1031
1032 return depth;
1033}
1034
1035
1036/*
1037 * first try will not touch pci bridge res
1038 * second and later try will clear small leaf bridge res
1039 * will stop till to the max deepth if can not find good one
1040 */
994void __init 1041void __init
995pci_assign_unassigned_resources(void) 1042pci_assign_unassigned_resources(void)
996{ 1043{
997 struct pci_bus *bus; 1044 struct pci_bus *bus;
998 struct resource_list_x add_list; /* list of resources that 1045 struct resource_list_x add_list; /* list of resources that
999 want additional resources */ 1046 want additional resources */
1047 int tried_times = 0;
1048 enum release_type rel_type = leaf_only;
1049 struct resource_list_x head, *list;
1050 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1051 IORESOURCE_PREFETCH;
1052 unsigned long failed_type;
1053 int max_depth = pci_get_max_depth();
1054 int pci_try_num;
1055
1056
1057 head.next = NULL;
1000 add_list.next = NULL; 1058 add_list.next = NULL;
1059
1060 pci_try_num = max_depth + 1;
1061 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1062 max_depth, pci_try_num);
1063
1064again:
1001 /* Depth first, calculate sizes and alignments of all 1065 /* Depth first, calculate sizes and alignments of all
1002 subordinate buses. */ 1066 subordinate buses. */
1003 list_for_each_entry(bus, &pci_root_buses, node) { 1067 list_for_each_entry(bus, &pci_root_buses, node)
1004 __pci_bus_size_bridges(bus, &add_list); 1068 __pci_bus_size_bridges(bus, &add_list);
1005 }
1006 1069
1007 /* Depth last, allocate resources and update the hardware. */ 1070 /* Depth last, allocate resources and update the hardware. */
1008 list_for_each_entry(bus, &pci_root_buses, node) { 1071 list_for_each_entry(bus, &pci_root_buses, node)
1009 __pci_bus_assign_resources(bus, &add_list, NULL); 1072 __pci_bus_assign_resources(bus, &add_list, &head);
1010 pci_enable_bridges(bus);
1011 }
1012 BUG_ON(add_list.next); 1073 BUG_ON(add_list.next);
1074 tried_times++;
1075
1076 /* any device complain? */
1077 if (!head.next)
1078 goto enable_and_dump;
1079
1080 /* don't realloc if asked to do so */
1081 if (!pci_realloc_enabled()) {
1082 free_list(resource_list_x, &head);
1083 goto enable_and_dump;
1084 }
1085
1086 failed_type = 0;
1087 for (list = head.next; list;) {
1088 failed_type |= list->flags;
1089 list = list->next;
1090 }
1091 /*
1092 * io port are tight, don't try extra
1093 * or if reach the limit, don't want to try more
1094 */
1095 failed_type &= type_mask;
1096 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
1097 free_list(resource_list_x, &head);
1098 goto enable_and_dump;
1099 }
1100
1101 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1102 tried_times + 1);
1103
1104 /* third times and later will not check if it is leaf */
1105 if ((tried_times + 1) > 2)
1106 rel_type = whole_subtree;
1107
1108 /*
1109 * Try to release leaf bridge's resources that doesn't fit resource of
1110 * child device under that bridge
1111 */
1112 for (list = head.next; list;) {
1113 bus = list->dev->bus;
1114 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
1115 rel_type);
1116 list = list->next;
1117 }
1118 /* restore size and flags */
1119 for (list = head.next; list;) {
1120 struct resource *res = list->res;
1121
1122 res->start = list->start;
1123 res->end = list->end;
1124 res->flags = list->flags;
1125 if (list->dev->subordinate)
1126 res->flags = 0;
1127
1128 list = list->next;
1129 }
1130 free_list(resource_list_x, &head);
1131
1132 goto again;
1133
1134enable_and_dump:
1135 /* Depth last, update the hardware. */
1136 list_for_each_entry(bus, &pci_root_buses, node)
1137 pci_enable_bridges(bus);
1013 1138
1014 /* dump the resource on buses */ 1139 /* dump the resource on buses */
1015 list_for_each_entry(bus, &pci_root_buses, node) { 1140 list_for_each_entry(bus, &pci_root_buses, node)
1016 pci_bus_dump_resources(bus); 1141 pci_bus_dump_resources(bus);
1017 }
1018} 1142}
1019 1143
1020void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 1144void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-10 06:07:15 -0400