3 files changed, 45 insertions, 12 deletions

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 1b34fc56067e..c62d2f043397 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -333,13 +333,17 @@ pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
         if (platform_pci_choose_state) {
                 ret = platform_pci_choose_state(dev, state);
                 if (ret >= 0)
-                        state = ret;
+                        state.event = ret;
         }
-        switch (state) {
-        case 0: return PCI_D0;
-        case 3: return PCI_D3hot;
+
+        switch (state.event) {
+        case PM_EVENT_ON:
+                return PCI_D0;
+        case PM_EVENT_FREEZE:
+        case PM_EVENT_SUSPEND:
+                return PCI_D3hot;
         default:
-                printk("They asked me for state %d\n", state);
+                printk("They asked me for state %d\n", state.event);
                 BUG();
         }
         return PCI_D0;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index bb36bb69803f..140354a2aa72 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -422,6 +422,25 @@ static void __devinit quirk_via_ioapic(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic );
 
 /*
+ * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
+ * This leads to doubled level interrupt rates.
+ * Set this bit to get rid of cycle wastage.
+ * Otherwise uncritical.
+ */
+static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
+{
+        u8 misc_control2;
+#define BYPASS_APIC_DEASSERT 8
+
+        pci_read_config_byte(dev, 0x5B, &misc_control2);
+        if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
+                printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
+                pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
+        }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
+
+/*
  * The AMD io apic can hang the box when an apic irq is masked.
  * We check all revs >= B0 (yet not in the pre production!) as the bug
  * is currently marked NoFix
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index 713c78f3a65d..49bd21702314 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -21,13 +21,21 @@
  * between the ROM and other resources, so enabling it may disable access
  * to MMIO registers or other card memory.
  */
-static void pci_enable_rom(struct pci_dev *pdev)
+static int pci_enable_rom(struct pci_dev *pdev)
 {
+        struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
+        struct pci_bus_region region;
         u32 rom_addr;
 
+        if (!res->flags)
+                return -1;
+
+        pcibios_resource_to_bus(pdev, &region, res);
         pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
-        rom_addr |= PCI_ROM_ADDRESS_ENABLE;
+        rom_addr &= ~PCI_ROM_ADDRESS_MASK;
+        rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
         pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
+        return 0;
 }
 
 /**
@@ -71,19 +79,21 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
         } else {
                 if (res->flags & IORESOURCE_ROM_COPY) {
                         *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
-                        return (void __iomem *)pci_resource_start(pdev, PCI_ROM_RESOURCE);
+                        return (void __iomem *)pci_resource_start(pdev,
+                                                             PCI_ROM_RESOURCE);
                 } else {
                         /* assign the ROM an address if it doesn't have one */
-                        if (res->parent == NULL)
-                                pci_assign_resource(pdev, PCI_ROM_RESOURCE);
-
+                        if (res->parent == NULL &&
+                            pci_assign_resource(pdev,PCI_ROM_RESOURCE))
+                                return NULL;
                         start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
                         *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
                         if (*size == 0)
                                 return NULL;
 
                         /* Enable ROM space decodes */
-                        pci_enable_rom(pdev);
+                        if (pci_enable_rom(pdev))
+                                return NULL;
                 }
         }