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-rw-r--r--drivers/pci/access.c12
-rw-r--r--drivers/pci/bus.c11
-rw-r--r--drivers/pci/host-bridge.c1
-rw-r--r--drivers/pci/host/Kconfig13
-rw-r--r--drivers/pci/host/Makefile2
-rw-r--r--drivers/pci/host/pci-exynos.c8
-rw-r--r--drivers/pci/host/pci-host-generic.c388
-rw-r--r--drivers/pci/host/pci-imx6.c1
-rw-r--r--drivers/pci/host/pci-mvebu.c102
-rw-r--r--drivers/pci/host/pci-rcar-gen2.c39
-rw-r--r--drivers/pci/host/pci-tegra.c7
-rw-r--r--drivers/pci/host/pcie-designware.c26
-rw-r--r--drivers/pci/host/pcie-designware.h1
-rw-r--r--drivers/pci/host/pcie-rcar.c1008
-rw-r--r--drivers/pci/hotplug-pci.c2
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c6
-rw-r--r--drivers/pci/hotplug/cpci_hotplug_pci.c5
-rw-r--r--drivers/pci/hotplug/cpqphp_ctrl.c3
-rw-r--r--drivers/pci/hotplug/cpqphp_nvram.c1
-rw-r--r--drivers/pci/hotplug/pciehp.h2
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c2
-rw-r--r--drivers/pci/hotplug/pciehp_pci.c3
-rw-r--r--drivers/pci/hotplug/pcihp_slot.c3
-rw-r--r--drivers/pci/hotplug/rpadlpar_core.c3
-rw-r--r--drivers/pci/hotplug/rpaphp_core.c15
-rw-r--r--drivers/pci/hotplug/s390_pci_hpc.c1
-rw-r--r--drivers/pci/hotplug/shpchp_pci.c5
-rw-r--r--drivers/pci/iov.c2
-rw-r--r--drivers/pci/msi.c96
-rw-r--r--drivers/pci/pci-acpi.c8
-rw-r--r--drivers/pci/pci-driver.c58
-rw-r--r--drivers/pci/pci-sysfs.c68
-rw-r--r--drivers/pci/pci.c34
-rw-r--r--drivers/pci/pci.h10
-rw-r--r--drivers/pci/pcie/portdrv_core.c9
-rw-r--r--drivers/pci/probe.c101
-rw-r--r--drivers/pci/quirks.c86
-rw-r--r--drivers/pci/search.c88
-rw-r--r--drivers/pci/setup-bus.c251
-rw-r--r--drivers/pci/setup-irq.c1
-rw-r--r--drivers/pci/setup-res.c42
41 files changed, 2214 insertions, 310 deletions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 7f8b78c08879..8c148f39e8d7 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -148,7 +148,7 @@ static noinline void pci_wait_cfg(struct pci_dev *dev)
148int pci_user_read_config_##size \ 148int pci_user_read_config_##size \
149 (struct pci_dev *dev, int pos, type *val) \ 149 (struct pci_dev *dev, int pos, type *val) \
150{ \ 150{ \
151 int ret = 0; \ 151 int ret = PCIBIOS_SUCCESSFUL; \
152 u32 data = -1; \ 152 u32 data = -1; \
153 if (PCI_##size##_BAD) \ 153 if (PCI_##size##_BAD) \
154 return -EINVAL; \ 154 return -EINVAL; \
@@ -159,9 +159,7 @@ int pci_user_read_config_##size \
159 pos, sizeof(type), &data); \ 159 pos, sizeof(type), &data); \
160 raw_spin_unlock_irq(&pci_lock); \ 160 raw_spin_unlock_irq(&pci_lock); \
161 *val = (type)data; \ 161 *val = (type)data; \
162 if (ret > 0) \ 162 return pcibios_err_to_errno(ret); \
163 ret = -EINVAL; \
164 return ret; \
165} \ 163} \
166EXPORT_SYMBOL_GPL(pci_user_read_config_##size); 164EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
167 165
@@ -170,7 +168,7 @@ EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
170int pci_user_write_config_##size \ 168int pci_user_write_config_##size \
171 (struct pci_dev *dev, int pos, type val) \ 169 (struct pci_dev *dev, int pos, type val) \
172{ \ 170{ \
173 int ret = -EIO; \ 171 int ret = PCIBIOS_SUCCESSFUL; \
174 if (PCI_##size##_BAD) \ 172 if (PCI_##size##_BAD) \
175 return -EINVAL; \ 173 return -EINVAL; \
176 raw_spin_lock_irq(&pci_lock); \ 174 raw_spin_lock_irq(&pci_lock); \
@@ -179,9 +177,7 @@ int pci_user_write_config_##size \
179 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 177 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
180 pos, sizeof(type), val); \ 178 pos, sizeof(type), val); \
181 raw_spin_unlock_irq(&pci_lock); \ 179 raw_spin_unlock_irq(&pci_lock); \
182 if (ret > 0) \ 180 return pcibios_err_to_errno(ret); \
183 ret = -EINVAL; \
184 return ret; \
185} \ 181} \
186EXPORT_SYMBOL_GPL(pci_user_write_config_##size); 182EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
187 183
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index fb8aed307c28..447d393725e1 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -13,7 +13,6 @@
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/proc_fs.h> 15#include <linux/proc_fs.h>
16#include <linux/init.h>
17#include <linux/slab.h> 16#include <linux/slab.h>
18 17
19#include "pci.h" 18#include "pci.h"
@@ -236,7 +235,7 @@ void __weak pcibios_resource_survey_bus(struct pci_bus *bus) { }
236 * 235 *
237 * This adds add sysfs entries and start device drivers 236 * This adds add sysfs entries and start device drivers
238 */ 237 */
239int pci_bus_add_device(struct pci_dev *dev) 238void pci_bus_add_device(struct pci_dev *dev)
240{ 239{
241 int retval; 240 int retval;
242 241
@@ -253,8 +252,6 @@ int pci_bus_add_device(struct pci_dev *dev)
253 WARN_ON(retval < 0); 252 WARN_ON(retval < 0);
254 253
255 dev->is_added = 1; 254 dev->is_added = 1;
256
257 return 0;
258} 255}
259 256
260/** 257/**
@@ -267,16 +264,12 @@ void pci_bus_add_devices(const struct pci_bus *bus)
267{ 264{
268 struct pci_dev *dev; 265 struct pci_dev *dev;
269 struct pci_bus *child; 266 struct pci_bus *child;
270 int retval;
271 267
272 list_for_each_entry(dev, &bus->devices, bus_list) { 268 list_for_each_entry(dev, &bus->devices, bus_list) {
273 /* Skip already-added devices */ 269 /* Skip already-added devices */
274 if (dev->is_added) 270 if (dev->is_added)
275 continue; 271 continue;
276 retval = pci_bus_add_device(dev); 272 pci_bus_add_device(dev);
277 if (retval)
278 dev_err(&dev->dev, "Error adding device (%d)\n",
279 retval);
280 } 273 }
281 274
282 list_for_each_entry(dev, &bus->devices, bus_list) { 275 list_for_each_entry(dev, &bus->devices, bus_list) {
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index 47aaf22d814e..0e5f3c95af5b 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -3,7 +3,6 @@
3 */ 3 */
4 4
5#include <linux/kernel.h> 5#include <linux/kernel.h>
6#include <linux/init.h>
7#include <linux/pci.h> 6#include <linux/pci.h>
8#include <linux/module.h> 7#include <linux/module.h>
9 8
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec8882f..21df477be0c8 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,17 @@ config PCI_RCAR_GEN2
33 There are 3 internal PCI controllers available with a single 33 There are 3 internal PCI controllers available with a single
34 built-in EHCI/OHCI host controller present on each one. 34 built-in EHCI/OHCI host controller present on each one.
35 35
36config PCI_RCAR_GEN2_PCIE
37 bool "Renesas R-Car PCIe controller"
38 depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
39 help
40 Say Y here if you want PCIe controller support on R-Car Gen2 SoCs.
41
42config PCI_HOST_GENERIC
43 bool "Generic PCI host controller"
44 depends on ARM && OF
45 help
46 Say Y here if you want to support a simple generic PCI host
47 controller, such as the one emulated by kvmtool.
48
36endmenu 49endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb3333aa05..611ba4b48c94 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,5 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
4obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o 4obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
5obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o 5obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
6obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o 6obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
7obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
8obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index b616d34922d8..c5d0ca384502 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -509,7 +509,8 @@ static struct pcie_host_ops exynos_pcie_host_ops = {
509 .host_init = exynos_pcie_host_init, 509 .host_init = exynos_pcie_host_init,
510}; 510};
511 511
512static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) 512static int __init add_pcie_port(struct pcie_port *pp,
513 struct platform_device *pdev)
513{ 514{
514 int ret; 515 int ret;
515 516
@@ -544,7 +545,6 @@ static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
544 pp->root_bus_nr = -1; 545 pp->root_bus_nr = -1;
545 pp->ops = &exynos_pcie_host_ops; 546 pp->ops = &exynos_pcie_host_ops;
546 547
547 spin_lock_init(&pp->conf_lock);
548 ret = dw_pcie_host_init(pp); 548 ret = dw_pcie_host_init(pp);
549 if (ret) { 549 if (ret) {
550 dev_err(&pdev->dev, "failed to initialize host\n"); 550 dev_err(&pdev->dev, "failed to initialize host\n");
@@ -566,10 +566,8 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
566 566
567 exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie), 567 exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
568 GFP_KERNEL); 568 GFP_KERNEL);
569 if (!exynos_pcie) { 569 if (!exynos_pcie)
570 dev_err(&pdev->dev, "no memory for exynos pcie\n");
571 return -ENOMEM; 570 return -ENOMEM;
572 }
573 571
574 pp = &exynos_pcie->pp; 572 pp = &exynos_pcie->pp;
575 573
diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c
new file mode 100644
index 000000000000..44fe6aa6a43f
--- /dev/null
+++ b/drivers/pci/host/pci-host-generic.c
@@ -0,0 +1,388 @@
1/*
2 * Simple, generic PCI host controller driver targetting firmware-initialised
3 * systems and virtual machines (e.g. the PCI emulation provided by kvmtool).
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * Copyright (C) 2014 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of_address.h>
25#include <linux/of_pci.h>
26#include <linux/platform_device.h>
27
28struct gen_pci_cfg_bus_ops {
29 u32 bus_shift;
30 void __iomem *(*map_bus)(struct pci_bus *, unsigned int, int);
31};
32
33struct gen_pci_cfg_windows {
34 struct resource res;
35 struct resource bus_range;
36 void __iomem **win;
37
38 const struct gen_pci_cfg_bus_ops *ops;
39};
40
41struct gen_pci {
42 struct pci_host_bridge host;
43 struct gen_pci_cfg_windows cfg;
44 struct list_head resources;
45};
46
47static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
48 unsigned int devfn,
49 int where)
50{
51 struct pci_sys_data *sys = bus->sysdata;
52 struct gen_pci *pci = sys->private_data;
53 resource_size_t idx = bus->number - pci->cfg.bus_range.start;
54
55 return pci->cfg.win[idx] + ((devfn << 8) | where);
56}
57
58static struct gen_pci_cfg_bus_ops gen_pci_cfg_cam_bus_ops = {
59 .bus_shift = 16,
60 .map_bus = gen_pci_map_cfg_bus_cam,
61};
62
63static void __iomem *gen_pci_map_cfg_bus_ecam(struct pci_bus *bus,
64 unsigned int devfn,
65 int where)
66{
67 struct pci_sys_data *sys = bus->sysdata;
68 struct gen_pci *pci = sys->private_data;
69 resource_size_t idx = bus->number - pci->cfg.bus_range.start;
70
71 return pci->cfg.win[idx] + ((devfn << 12) | where);
72}
73
74static struct gen_pci_cfg_bus_ops gen_pci_cfg_ecam_bus_ops = {
75 .bus_shift = 20,
76 .map_bus = gen_pci_map_cfg_bus_ecam,
77};
78
79static int gen_pci_config_read(struct pci_bus *bus, unsigned int devfn,
80 int where, int size, u32 *val)
81{
82 void __iomem *addr;
83 struct pci_sys_data *sys = bus->sysdata;
84 struct gen_pci *pci = sys->private_data;
85
86 addr = pci->cfg.ops->map_bus(bus, devfn, where);
87
88 switch (size) {
89 case 1:
90 *val = readb(addr);
91 break;
92 case 2:
93 *val = readw(addr);
94 break;
95 default:
96 *val = readl(addr);
97 }
98
99 return PCIBIOS_SUCCESSFUL;
100}
101
102static int gen_pci_config_write(struct pci_bus *bus, unsigned int devfn,
103 int where, int size, u32 val)
104{
105 void __iomem *addr;
106 struct pci_sys_data *sys = bus->sysdata;
107 struct gen_pci *pci = sys->private_data;
108
109 addr = pci->cfg.ops->map_bus(bus, devfn, where);
110
111 switch (size) {
112 case 1:
113 writeb(val, addr);
114 break;
115 case 2:
116 writew(val, addr);
117 break;
118 default:
119 writel(val, addr);
120 }
121
122 return PCIBIOS_SUCCESSFUL;
123}
124
125static struct pci_ops gen_pci_ops = {
126 .read = gen_pci_config_read,
127 .write = gen_pci_config_write,
128};
129
130static const struct of_device_id gen_pci_of_match[] = {
131 { .compatible = "pci-host-cam-generic",
132 .data = &gen_pci_cfg_cam_bus_ops },
133
134 { .compatible = "pci-host-ecam-generic",
135 .data = &gen_pci_cfg_ecam_bus_ops },
136
137 { },
138};
139MODULE_DEVICE_TABLE(of, gen_pci_of_match);
140
141static int gen_pci_calc_io_offset(struct device *dev,
142 struct of_pci_range *range,
143 struct resource *res,
144 resource_size_t *offset)
145{
146 static atomic_t wins = ATOMIC_INIT(0);
147 int err, idx, max_win;
148 unsigned int window;
149
150 if (!PAGE_ALIGNED(range->cpu_addr))
151 return -EINVAL;
152
153 max_win = (IO_SPACE_LIMIT + 1) / SZ_64K;
154 idx = atomic_inc_return(&wins);
155 if (idx > max_win)
156 return -ENOSPC;
157
158 window = (idx - 1) * SZ_64K;
159 err = pci_ioremap_io(window, range->cpu_addr);
160 if (err)
161 return err;
162
163 of_pci_range_to_resource(range, dev->of_node, res);
164 res->start = window;
165 res->end = res->start + range->size - 1;
166 *offset = window - range->pci_addr;
167 return 0;
168}
169
170static int gen_pci_calc_mem_offset(struct device *dev,
171 struct of_pci_range *range,
172 struct resource *res,
173 resource_size_t *offset)
174{
175 of_pci_range_to_resource(range, dev->of_node, res);
176 *offset = range->cpu_addr - range->pci_addr;
177 return 0;
178}
179
180static void gen_pci_release_of_pci_ranges(struct gen_pci *pci)
181{
182 struct pci_host_bridge_window *win;
183
184 list_for_each_entry(win, &pci->resources, list)
185 release_resource(win->res);
186
187 pci_free_resource_list(&pci->resources);
188}
189
190static int gen_pci_parse_request_of_pci_ranges(struct gen_pci *pci)
191{
192 struct of_pci_range range;
193 struct of_pci_range_parser parser;
194 int err, res_valid = 0;
195 struct device *dev = pci->host.dev.parent;
196 struct device_node *np = dev->of_node;
197
198 if (of_pci_range_parser_init(&parser, np)) {
199 dev_err(dev, "missing \"ranges\" property\n");
200 return -EINVAL;
201 }
202
203 for_each_of_pci_range(&parser, &range) {
204 struct resource *parent, *res;
205 resource_size_t offset;
206 u32 restype = range.flags & IORESOURCE_TYPE_BITS;
207
208 res = devm_kmalloc(dev, sizeof(*res), GFP_KERNEL);
209 if (!res) {
210 err = -ENOMEM;
211 goto out_release_res;
212 }
213
214 switch (restype) {
215 case IORESOURCE_IO:
216 parent = &ioport_resource;
217 err = gen_pci_calc_io_offset(dev, &range, res, &offset);
218 break;
219 case IORESOURCE_MEM:
220 parent = &iomem_resource;
221 err = gen_pci_calc_mem_offset(dev, &range, res, &offset);
222 res_valid |= !(res->flags & IORESOURCE_PREFETCH || err);
223 break;
224 default:
225 err = -EINVAL;
226 continue;
227 }
228
229 if (err) {
230 dev_warn(dev,
231 "error %d: failed to add resource [type 0x%x, %lld bytes]\n",
232 err, restype, range.size);
233 continue;
234 }
235
236 err = request_resource(parent, res);
237 if (err)
238 goto out_release_res;
239
240 pci_add_resource_offset(&pci->resources, res, offset);
241 }
242
243 if (!res_valid) {
244 dev_err(dev, "non-prefetchable memory resource required\n");
245 err = -EINVAL;
246 goto out_release_res;
247 }
248
249 return 0;
250
251out_release_res:
252 gen_pci_release_of_pci_ranges(pci);
253 return err;
254}
255
256static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
257{
258 int err;
259 u8 bus_max;
260 resource_size_t busn;
261 struct resource *bus_range;
262 struct device *dev = pci->host.dev.parent;
263 struct device_node *np = dev->of_node;
264
265 if (of_pci_parse_bus_range(np, &pci->cfg.bus_range))
266 pci->cfg.bus_range = (struct resource) {
267 .name = np->name,
268 .start = 0,
269 .end = 0xff,
270 .flags = IORESOURCE_BUS,
271 };
272
273 err = of_address_to_resource(np, 0, &pci->cfg.res);
274 if (err) {
275 dev_err(dev, "missing \"reg\" property\n");
276 return err;
277 }
278
279 pci->cfg.win = devm_kcalloc(dev, resource_size(&pci->cfg.bus_range),
280 sizeof(*pci->cfg.win), GFP_KERNEL);
281 if (!pci->cfg.win)
282 return -ENOMEM;
283
284 /* Limit the bus-range to fit within reg */
285 bus_max = pci->cfg.bus_range.start +
286 (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
287 pci->cfg.bus_range.end = min_t(resource_size_t, pci->cfg.bus_range.end,
288 bus_max);
289
290 /* Map our Configuration Space windows */
291 if (!devm_request_mem_region(dev, pci->cfg.res.start,
292 resource_size(&pci->cfg.res),
293 "Configuration Space"))
294 return -ENOMEM;
295
296 bus_range = &pci->cfg.bus_range;
297 for (busn = bus_range->start; busn <= bus_range->end; ++busn) {
298 u32 idx = busn - bus_range->start;
299 u32 sz = 1 << pci->cfg.ops->bus_shift;
300
301 pci->cfg.win[idx] = devm_ioremap(dev,
302 pci->cfg.res.start + busn * sz,
303 sz);
304 if (!pci->cfg.win[idx])
305 return -ENOMEM;
306 }
307
308 /* Register bus resource */
309 pci_add_resource(&pci->resources, bus_range);
310 return 0;
311}
312
313static int gen_pci_setup(int nr, struct pci_sys_data *sys)
314{
315 struct gen_pci *pci = sys->private_data;
316 list_splice_init(&pci->resources, &sys->resources);
317 return 1;
318}
319
320static int gen_pci_probe(struct platform_device *pdev)
321{
322 int err;
323 const char *type;
324 const struct of_device_id *of_id;
325 const int *prop;
326 struct device *dev = &pdev->dev;
327 struct device_node *np = dev->of_node;
328 struct gen_pci *pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
329 struct hw_pci hw = {
330 .nr_controllers = 1,
331 .private_data = (void **)&pci,
332 .setup = gen_pci_setup,
333 .map_irq = of_irq_parse_and_map_pci,
334 .ops = &gen_pci_ops,
335 };
336
337 if (!pci)
338 return -ENOMEM;
339
340 type = of_get_property(np, "device_type", NULL);
341 if (!type || strcmp(type, "pci")) {
342 dev_err(dev, "invalid \"device_type\" %s\n", type);
343 return -EINVAL;
344 }
345
346 prop = of_get_property(of_chosen, "linux,pci-probe-only", NULL);
347 if (prop) {
348 if (*prop)
349 pci_add_flags(PCI_PROBE_ONLY);
350 else
351 pci_clear_flags(PCI_PROBE_ONLY);
352 }
353
354 of_id = of_match_node(gen_pci_of_match, np);
355 pci->cfg.ops = of_id->data;
356 pci->host.dev.parent = dev;
357 INIT_LIST_HEAD(&pci->host.windows);
358 INIT_LIST_HEAD(&pci->resources);
359
360 /* Parse our PCI ranges and request their resources */
361 err = gen_pci_parse_request_of_pci_ranges(pci);
362 if (err)
363 return err;
364
365 /* Parse and map our Configuration Space windows */
366 err = gen_pci_parse_map_cfg_windows(pci);
367 if (err) {
368 gen_pci_release_of_pci_ranges(pci);
369 return err;
370 }
371
372 pci_common_init_dev(dev, &hw);
373 return 0;
374}
375
376static struct platform_driver gen_pci_driver = {
377 .driver = {
378 .name = "pci-host-generic",
379 .owner = THIS_MODULE,
380 .of_match_table = gen_pci_of_match,
381 },
382 .probe = gen_pci_probe,
383};
384module_platform_driver(gen_pci_driver);
385
386MODULE_DESCRIPTION("Generic PCI host driver");
387MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
388MODULE_LICENSE("GPLv2");
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index a5645ae4aef0..a568efaa331c 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -507,7 +507,6 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp,
507 pp->root_bus_nr = -1; 507 pp->root_bus_nr = -1;
508 pp->ops = &imx6_pcie_host_ops; 508 pp->ops = &imx6_pcie_host_ops;
509 509
510 spin_lock_init(&pp->conf_lock);
511 ret = dw_pcie_host_init(pp); 510 ret = dw_pcie_host_init(pp);
512 if (ret) { 511 if (ret) {
513 dev_err(&pdev->dev, "failed to initialize host\n"); 512 dev_err(&pdev->dev, "failed to initialize host\n");
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index d3d1cfd51e09..7f450322f397 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -113,7 +113,6 @@ struct mvebu_pcie {
113struct mvebu_pcie_port { 113struct mvebu_pcie_port {
114 char *name; 114 char *name;
115 void __iomem *base; 115 void __iomem *base;
116 spinlock_t conf_lock;
117 u32 port; 116 u32 port;
118 u32 lane; 117 u32 lane;
119 int devfn; 118 int devfn;
@@ -293,6 +292,60 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
293 return PCIBIOS_SUCCESSFUL; 292 return PCIBIOS_SUCCESSFUL;
294} 293}
295 294
295/*
296 * Remove windows, starting from the largest ones to the smallest
297 * ones.
298 */
299static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
300 phys_addr_t base, size_t size)
301{
302 while (size) {
303 size_t sz = 1 << (fls(size) - 1);
304
305 mvebu_mbus_del_window(base, sz);
306 base += sz;
307 size -= sz;
308 }
309}
310
311/*
312 * MBus windows can only have a power of two size, but PCI BARs do not
313 * have this constraint. Therefore, we have to split the PCI BAR into
314 * areas each having a power of two size. We start from the largest
315 * one (i.e highest order bit set in the size).
316 */
317static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
318 unsigned int target, unsigned int attribute,
319 phys_addr_t base, size_t size,
320 phys_addr_t remap)
321{
322 size_t size_mapped = 0;
323
324 while (size) {
325 size_t sz = 1 << (fls(size) - 1);
326 int ret;
327
328 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
329 sz, remap);
330 if (ret) {
331 phys_addr_t end = base + sz - 1;
332
333 dev_err(&port->pcie->pdev->dev,
334 "Could not create MBus window at [mem %pa-%pa]: %d\n",
335 &base, &end, ret);
336 mvebu_pcie_del_windows(port, base - size_mapped,
337 size_mapped);
338 return;
339 }
340
341 size -= sz;
342 size_mapped += sz;
343 base += sz;
344 if (remap != MVEBU_MBUS_NO_REMAP)
345 remap += sz;
346 }
347}
348
296static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 349static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
297{ 350{
298 phys_addr_t iobase; 351 phys_addr_t iobase;
@@ -304,8 +357,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
304 357
305 /* If a window was configured, remove it */ 358 /* If a window was configured, remove it */
306 if (port->iowin_base) { 359 if (port->iowin_base) {
307 mvebu_mbus_del_window(port->iowin_base, 360 mvebu_pcie_del_windows(port, port->iowin_base,
308 port->iowin_size); 361 port->iowin_size);
309 port->iowin_base = 0; 362 port->iowin_base = 0;
310 port->iowin_size = 0; 363 port->iowin_size = 0;
311 } 364 }
@@ -331,11 +384,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
331 port->iowin_base = port->pcie->io.start + iobase; 384 port->iowin_base = port->pcie->io.start + iobase;
332 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 385 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
333 (port->bridge.iolimitupper << 16)) - 386 (port->bridge.iolimitupper << 16)) -
334 iobase); 387 iobase) + 1;
335 388
336 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr, 389 mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
337 port->iowin_base, port->iowin_size, 390 port->iowin_base, port->iowin_size,
338 iobase); 391 iobase);
339} 392}
340 393
341static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 394static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
@@ -346,8 +399,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
346 399
347 /* If a window was configured, remove it */ 400 /* If a window was configured, remove it */
348 if (port->memwin_base) { 401 if (port->memwin_base) {
349 mvebu_mbus_del_window(port->memwin_base, 402 mvebu_pcie_del_windows(port, port->memwin_base,
350 port->memwin_size); 403 port->memwin_size);
351 port->memwin_base = 0; 404 port->memwin_base = 0;
352 port->memwin_size = 0; 405 port->memwin_size = 0;
353 } 406 }
@@ -364,10 +417,11 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
364 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); 417 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
365 port->memwin_size = 418 port->memwin_size =
366 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 419 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
367 port->memwin_base; 420 port->memwin_base + 1;
368 421
369 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr, 422 mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
370 port->memwin_base, port->memwin_size); 423 port->memwin_base, port->memwin_size,
424 MVEBU_MBUS_NO_REMAP);
371} 425}
372 426
373/* 427/*
@@ -585,7 +639,6 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
585{ 639{
586 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 640 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
587 struct mvebu_pcie_port *port; 641 struct mvebu_pcie_port *port;
588 unsigned long flags;
589 int ret; 642 int ret;
590 643
591 port = mvebu_pcie_find_port(pcie, bus, devfn); 644 port = mvebu_pcie_find_port(pcie, bus, devfn);
@@ -611,10 +664,8 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
611 return PCIBIOS_DEVICE_NOT_FOUND; 664 return PCIBIOS_DEVICE_NOT_FOUND;
612 665
613 /* Access the real PCIe interface */ 666 /* Access the real PCIe interface */
614 spin_lock_irqsave(&port->conf_lock, flags);
615 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, 667 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
616 where, size, val); 668 where, size, val);
617 spin_unlock_irqrestore(&port->conf_lock, flags);
618 669
619 return ret; 670 return ret;
620} 671}
@@ -625,7 +676,6 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
625{ 676{
626 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); 677 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
627 struct mvebu_pcie_port *port; 678 struct mvebu_pcie_port *port;
628 unsigned long flags;
629 int ret; 679 int ret;
630 680
631 port = mvebu_pcie_find_port(pcie, bus, devfn); 681 port = mvebu_pcie_find_port(pcie, bus, devfn);
@@ -657,10 +707,8 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
657 } 707 }
658 708
659 /* Access the real PCIe interface */ 709 /* Access the real PCIe interface */
660 spin_lock_irqsave(&port->conf_lock, flags);
661 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, 710 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
662 where, size, val); 711 where, size, val);
663 spin_unlock_irqrestore(&port->conf_lock, flags);
664 712
665 return ret; 713 return ret;
666} 714}
@@ -743,14 +791,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
743 791
744 /* 792 /*
745 * On the PCI-to-PCI bridge side, the I/O windows must have at 793 * On the PCI-to-PCI bridge side, the I/O windows must have at
746 * least a 64 KB size and be aligned on their size, and the 794 * least a 64 KB size and the memory windows must have at
747 * memory windows must have at least a 1 MB size and be 795 * least a 1 MB size. Moreover, MBus windows need to have a
748 * aligned on their size 796 * base address aligned on their size, and their size must be
797 * a power of two. This means that if the BAR doesn't have a
798 * power of two size, several MBus windows will actually be
799 * created. We need to ensure that the biggest MBus window
800 * (which will be the first one) is aligned on its size, which
801 * explains the rounddown_pow_of_two() being done here.
749 */ 802 */
750 if (res->flags & IORESOURCE_IO) 803 if (res->flags & IORESOURCE_IO)
751 return round_up(start, max_t(resource_size_t, SZ_64K, size)); 804 return round_up(start, max_t(resource_size_t, SZ_64K,
805 rounddown_pow_of_two(size)));
752 else if (res->flags & IORESOURCE_MEM) 806 else if (res->flags & IORESOURCE_MEM)
753 return round_up(start, max_t(resource_size_t, SZ_1M, size)); 807 return round_up(start, max_t(resource_size_t, SZ_1M,
808 rounddown_pow_of_two(size)));
754 else 809 else
755 return start; 810 return start;
756} 811}
@@ -1000,7 +1055,6 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
1000 mvebu_pcie_set_local_dev_nr(port, 1); 1055 mvebu_pcie_set_local_dev_nr(port, 1);
1001 1056
1002 port->dn = child; 1057 port->dn = child;
1003 spin_lock_init(&port->conf_lock);
1004 mvebu_sw_pci_bridge_init(port); 1058 mvebu_sw_pci_bridge_init(port);
1005 i++; 1059 i++;
1006 } 1060 }
diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
index fd3e3ab56509..3ef854f5a5b5 100644
--- a/drivers/pci/host/pci-rcar-gen2.c
+++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -15,6 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/of_pci.h>
18#include <linux/pci.h> 19#include <linux/pci.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
20#include <linux/pm_runtime.h> 21#include <linux/pm_runtime.h>
@@ -98,6 +99,7 @@ struct rcar_pci_priv {
98 struct resource io_res; 99 struct resource io_res;
99 struct resource mem_res; 100 struct resource mem_res;
100 struct resource *cfg_res; 101 struct resource *cfg_res;
102 unsigned busnr;
101 int irq; 103 int irq;
102 unsigned long window_size; 104 unsigned long window_size;
103}; 105};
@@ -180,8 +182,13 @@ static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
180{ 182{
181 struct pci_sys_data *sys = dev->bus->sysdata; 183 struct pci_sys_data *sys = dev->bus->sysdata;
182 struct rcar_pci_priv *priv = sys->private_data; 184 struct rcar_pci_priv *priv = sys->private_data;
185 int irq;
186
187 irq = of_irq_parse_and_map_pci(dev, slot, pin);
188 if (!irq)
189 irq = priv->irq;
183 190
184 return priv->irq; 191 return irq;
185} 192}
186 193
187#ifdef CONFIG_PCI_DEBUG 194#ifdef CONFIG_PCI_DEBUG
@@ -312,8 +319,8 @@ static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
312 pci_add_resource(&sys->resources, &priv->io_res); 319 pci_add_resource(&sys->resources, &priv->io_res);
313 pci_add_resource(&sys->resources, &priv->mem_res); 320 pci_add_resource(&sys->resources, &priv->mem_res);
314 321
315 /* Setup bus number based on platform device id */ 322 /* Setup bus number based on platform device id / of bus-range */
316 sys->busnr = to_platform_device(priv->dev)->id; 323 sys->busnr = priv->busnr;
317 return 1; 324 return 1;
318} 325}
319 326
@@ -366,6 +373,23 @@ static int rcar_pci_probe(struct platform_device *pdev)
366 373
367 priv->window_size = SZ_1G; 374 priv->window_size = SZ_1G;
368 375
376 if (pdev->dev.of_node) {
377 struct resource busnr;
378 int ret;
379
380 ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
381 if (ret < 0) {
382 dev_err(&pdev->dev, "failed to parse bus-range\n");
383 return ret;
384 }
385
386 priv->busnr = busnr.start;
387 if (busnr.end != busnr.start)
388 dev_warn(&pdev->dev, "only one bus number supported\n");
389 } else {
390 priv->busnr = pdev->id;
391 }
392
369 hw_private[0] = priv; 393 hw_private[0] = priv;
370 memset(&hw, 0, sizeof(hw)); 394 memset(&hw, 0, sizeof(hw));
371 hw.nr_controllers = ARRAY_SIZE(hw_private); 395 hw.nr_controllers = ARRAY_SIZE(hw_private);
@@ -377,11 +401,20 @@ static int rcar_pci_probe(struct platform_device *pdev)
377 return 0; 401 return 0;
378} 402}
379 403
404static struct of_device_id rcar_pci_of_match[] = {
405 { .compatible = "renesas,pci-r8a7790", },
406 { .compatible = "renesas,pci-r8a7791", },
407 { },
408};
409
410MODULE_DEVICE_TABLE(of, rcar_pci_of_match);
411
380static struct platform_driver rcar_pci_driver = { 412static struct platform_driver rcar_pci_driver = {
381 .driver = { 413 .driver = {
382 .name = "pci-rcar-gen2", 414 .name = "pci-rcar-gen2",
383 .owner = THIS_MODULE, 415 .owner = THIS_MODULE,
384 .suppress_bind_attrs = true, 416 .suppress_bind_attrs = true,
417 .of_match_table = rcar_pci_of_match,
385 }, 418 },
386 .probe = rcar_pci_probe, 419 .probe = rcar_pci_probe,
387}; 420};
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 330f7e3a32dd..083cf37ca047 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -639,10 +639,15 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
639static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) 639static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
640{ 640{
641 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata); 641 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
642 int irq;
642 643
643 tegra_cpuidle_pcie_irqs_in_use(); 644 tegra_cpuidle_pcie_irqs_in_use();
644 645
645 return pcie->irq; 646 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
647 if (!irq)
648 irq = pcie->irq;
649
650 return irq;
646} 651}
647 652
648static void tegra_pcie_add_bus(struct pci_bus *bus) 653static void tegra_pcie_add_bus(struct pci_bus *bus)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 77a649dd1473..1eaf4df3618a 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -17,6 +17,7 @@
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/msi.h> 18#include <linux/msi.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/of_pci.h>
20#include <linux/pci.h> 21#include <linux/pci.h>
21#include <linux/pci_regs.h> 22#include <linux/pci_regs.h>
22#include <linux/types.h> 23#include <linux/types.h>
@@ -494,7 +495,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
494 dw_pci.nr_controllers = 1; 495 dw_pci.nr_controllers = 1;
495 dw_pci.private_data = (void **)&pp; 496 dw_pci.private_data = (void **)&pp;
496 497
497 pci_common_init(&dw_pci); 498 pci_common_init_dev(pp->dev, &dw_pci);
498 pci_assign_unassigned_resources(); 499 pci_assign_unassigned_resources();
499#ifdef CONFIG_PCI_DOMAINS 500#ifdef CONFIG_PCI_DOMAINS
500 dw_pci.domain++; 501 dw_pci.domain++;
@@ -524,13 +525,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
524 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 525 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
525 PCIE_ATU_VIEWPORT); 526 PCIE_ATU_VIEWPORT);
526 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); 527 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
527 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
528 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE); 528 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
529 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE); 529 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
530 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, 530 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
531 PCIE_ATU_LIMIT); 531 PCIE_ATU_LIMIT);
532 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); 532 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
533 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); 533 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
534 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
534} 535}
535 536
536static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) 537static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -539,7 +540,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
539 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 540 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
540 PCIE_ATU_VIEWPORT); 541 PCIE_ATU_VIEWPORT);
541 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); 542 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
542 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
543 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); 543 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
544 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); 544 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
545 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, 545 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
@@ -547,6 +547,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
547 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); 547 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
548 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), 548 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
549 PCIE_ATU_UPPER_TARGET); 549 PCIE_ATU_UPPER_TARGET);
550 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
550} 551}
551 552
552static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) 553static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
@@ -555,7 +556,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
555 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 556 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
556 PCIE_ATU_VIEWPORT); 557 PCIE_ATU_VIEWPORT);
557 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); 558 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
558 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
559 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); 559 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
560 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); 560 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
561 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, 561 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
@@ -563,6 +563,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
563 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); 563 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
564 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), 564 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
565 PCIE_ATU_UPPER_TARGET); 565 PCIE_ATU_UPPER_TARGET);
566 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
566} 567}
567 568
568static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 569static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -642,7 +643,6 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
642 int size, u32 *val) 643 int size, u32 *val)
643{ 644{
644 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 645 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
645 unsigned long flags;
646 int ret; 646 int ret;
647 647
648 if (!pp) { 648 if (!pp) {
@@ -655,13 +655,11 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
655 return PCIBIOS_DEVICE_NOT_FOUND; 655 return PCIBIOS_DEVICE_NOT_FOUND;
656 } 656 }
657 657
658 spin_lock_irqsave(&pp->conf_lock, flags);
659 if (bus->number != pp->root_bus_nr) 658 if (bus->number != pp->root_bus_nr)
660 ret = dw_pcie_rd_other_conf(pp, bus, devfn, 659 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
661 where, size, val); 660 where, size, val);
662 else 661 else
663 ret = dw_pcie_rd_own_conf(pp, where, size, val); 662 ret = dw_pcie_rd_own_conf(pp, where, size, val);
664 spin_unlock_irqrestore(&pp->conf_lock, flags);
665 663
666 return ret; 664 return ret;
667} 665}
@@ -670,7 +668,6 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
670 int where, int size, u32 val) 668 int where, int size, u32 val)
671{ 669{
672 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 670 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
673 unsigned long flags;
674 int ret; 671 int ret;
675 672
676 if (!pp) { 673 if (!pp) {
@@ -681,13 +678,11 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
681 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) 678 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
682 return PCIBIOS_DEVICE_NOT_FOUND; 679 return PCIBIOS_DEVICE_NOT_FOUND;
683 680
684 spin_lock_irqsave(&pp->conf_lock, flags);
685 if (bus->number != pp->root_bus_nr) 681 if (bus->number != pp->root_bus_nr)
686 ret = dw_pcie_wr_other_conf(pp, bus, devfn, 682 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
687 where, size, val); 683 where, size, val);
688 else 684 else
689 ret = dw_pcie_wr_own_conf(pp, where, size, val); 685 ret = dw_pcie_wr_own_conf(pp, where, size, val);
690 spin_unlock_irqrestore(&pp->conf_lock, flags);
691 686
692 return ret; 687 return ret;
693} 688}
@@ -727,7 +722,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
727 722
728 if (pp) { 723 if (pp) {
729 pp->root_bus_nr = sys->busnr; 724 pp->root_bus_nr = sys->busnr;
730 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops, 725 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
731 sys, &sys->resources); 726 sys, &sys->resources);
732 } else { 727 } else {
733 bus = NULL; 728 bus = NULL;
@@ -740,8 +735,13 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
740static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 735static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
741{ 736{
742 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); 737 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
738 int irq;
739
740 irq = of_irq_parse_and_map_pci(dev, slot, pin);
741 if (!irq)
742 irq = pp->irq;
743 743
744 return pp->irq; 744 return irq;
745} 745}
746 746
747static void dw_pcie_add_bus(struct pci_bus *bus) 747static void dw_pcie_add_bus(struct pci_bus *bus)
@@ -768,7 +768,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
768 u32 membase; 768 u32 membase;
769 u32 memlimit; 769 u32 memlimit;
770 770
771 /* set the number of lines as 4 */ 771 /* set the number of lanes */
772 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); 772 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
773 val &= ~PORT_LINK_MODE_MASK; 773 val &= ~PORT_LINK_MODE_MASK;
774 switch (pp->lanes) { 774 switch (pp->lanes) {
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index a169d22d517e..77f592faa7bf 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -41,7 +41,6 @@ struct pcie_port {
41 void __iomem *va_cfg1_base; 41 void __iomem *va_cfg1_base;
42 u64 io_base; 42 u64 io_base;
43 u64 mem_base; 43 u64 mem_base;
44 spinlock_t conf_lock;
45 struct resource cfg; 44 struct resource cfg;
46 struct resource io; 45 struct resource io;
47 struct resource mem; 46 struct resource mem;
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
new file mode 100644
index 000000000000..8e06124aa80f
--- /dev/null
+++ b/drivers/pci/host/pcie-rcar.c
@@ -0,0 +1,1008 @@
1/*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/msi.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/of_platform.h>
27#include <linux/pci.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30
31#define DRV_NAME "rcar-pcie"
32
33#define PCIECAR 0x000010
34#define PCIECCTLR 0x000018
35#define CONFIG_SEND_ENABLE (1 << 31)
36#define TYPE0 (0 << 8)
37#define TYPE1 (1 << 8)
38#define PCIECDR 0x000020
39#define PCIEMSR 0x000028
40#define PCIEINTXR 0x000400
41#define PCIEMSITXR 0x000840
42
43/* Transfer control */
44#define PCIETCTLR 0x02000
45#define CFINIT 1
46#define PCIETSTR 0x02004
47#define DATA_LINK_ACTIVE 1
48#define PCIEERRFR 0x02020
49#define UNSUPPORTED_REQUEST (1 << 4)
50#define PCIEMSIFR 0x02044
51#define PCIEMSIALR 0x02048
52#define MSIFE 1
53#define PCIEMSIAUR 0x0204c
54#define PCIEMSIIER 0x02050
55
56/* root port address */
57#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59/* local address reg & mask */
60#define PCIELAR(x) (0x02200 + ((x) * 0x20))
61#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62#define LAM_PREFETCH (1 << 3)
63#define LAM_64BIT (1 << 2)
64#define LAR_ENABLE (1 << 1)
65
66/* PCIe address reg & mask */
67#define PCIEPARL(x) (0x03400 + ((x) * 0x20))
68#define PCIEPARH(x) (0x03404 + ((x) * 0x20))
69#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71#define PAR_ENABLE (1 << 31)
72#define IO_SPACE (1 << 8)
73
74/* Configuration */
75#define PCICONF(x) (0x010000 + ((x) * 0x4))
76#define PMCAP(x) (0x010040 + ((x) * 0x4))
77#define EXPCAP(x) (0x010070 + ((x) * 0x4))
78#define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80/* link layer */
81#define IDSETR1 0x011004
82#define TLCTLR 0x011048
83#define MACSR 0x011054
84#define MACCTLR 0x011058
85#define SCRAMBLE_DISABLE (1 << 27)
86
87/* R-Car H1 PHY */
88#define H1_PCIEPHYADRR 0x04000c
89#define WRITE_CMD (1 << 16)
90#define PHY_ACK (1 << 24)
91#define RATE_POS 12
92#define LANE_POS 8
93#define ADR_POS 0
94#define H1_PCIEPHYDOUTR 0x040014
95#define H1_PCIEPHYSR 0x040018
96
97#define INT_PCI_MSI_NR 32
98
99#define RCONF(x) (PCICONF(0)+(x))
100#define RPMCAP(x) (PMCAP(0)+(x))
101#define REXPCAP(x) (EXPCAP(0)+(x))
102#define RVCCAP(x) (VCCAP(0)+(x))
103
104#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108#define PCI_MAX_RESOURCES 4
109#define MAX_NR_INBOUND_MAPS 6
110
111struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_chip chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119};
120
121static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
122{
123 return container_of(chip, struct rcar_msi, chip);
124}
125
126/* Structure representing the PCIe interface */
127struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
130 struct resource res[PCI_MAX_RESOURCES];
131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
135 struct rcar_msi msi;
136};
137
138static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139{
140 return sys->private_data;
141}
142
143static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145{
146 writel(val, pcie->base + reg);
147}
148
149static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
150{
151 return readl(pcie->base + reg);
152}
153
154enum {
155 PCI_ACCESS_READ,
156 PCI_ACCESS_WRITE,
157};
158
159static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
160{
161 int shift = 8 * (where & 3);
162 u32 val = pci_read_reg(pcie, where & ~3);
163
164 val &= ~(mask << shift);
165 val |= data << shift;
166 pci_write_reg(pcie, val, where & ~3);
167}
168
169static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
170{
171 int shift = 8 * (where & 3);
172 u32 val = pci_read_reg(pcie, where & ~3);
173
174 return val >> shift;
175}
176
177/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
178static int rcar_pcie_config_access(struct rcar_pcie *pcie,
179 unsigned char access_type, struct pci_bus *bus,
180 unsigned int devfn, int where, u32 *data)
181{
182 int dev, func, reg, index;
183
184 dev = PCI_SLOT(devfn);
185 func = PCI_FUNC(devfn);
186 reg = where & ~3;
187 index = reg / 4;
188
189 /*
190 * While each channel has its own memory-mapped extended config
191 * space, it's generally only accessible when in endpoint mode.
192 * When in root complex mode, the controller is unable to target
193 * itself with either type 0 or type 1 accesses, and indeed, any
194 * controller initiated target transfer to its own config space
195 * result in a completer abort.
196 *
197 * Each channel effectively only supports a single device, but as
198 * the same channel <-> device access works for any PCI_SLOT()
199 * value, we cheat a bit here and bind the controller's config
200 * space to devfn 0 in order to enable self-enumeration. In this
201 * case the regular ECAR/ECDR path is sidelined and the mangled
202 * config access itself is initiated as an internal bus transaction.
203 */
204 if (pci_is_root_bus(bus)) {
205 if (dev != 0)
206 return PCIBIOS_DEVICE_NOT_FOUND;
207
208 if (access_type == PCI_ACCESS_READ) {
209 *data = pci_read_reg(pcie, PCICONF(index));
210 } else {
211 /* Keep an eye out for changes to the root bus number */
212 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
213 pcie->root_bus_nr = *data & 0xff;
214
215 pci_write_reg(pcie, *data, PCICONF(index));
216 }
217
218 return PCIBIOS_SUCCESSFUL;
219 }
220
221 if (pcie->root_bus_nr < 0)
222 return PCIBIOS_DEVICE_NOT_FOUND;
223
224 /* Clear errors */
225 pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
226
227 /* Set the PIO address */
228 pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
229 PCIE_CONF_FUNC(func) | reg, PCIECAR);
230
231 /* Enable the configuration access */
232 if (bus->parent->number == pcie->root_bus_nr)
233 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
234 else
235 pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
236
237 /* Check for errors */
238 if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 /* Check for master and target aborts */
242 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
243 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
244 return PCIBIOS_DEVICE_NOT_FOUND;
245
246 if (access_type == PCI_ACCESS_READ)
247 *data = pci_read_reg(pcie, PCIECDR);
248 else
249 pci_write_reg(pcie, *data, PCIECDR);
250
251 /* Disable the configuration access */
252 pci_write_reg(pcie, 0, PCIECCTLR);
253
254 return PCIBIOS_SUCCESSFUL;
255}
256
257static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
258 int where, int size, u32 *val)
259{
260 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
261 int ret;
262
263 if ((size == 2) && (where & 1))
264 return PCIBIOS_BAD_REGISTER_NUMBER;
265 else if ((size == 4) && (where & 3))
266 return PCIBIOS_BAD_REGISTER_NUMBER;
267
268 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
269 bus, devfn, where, val);
270 if (ret != PCIBIOS_SUCCESSFUL) {
271 *val = 0xffffffff;
272 return ret;
273 }
274
275 if (size == 1)
276 *val = (*val >> (8 * (where & 3))) & 0xff;
277 else if (size == 2)
278 *val = (*val >> (8 * (where & 2))) & 0xffff;
279
280 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
281 "where=0x%04x size=%d val=0x%08lx\n", bus->number,
282 devfn, where, size, (unsigned long)*val);
283
284 return ret;
285}
286
287/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
288static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
289 int where, int size, u32 val)
290{
291 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
292 int shift, ret;
293 u32 data;
294
295 if ((size == 2) && (where & 1))
296 return PCIBIOS_BAD_REGISTER_NUMBER;
297 else if ((size == 4) && (where & 3))
298 return PCIBIOS_BAD_REGISTER_NUMBER;
299
300 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
301 bus, devfn, where, &data);
302 if (ret != PCIBIOS_SUCCESSFUL)
303 return ret;
304
305 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
306 "where=0x%04x size=%d val=0x%08lx\n", bus->number,
307 devfn, where, size, (unsigned long)val);
308
309 if (size == 1) {
310 shift = 8 * (where & 3);
311 data &= ~(0xff << shift);
312 data |= ((val & 0xff) << shift);
313 } else if (size == 2) {
314 shift = 8 * (where & 2);
315 data &= ~(0xffff << shift);
316 data |= ((val & 0xffff) << shift);
317 } else
318 data = val;
319
320 ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
321 bus, devfn, where, &data);
322
323 return ret;
324}
325
326static struct pci_ops rcar_pcie_ops = {
327 .read = rcar_pcie_read_conf,
328 .write = rcar_pcie_write_conf,
329};
330
331static void rcar_pcie_setup_window(int win, struct resource *res,
332 struct rcar_pcie *pcie)
333{
334 /* Setup PCIe address space mappings for each resource */
335 resource_size_t size;
336 u32 mask;
337
338 pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
339
340 /*
341 * The PAMR mask is calculated in units of 128Bytes, which
342 * keeps things pretty simple.
343 */
344 size = resource_size(res);
345 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
346 pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
347
348 pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
349 pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
350
351 /* First resource is for IO */
352 mask = PAR_ENABLE;
353 if (res->flags & IORESOURCE_IO)
354 mask |= IO_SPACE;
355
356 pci_write_reg(pcie, mask, PCIEPTCTLR(win));
357}
358
359static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
360{
361 struct rcar_pcie *pcie = sys_to_pcie(sys);
362 struct resource *res;
363 int i;
364
365 pcie->root_bus_nr = -1;
366
367 /* Setup PCI resources */
368 for (i = 0; i < PCI_MAX_RESOURCES; i++) {
369
370 res = &pcie->res[i];
371 if (!res->flags)
372 continue;
373
374 rcar_pcie_setup_window(i, res, pcie);
375
376 if (res->flags & IORESOURCE_IO)
377 pci_ioremap_io(nr * SZ_64K, res->start);
378 else
379 pci_add_resource(&sys->resources, res);
380 }
381 pci_add_resource(&sys->resources, &pcie->busn);
382
383 return 1;
384}
385
386static void rcar_pcie_add_bus(struct pci_bus *bus)
387{
388 if (IS_ENABLED(CONFIG_PCI_MSI)) {
389 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
390
391 bus->msi = &pcie->msi.chip;
392 }
393}
394
395struct hw_pci rcar_pci = {
396 .setup = rcar_pcie_setup,
397 .map_irq = of_irq_parse_and_map_pci,
398 .ops = &rcar_pcie_ops,
399 .add_bus = rcar_pcie_add_bus,
400};
401
402static void rcar_pcie_enable(struct rcar_pcie *pcie)
403{
404 struct platform_device *pdev = to_platform_device(pcie->dev);
405
406 rcar_pci.nr_controllers = 1;
407 rcar_pci.private_data = (void **)&pcie;
408
409 pci_common_init_dev(&pdev->dev, &rcar_pci);
410#ifdef CONFIG_PCI_DOMAINS
411 rcar_pci.domain++;
412#endif
413}
414
415static int phy_wait_for_ack(struct rcar_pcie *pcie)
416{
417 unsigned int timeout = 100;
418
419 while (timeout--) {
420 if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
421 return 0;
422
423 udelay(100);
424 }
425
426 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
427
428 return -ETIMEDOUT;
429}
430
431static void phy_write_reg(struct rcar_pcie *pcie,
432 unsigned int rate, unsigned int addr,
433 unsigned int lane, unsigned int data)
434{
435 unsigned long phyaddr;
436
437 phyaddr = WRITE_CMD |
438 ((rate & 1) << RATE_POS) |
439 ((lane & 0xf) << LANE_POS) |
440 ((addr & 0xff) << ADR_POS);
441
442 /* Set write data */
443 pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
444 pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
445
446 /* Ignore errors as they will be dealt with if the data link is down */
447 phy_wait_for_ack(pcie);
448
449 /* Clear command */
450 pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
451 pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
452
453 /* Ignore errors as they will be dealt with if the data link is down */
454 phy_wait_for_ack(pcie);
455}
456
457static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
458{
459 unsigned int timeout = 10;
460
461 while (timeout--) {
462 if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
463 return 0;
464
465 msleep(5);
466 }
467
468 return -ETIMEDOUT;
469}
470
471static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
472{
473 int err;
474
475 /* Begin initialization */
476 pci_write_reg(pcie, 0, PCIETCTLR);
477
478 /* Set mode */
479 pci_write_reg(pcie, 1, PCIEMSR);
480
481 /*
482 * Initial header for port config space is type 1, set the device
483 * class to match. Hardware takes care of propagating the IDSETR
484 * settings, so there is no need to bother with a quirk.
485 */
486 pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
487
488 /*
489 * Setup Secondary Bus Number & Subordinate Bus Number, even though
490 * they aren't used, to avoid bridge being detected as broken.
491 */
492 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
493 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
494
495 /* Initialize default capabilities. */
496 rcar_rmw32(pcie, REXPCAP(0), 0, PCI_CAP_ID_EXP);
497 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
498 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
499 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
500 PCI_HEADER_TYPE_BRIDGE);
501
502 /* Enable data link layer active state reporting */
503 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), 0, PCI_EXP_LNKCAP_DLLLARC);
504
505 /* Write out the physical slot number = 0 */
506 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
507
508 /* Set the completion timer timeout to the maximum 50ms. */
509 rcar_rmw32(pcie, TLCTLR+1, 0x3f, 50);
510
511 /* Terminate list of capabilities (Next Capability Offset=0) */
512 rcar_rmw32(pcie, RVCCAP(0), 0xfff0, 0);
513
514 /* Enable MAC data scrambling. */
515 rcar_rmw32(pcie, MACCTLR, SCRAMBLE_DISABLE, 0);
516
517 /* Enable MSI */
518 if (IS_ENABLED(CONFIG_PCI_MSI))
519 pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
520
521 /* Finish initialization - establish a PCI Express link */
522 pci_write_reg(pcie, CFINIT, PCIETCTLR);
523
524 /* This will timeout if we don't have a link. */
525 err = rcar_pcie_wait_for_dl(pcie);
526 if (err)
527 return err;
528
529 /* Enable INTx interrupts */
530 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
531
532 /* Enable slave Bus Mastering */
533 rcar_rmw32(pcie, RCONF(PCI_STATUS), PCI_STATUS_DEVSEL_MASK,
534 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
535 PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST);
536
537 wmb();
538
539 return 0;
540}
541
542static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
543{
544 unsigned int timeout = 10;
545
546 /* Initialize the phy */
547 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
548 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
549 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
550 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
551 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
552 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
553 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
554 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
555 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
556 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
557 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
558 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
559
560 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
561 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
562 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
563
564 while (timeout--) {
565 if (pci_read_reg(pcie, H1_PCIEPHYSR))
566 return rcar_pcie_hw_init(pcie);
567
568 msleep(5);
569 }
570
571 return -ETIMEDOUT;
572}
573
574static int rcar_msi_alloc(struct rcar_msi *chip)
575{
576 int msi;
577
578 mutex_lock(&chip->lock);
579
580 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
581 if (msi < INT_PCI_MSI_NR)
582 set_bit(msi, chip->used);
583 else
584 msi = -ENOSPC;
585
586 mutex_unlock(&chip->lock);
587
588 return msi;
589}
590
591static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
592{
593 mutex_lock(&chip->lock);
594 clear_bit(irq, chip->used);
595 mutex_unlock(&chip->lock);
596}
597
598static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
599{
600 struct rcar_pcie *pcie = data;
601 struct rcar_msi *msi = &pcie->msi;
602 unsigned long reg;
603
604 reg = pci_read_reg(pcie, PCIEMSIFR);
605
606 /* MSI & INTx share an interrupt - we only handle MSI here */
607 if (!reg)
608 return IRQ_NONE;
609
610 while (reg) {
611 unsigned int index = find_first_bit(&reg, 32);
612 unsigned int irq;
613
614 /* clear the interrupt */
615 pci_write_reg(pcie, 1 << index, PCIEMSIFR);
616
617 irq = irq_find_mapping(msi->domain, index);
618 if (irq) {
619 if (test_bit(index, msi->used))
620 generic_handle_irq(irq);
621 else
622 dev_info(pcie->dev, "unhandled MSI\n");
623 } else {
624 /* Unknown MSI, just clear it */
625 dev_dbg(pcie->dev, "unexpected MSI\n");
626 }
627
628 /* see if there's any more pending in this vector */
629 reg = pci_read_reg(pcie, PCIEMSIFR);
630 }
631
632 return IRQ_HANDLED;
633}
634
635static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
636 struct msi_desc *desc)
637{
638 struct rcar_msi *msi = to_rcar_msi(chip);
639 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
640 struct msi_msg msg;
641 unsigned int irq;
642 int hwirq;
643
644 hwirq = rcar_msi_alloc(msi);
645 if (hwirq < 0)
646 return hwirq;
647
648 irq = irq_create_mapping(msi->domain, hwirq);
649 if (!irq) {
650 rcar_msi_free(msi, hwirq);
651 return -EINVAL;
652 }
653
654 irq_set_msi_desc(irq, desc);
655
656 msg.address_lo = pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
657 msg.address_hi = pci_read_reg(pcie, PCIEMSIAUR);
658 msg.data = hwirq;
659
660 write_msi_msg(irq, &msg);
661
662 return 0;
663}
664
665static void rcar_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
666{
667 struct rcar_msi *msi = to_rcar_msi(chip);
668 struct irq_data *d = irq_get_irq_data(irq);
669
670 rcar_msi_free(msi, d->hwirq);
671}
672
673static struct irq_chip rcar_msi_irq_chip = {
674 .name = "R-Car PCIe MSI",
675 .irq_enable = unmask_msi_irq,
676 .irq_disable = mask_msi_irq,
677 .irq_mask = mask_msi_irq,
678 .irq_unmask = unmask_msi_irq,
679};
680
681static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
682 irq_hw_number_t hwirq)
683{
684 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
685 irq_set_chip_data(irq, domain->host_data);
686 set_irq_flags(irq, IRQF_VALID);
687
688 return 0;
689}
690
691static const struct irq_domain_ops msi_domain_ops = {
692 .map = rcar_msi_map,
693};
694
695static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
696{
697 struct platform_device *pdev = to_platform_device(pcie->dev);
698 struct rcar_msi *msi = &pcie->msi;
699 unsigned long base;
700 int err;
701
702 mutex_init(&msi->lock);
703
704 msi->chip.dev = pcie->dev;
705 msi->chip.setup_irq = rcar_msi_setup_irq;
706 msi->chip.teardown_irq = rcar_msi_teardown_irq;
707
708 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
709 &msi_domain_ops, &msi->chip);
710 if (!msi->domain) {
711 dev_err(&pdev->dev, "failed to create IRQ domain\n");
712 return -ENOMEM;
713 }
714
715 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
716 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
717 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
718 if (err < 0) {
719 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
720 goto err;
721 }
722
723 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
724 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
725 if (err < 0) {
726 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
727 goto err;
728 }
729
730 /* setup MSI data target */
731 msi->pages = __get_free_pages(GFP_KERNEL, 0);
732 base = virt_to_phys((void *)msi->pages);
733
734 pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
735 pci_write_reg(pcie, 0, PCIEMSIAUR);
736
737 /* enable all MSI interrupts */
738 pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
739
740 return 0;
741
742err:
743 irq_domain_remove(msi->domain);
744 return err;
745}
746
747static int rcar_pcie_get_resources(struct platform_device *pdev,
748 struct rcar_pcie *pcie)
749{
750 struct resource res;
751 int err, i;
752
753 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
754 if (err)
755 return err;
756
757 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
758 if (IS_ERR(pcie->clk)) {
759 dev_err(pcie->dev, "cannot get platform clock\n");
760 return PTR_ERR(pcie->clk);
761 }
762 err = clk_prepare_enable(pcie->clk);
763 if (err)
764 goto fail_clk;
765
766 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
767 if (IS_ERR(pcie->bus_clk)) {
768 dev_err(pcie->dev, "cannot get pcie bus clock\n");
769 err = PTR_ERR(pcie->bus_clk);
770 goto fail_clk;
771 }
772 err = clk_prepare_enable(pcie->bus_clk);
773 if (err)
774 goto err_map_reg;
775
776 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
777 if (i < 0) {
778 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
779 err = -ENOENT;
780 goto err_map_reg;
781 }
782 pcie->msi.irq1 = i;
783
784 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
785 if (i < 0) {
786 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
787 err = -ENOENT;
788 goto err_map_reg;
789 }
790 pcie->msi.irq2 = i;
791
792 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
793 if (IS_ERR(pcie->base)) {
794 err = PTR_ERR(pcie->base);
795 goto err_map_reg;
796 }
797
798 return 0;
799
800err_map_reg:
801 clk_disable_unprepare(pcie->bus_clk);
802fail_clk:
803 clk_disable_unprepare(pcie->clk);
804
805 return err;
806}
807
808static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
809 struct of_pci_range *range,
810 int *index)
811{
812 u64 restype = range->flags;
813 u64 cpu_addr = range->cpu_addr;
814 u64 cpu_end = range->cpu_addr + range->size;
815 u64 pci_addr = range->pci_addr;
816 u32 flags = LAM_64BIT | LAR_ENABLE;
817 u64 mask;
818 u64 size;
819 int idx = *index;
820
821 if (restype & IORESOURCE_PREFETCH)
822 flags |= LAM_PREFETCH;
823
824 /*
825 * If the size of the range is larger than the alignment of the start
826 * address, we have to use multiple entries to perform the mapping.
827 */
828 if (cpu_addr > 0) {
829 unsigned long nr_zeros = __ffs64(cpu_addr);
830 u64 alignment = 1ULL << nr_zeros;
831 size = min(range->size, alignment);
832 } else {
833 size = range->size;
834 }
835 /* Hardware supports max 4GiB inbound region */
836 size = min(size, 1ULL << 32);
837
838 mask = roundup_pow_of_two(size) - 1;
839 mask &= ~0xf;
840
841 while (cpu_addr < cpu_end) {
842 /*
843 * Set up 64-bit inbound regions as the range parser doesn't
844 * distinguish between 32 and 64-bit types.
845 */
846 pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
847 pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
848 pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
849
850 pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
851 pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
852 pci_write_reg(pcie, 0, PCIELAMR(idx+1));
853
854 pci_addr += size;
855 cpu_addr += size;
856 idx += 2;
857
858 if (idx > MAX_NR_INBOUND_MAPS) {
859 dev_err(pcie->dev, "Failed to map inbound regions!\n");
860 return -EINVAL;
861 }
862 }
863 *index = idx;
864
865 return 0;
866}
867
868static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
869 struct device_node *node)
870{
871 const int na = 3, ns = 2;
872 int rlen;
873
874 parser->node = node;
875 parser->pna = of_n_addr_cells(node);
876 parser->np = parser->pna + na + ns;
877
878 parser->range = of_get_property(node, "dma-ranges", &rlen);
879 if (!parser->range)
880 return -ENOENT;
881
882 parser->end = parser->range + rlen / sizeof(__be32);
883 return 0;
884}
885
886static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
887 struct device_node *np)
888{
889 struct of_pci_range range;
890 struct of_pci_range_parser parser;
891 int index = 0;
892 int err;
893
894 if (pci_dma_range_parser_init(&parser, np))
895 return -EINVAL;
896
897 /* Get the dma-ranges from DT */
898 for_each_of_pci_range(&parser, &range) {
899 u64 end = range.cpu_addr + range.size - 1;
900 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
901 range.flags, range.cpu_addr, end, range.pci_addr);
902
903 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
904 if (err)
905 return err;
906 }
907
908 return 0;
909}
910
911static const struct of_device_id rcar_pcie_of_match[] = {
912 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
913 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
914 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
915 {},
916};
917MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
918
919static int rcar_pcie_probe(struct platform_device *pdev)
920{
921 struct rcar_pcie *pcie;
922 unsigned int data;
923 struct of_pci_range range;
924 struct of_pci_range_parser parser;
925 const struct of_device_id *of_id;
926 int err, win = 0;
927 int (*hw_init_fn)(struct rcar_pcie *);
928
929 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
930 if (!pcie)
931 return -ENOMEM;
932
933 pcie->dev = &pdev->dev;
934 platform_set_drvdata(pdev, pcie);
935
936 /* Get the bus range */
937 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
938 dev_err(&pdev->dev, "failed to parse bus-range property\n");
939 return -EINVAL;
940 }
941
942 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
943 dev_err(&pdev->dev, "missing ranges property\n");
944 return -EINVAL;
945 }
946
947 err = rcar_pcie_get_resources(pdev, pcie);
948 if (err < 0) {
949 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
950 return err;
951 }
952
953 for_each_of_pci_range(&parser, &range) {
954 of_pci_range_to_resource(&range, pdev->dev.of_node,
955 &pcie->res[win++]);
956
957 if (win > PCI_MAX_RESOURCES)
958 break;
959 }
960
961 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
962 if (err)
963 return err;
964
965 if (IS_ENABLED(CONFIG_PCI_MSI)) {
966 err = rcar_pcie_enable_msi(pcie);
967 if (err < 0) {
968 dev_err(&pdev->dev,
969 "failed to enable MSI support: %d\n",
970 err);
971 return err;
972 }
973 }
974
975 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
976 if (!of_id || !of_id->data)
977 return -EINVAL;
978 hw_init_fn = of_id->data;
979
980 /* Failure to get a link might just be that no cards are inserted */
981 err = hw_init_fn(pcie);
982 if (err) {
983 dev_info(&pdev->dev, "PCIe link down\n");
984 return 0;
985 }
986
987 data = pci_read_reg(pcie, MACSR);
988 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
989
990 rcar_pcie_enable(pcie);
991
992 return 0;
993}
994
995static struct platform_driver rcar_pcie_driver = {
996 .driver = {
997 .name = DRV_NAME,
998 .owner = THIS_MODULE,
999 .of_match_table = rcar_pcie_of_match,
1000 .suppress_bind_attrs = true,
1001 },
1002 .probe = rcar_pcie_probe,
1003};
1004module_platform_driver(rcar_pcie_driver);
1005
1006MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1007MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1008MODULE_LICENSE("GPLv2");
diff --git a/drivers/pci/hotplug-pci.c b/drivers/pci/hotplug-pci.c
index 6258dc260d9f..c68366cee6b7 100644
--- a/drivers/pci/hotplug-pci.c
+++ b/drivers/pci/hotplug-pci.c
@@ -4,7 +4,7 @@
4#include <linux/export.h> 4#include <linux/export.h>
5#include "pci.h" 5#include "pci.h"
6 6
7int __ref pci_hp_add_bridge(struct pci_dev *dev) 7int pci_hp_add_bridge(struct pci_dev *dev)
8{ 8{
9 struct pci_bus *parent = dev->bus; 9 struct pci_bus *parent = dev->bus;
10 int pass, busnr, start = parent->busn_res.start; 10 int pass, busnr, start = parent->busn_res.start;
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index bccc27ee1030..75e178330215 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -41,7 +41,6 @@
41 41
42#define pr_fmt(fmt) "acpiphp_glue: " fmt 42#define pr_fmt(fmt) "acpiphp_glue: " fmt
43 43
44#include <linux/init.h>
45#include <linux/module.h> 44#include <linux/module.h>
46 45
47#include <linux/kernel.h> 46#include <linux/kernel.h>
@@ -501,7 +500,7 @@ static int acpiphp_rescan_slot(struct acpiphp_slot *slot)
501 * This function should be called per *physical slot*, 500 * This function should be called per *physical slot*,
502 * not per each slot object in ACPI namespace. 501 * not per each slot object in ACPI namespace.
503 */ 502 */
504static void __ref enable_slot(struct acpiphp_slot *slot) 503static void enable_slot(struct acpiphp_slot *slot)
505{ 504{
506 struct pci_dev *dev; 505 struct pci_dev *dev;
507 struct pci_bus *bus = slot->bus; 506 struct pci_bus *bus = slot->bus;
@@ -516,8 +515,7 @@ static void __ref enable_slot(struct acpiphp_slot *slot)
516 if (PCI_SLOT(dev->devfn) != slot->device) 515 if (PCI_SLOT(dev->devfn) != slot->device)
517 continue; 516 continue;
518 517
519 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 518 if (pci_is_bridge(dev)) {
520 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
521 max = pci_scan_bridge(bus, dev, max, pass); 519 max = pci_scan_bridge(bus, dev, max, pass);
522 if (pass && dev->subordinate) { 520 if (pass && dev->subordinate) {
523 check_hotplug_bridge(slot, dev); 521 check_hotplug_bridge(slot, dev);
diff --git a/drivers/pci/hotplug/cpci_hotplug_pci.c b/drivers/pci/hotplug/cpci_hotplug_pci.c
index 8c1464851768..f6ef64c2ccb5 100644
--- a/drivers/pci/hotplug/cpci_hotplug_pci.c
+++ b/drivers/pci/hotplug/cpci_hotplug_pci.c
@@ -250,7 +250,7 @@ int cpci_led_off(struct slot* slot)
250 * Device configuration functions 250 * Device configuration functions
251 */ 251 */
252 252
253int __ref cpci_configure_slot(struct slot *slot) 253int cpci_configure_slot(struct slot *slot)
254{ 254{
255 struct pci_dev *dev; 255 struct pci_dev *dev;
256 struct pci_bus *parent; 256 struct pci_bus *parent;
@@ -289,8 +289,7 @@ int __ref cpci_configure_slot(struct slot *slot)
289 list_for_each_entry(dev, &parent->devices, bus_list) 289 list_for_each_entry(dev, &parent->devices, bus_list)
290 if (PCI_SLOT(dev->devfn) != PCI_SLOT(slot->devfn)) 290 if (PCI_SLOT(dev->devfn) != PCI_SLOT(slot->devfn))
291 continue; 291 continue;
292 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 292 if (pci_is_bridge(dev))
293 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
294 pci_hp_add_bridge(dev); 293 pci_hp_add_bridge(dev);
295 294
296 295
diff --git a/drivers/pci/hotplug/cpqphp_ctrl.c b/drivers/pci/hotplug/cpqphp_ctrl.c
index 11845b796799..f593585f2784 100644
--- a/drivers/pci/hotplug/cpqphp_ctrl.c
+++ b/drivers/pci/hotplug/cpqphp_ctrl.c
@@ -709,7 +709,8 @@ static struct pci_resource *get_max_resource(struct pci_resource **head, u32 siz
709 temp = temp->next; 709 temp = temp->next;
710 } 710 }
711 711
712 temp->next = max->next; 712 if (temp)
713 temp->next = max->next;
713 } 714 }
714 715
715 max->next = NULL; 716 max->next = NULL;
diff --git a/drivers/pci/hotplug/cpqphp_nvram.c b/drivers/pci/hotplug/cpqphp_nvram.c
index 76ba8a1c774d..9600a392eaae 100644
--- a/drivers/pci/hotplug/cpqphp_nvram.c
+++ b/drivers/pci/hotplug/cpqphp_nvram.c
@@ -34,7 +34,6 @@
34#include <linux/workqueue.h> 34#include <linux/workqueue.h>
35#include <linux/pci.h> 35#include <linux/pci.h>
36#include <linux/pci_hotplug.h> 36#include <linux/pci_hotplug.h>
37#include <linux/init.h>
38#include <asm/uaccess.h> 37#include <asm/uaccess.h>
39#include "cpqphp.h" 38#include "cpqphp.h"
40#include "cpqphp_nvram.h" 39#include "cpqphp_nvram.h"
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 8a66866b8cf1..8e9012dca450 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -127,7 +127,7 @@ struct controller {
127#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS) 127#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
128#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP) 128#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
129#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS) 129#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
130#define PSN(ctrl) ((ctrl)->slot_cap >> 19) 130#define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
131 131
132int pciehp_sysfs_enable_slot(struct slot *slot); 132int pciehp_sysfs_enable_slot(struct slot *slot);
133int pciehp_sysfs_disable_slot(struct slot *slot); 133int pciehp_sysfs_disable_slot(struct slot *slot);
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index d7d058fa19a4..1463412cf7f8 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -159,6 +159,8 @@ static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
159 159
160 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 160 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
161 if (slot_status & PCI_EXP_SLTSTA_CC) { 161 if (slot_status & PCI_EXP_SLTSTA_CC) {
162 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
163 PCI_EXP_SLTSTA_CC);
162 if (!ctrl->no_cmd_complete) { 164 if (!ctrl->no_cmd_complete) {
163 /* 165 /*
164 * After 1 sec and CMD_COMPLETED still not set, just 166 * After 1 sec and CMD_COMPLETED still not set, just
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index 1b533060ce65..b6cb1df67097 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -62,8 +62,7 @@ int pciehp_configure_device(struct slot *p_slot)
62 } 62 }
63 63
64 list_for_each_entry(dev, &parent->devices, bus_list) 64 list_for_each_entry(dev, &parent->devices, bus_list)
65 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 65 if (pci_is_bridge(dev))
66 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
67 pci_hp_add_bridge(dev); 66 pci_hp_add_bridge(dev);
68 67
69 pci_assign_unassigned_bridge_resources(bridge); 68 pci_assign_unassigned_bridge_resources(bridge);
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
index 16f920352317..e246a10a0d2c 100644
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ b/drivers/pci/hotplug/pcihp_slot.c
@@ -160,8 +160,7 @@ void pci_configure_slot(struct pci_dev *dev)
160 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) 160 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
161 return; 161 return;
162 162
163 if (dev->bus) 163 pcie_bus_configure_settings(dev->bus);
164 pcie_bus_configure_settings(dev->bus);
165 164
166 memset(&hpp, 0, sizeof(hpp)); 165 memset(&hpp, 0, sizeof(hpp));
167 ret = pci_get_hp_params(dev, &hpp); 166 ret = pci_get_hp_params(dev, &hpp);
diff --git a/drivers/pci/hotplug/rpadlpar_core.c b/drivers/pci/hotplug/rpadlpar_core.c
index 4fcdeedda31b..7660232ef460 100644
--- a/drivers/pci/hotplug/rpadlpar_core.c
+++ b/drivers/pci/hotplug/rpadlpar_core.c
@@ -157,8 +157,7 @@ static void dlpar_pci_add_bus(struct device_node *dn)
157 } 157 }
158 158
159 /* Scan below the new bridge */ 159 /* Scan below the new bridge */
160 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 160 if (pci_is_bridge(dev))
161 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
162 of_scan_pci_bridge(dev); 161 of_scan_pci_bridge(dev);
163 162
164 /* Map IO space for child bus, which may or may not succeed */ 163 /* Map IO space for child bus, which may or may not succeed */
diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
index 4796c15fba94..984d708552f6 100644
--- a/drivers/pci/hotplug/rpaphp_core.c
+++ b/drivers/pci/hotplug/rpaphp_core.c
@@ -223,16 +223,16 @@ int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
223 type_tmp = (char *) &types[1]; 223 type_tmp = (char *) &types[1];
224 224
225 /* Iterate through parent properties, looking for my-drc-index */ 225 /* Iterate through parent properties, looking for my-drc-index */
226 for (i = 0; i < indexes[0]; i++) { 226 for (i = 0; i < be32_to_cpu(indexes[0]); i++) {
227 if ((unsigned int) indexes[i + 1] == *my_index) { 227 if ((unsigned int) indexes[i + 1] == *my_index) {
228 if (drc_name) 228 if (drc_name)
229 *drc_name = name_tmp; 229 *drc_name = name_tmp;
230 if (drc_type) 230 if (drc_type)
231 *drc_type = type_tmp; 231 *drc_type = type_tmp;
232 if (drc_index) 232 if (drc_index)
233 *drc_index = *my_index; 233 *drc_index = be32_to_cpu(*my_index);
234 if (drc_power_domain) 234 if (drc_power_domain)
235 *drc_power_domain = domains[i+1]; 235 *drc_power_domain = be32_to_cpu(domains[i+1]);
236 return 0; 236 return 0;
237 } 237 }
238 name_tmp += (strlen(name_tmp) + 1); 238 name_tmp += (strlen(name_tmp) + 1);
@@ -321,16 +321,19 @@ int rpaphp_add_slot(struct device_node *dn)
321 /* register PCI devices */ 321 /* register PCI devices */
322 name = (char *) &names[1]; 322 name = (char *) &names[1];
323 type = (char *) &types[1]; 323 type = (char *) &types[1];
324 for (i = 0; i < indexes[0]; i++) { 324 for (i = 0; i < be32_to_cpu(indexes[0]); i++) {
325 int index;
325 326
326 slot = alloc_slot_struct(dn, indexes[i + 1], name, power_domains[i + 1]); 327 index = be32_to_cpu(indexes[i + 1]);
328 slot = alloc_slot_struct(dn, index, name,
329 be32_to_cpu(power_domains[i + 1]));
327 if (!slot) 330 if (!slot)
328 return -ENOMEM; 331 return -ENOMEM;
329 332
330 slot->type = simple_strtoul(type, NULL, 10); 333 slot->type = simple_strtoul(type, NULL, 10);
331 334
332 dbg("Found drc-index:0x%x drc-name:%s drc-type:%s\n", 335 dbg("Found drc-index:0x%x drc-name:%s drc-type:%s\n",
333 indexes[i + 1], name, type); 336 index, name, type);
334 337
335 retval = rpaphp_enable_slot(slot); 338 retval = rpaphp_enable_slot(slot);
336 if (!retval) 339 if (!retval)
diff --git a/drivers/pci/hotplug/s390_pci_hpc.c b/drivers/pci/hotplug/s390_pci_hpc.c
index 8d2ce22151eb..d1332d2f8730 100644
--- a/drivers/pci/hotplug/s390_pci_hpc.c
+++ b/drivers/pci/hotplug/s390_pci_hpc.c
@@ -15,7 +15,6 @@
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/pci.h> 16#include <linux/pci.h>
17#include <linux/pci_hotplug.h> 17#include <linux/pci_hotplug.h>
18#include <linux/init.h>
19#include <asm/pci_debug.h> 18#include <asm/pci_debug.h>
20#include <asm/sclp.h> 19#include <asm/sclp.h>
21 20
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index 2bf69fe1926c..9202d133485c 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -34,7 +34,7 @@
34#include "../pci.h" 34#include "../pci.h"
35#include "shpchp.h" 35#include "shpchp.h"
36 36
37int __ref shpchp_configure_device(struct slot *p_slot) 37int shpchp_configure_device(struct slot *p_slot)
38{ 38{
39 struct pci_dev *dev; 39 struct pci_dev *dev;
40 struct controller *ctrl = p_slot->ctrl; 40 struct controller *ctrl = p_slot->ctrl;
@@ -64,8 +64,7 @@ int __ref shpchp_configure_device(struct slot *p_slot)
64 list_for_each_entry(dev, &parent->devices, bus_list) { 64 list_for_each_entry(dev, &parent->devices, bus_list) {
65 if (PCI_SLOT(dev->devfn) != p_slot->device) 65 if (PCI_SLOT(dev->devfn) != p_slot->device)
66 continue; 66 continue;
67 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 67 if (pci_is_bridge(dev))
68 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
69 pci_hp_add_bridge(dev); 68 pci_hp_add_bridge(dev);
70 } 69 }
71 70
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index de7a74782f92..cb6f24740ee3 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -106,7 +106,7 @@ static int virtfn_add(struct pci_dev *dev, int id, int reset)
106 pci_device_add(virtfn, virtfn->bus); 106 pci_device_add(virtfn, virtfn->bus);
107 mutex_unlock(&iov->dev->sriov->lock); 107 mutex_unlock(&iov->dev->sriov->lock);
108 108
109 rc = pci_bus_add_device(virtfn); 109 pci_bus_add_device(virtfn);
110 sprintf(buf, "virtfn%u", id); 110 sprintf(buf, "virtfn%u", id);
111 rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf); 111 rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf);
112 if (rc) 112 if (rc)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 955ab7990c5b..27a7e67ddfe4 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -10,7 +10,6 @@
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <linux/irq.h> 11#include <linux/irq.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/export.h> 13#include <linux/export.h>
15#include <linux/ioport.h> 14#include <linux/ioport.h>
16#include <linux/pci.h> 15#include <linux/pci.h>
@@ -544,22 +543,18 @@ static int populate_msi_sysfs(struct pci_dev *pdev)
544 if (!msi_attrs) 543 if (!msi_attrs)
545 return -ENOMEM; 544 return -ENOMEM;
546 list_for_each_entry(entry, &pdev->msi_list, list) { 545 list_for_each_entry(entry, &pdev->msi_list, list) {
547 char *name = kmalloc(20, GFP_KERNEL);
548 if (!name)
549 goto error_attrs;
550
551 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); 546 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
552 if (!msi_dev_attr) { 547 if (!msi_dev_attr)
553 kfree(name);
554 goto error_attrs; 548 goto error_attrs;
555 } 549 msi_attrs[count] = &msi_dev_attr->attr;
556 550
557 sprintf(name, "%d", entry->irq);
558 sysfs_attr_init(&msi_dev_attr->attr); 551 sysfs_attr_init(&msi_dev_attr->attr);
559 msi_dev_attr->attr.name = name; 552 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
553 entry->irq);
554 if (!msi_dev_attr->attr.name)
555 goto error_attrs;
560 msi_dev_attr->attr.mode = S_IRUGO; 556 msi_dev_attr->attr.mode = S_IRUGO;
561 msi_dev_attr->show = msi_mode_show; 557 msi_dev_attr->show = msi_mode_show;
562 msi_attrs[count] = &msi_dev_attr->attr;
563 ++count; 558 ++count;
564 } 559 }
565 560
@@ -883,50 +878,6 @@ int pci_msi_vec_count(struct pci_dev *dev)
883} 878}
884EXPORT_SYMBOL(pci_msi_vec_count); 879EXPORT_SYMBOL(pci_msi_vec_count);
885 880
886/**
887 * pci_enable_msi_block - configure device's MSI capability structure
888 * @dev: device to configure
889 * @nvec: number of interrupts to configure
890 *
891 * Allocate IRQs for a device with the MSI capability.
892 * This function returns a negative errno if an error occurs. If it
893 * is unable to allocate the number of interrupts requested, it returns
894 * the number of interrupts it might be able to allocate. If it successfully
895 * allocates at least the number of interrupts requested, it returns 0 and
896 * updates the @dev's irq member to the lowest new interrupt number; the
897 * other interrupt numbers allocated to this device are consecutive.
898 */
899int pci_enable_msi_block(struct pci_dev *dev, int nvec)
900{
901 int status, maxvec;
902
903 if (dev->current_state != PCI_D0)
904 return -EINVAL;
905
906 maxvec = pci_msi_vec_count(dev);
907 if (maxvec < 0)
908 return maxvec;
909 if (nvec > maxvec)
910 return maxvec;
911
912 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
913 if (status)
914 return status;
915
916 WARN_ON(!!dev->msi_enabled);
917
918 /* Check whether driver already requested MSI-X irqs */
919 if (dev->msix_enabled) {
920 dev_info(&dev->dev, "can't enable MSI "
921 "(MSI-X already enabled)\n");
922 return -EINVAL;
923 }
924
925 status = msi_capability_init(dev, nvec);
926 return status;
927}
928EXPORT_SYMBOL(pci_enable_msi_block);
929
930void pci_msi_shutdown(struct pci_dev *dev) 881void pci_msi_shutdown(struct pci_dev *dev)
931{ 882{
932 struct msi_desc *desc; 883 struct msi_desc *desc;
@@ -1132,14 +1083,45 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
1132 **/ 1083 **/
1133int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) 1084int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1134{ 1085{
1135 int nvec = maxvec; 1086 int nvec;
1136 int rc; 1087 int rc;
1137 1088
1089 if (dev->current_state != PCI_D0)
1090 return -EINVAL;
1091
1092 WARN_ON(!!dev->msi_enabled);
1093
1094 /* Check whether driver already requested MSI-X irqs */
1095 if (dev->msix_enabled) {
1096 dev_info(&dev->dev,
1097 "can't enable MSI (MSI-X already enabled)\n");
1098 return -EINVAL;
1099 }
1100
1138 if (maxvec < minvec) 1101 if (maxvec < minvec)
1139 return -ERANGE; 1102 return -ERANGE;
1140 1103
1104 nvec = pci_msi_vec_count(dev);
1105 if (nvec < 0)
1106 return nvec;
1107 else if (nvec < minvec)
1108 return -EINVAL;
1109 else if (nvec > maxvec)
1110 nvec = maxvec;
1111
1112 do {
1113 rc = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
1114 if (rc < 0) {
1115 return rc;
1116 } else if (rc > 0) {
1117 if (rc < minvec)
1118 return -ENOSPC;
1119 nvec = rc;
1120 }
1121 } while (rc);
1122
1141 do { 1123 do {
1142 rc = pci_enable_msi_block(dev, nvec); 1124 rc = msi_capability_init(dev, nvec);
1143 if (rc < 0) { 1125 if (rc < 0) {
1144 return rc; 1126 return rc;
1145 } else if (rc > 0) { 1127 } else if (rc > 0) {
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index f49abef88485..ca4927ba8433 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -309,13 +309,7 @@ static struct acpi_device *acpi_pci_find_companion(struct device *dev)
309 bool check_children; 309 bool check_children;
310 u64 addr; 310 u64 addr;
311 311
312 /* 312 check_children = pci_is_bridge(pci_dev);
313 * pci_is_bridge() is not suitable here, because pci_dev->subordinate
314 * is set only after acpi_pci_find_device() has been called for the
315 * given device.
316 */
317 check_children = pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE
318 || pci_dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
319 /* Please ref to ACPI spec for the syntax of _ADR */ 313 /* Please ref to ACPI spec for the syntax of _ADR */
320 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn); 314 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn);
321 return acpi_find_child_device(ACPI_COMPANION(dev->parent), addr, 315 return acpi_find_child_device(ACPI_COMPANION(dev->parent), addr,
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index d911e0c1f359..837d71f5390b 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -107,7 +107,7 @@ store_new_id(struct device_driver *driver, const char *buf, size_t count)
107 subdevice=PCI_ANY_ID, class=0, class_mask=0; 107 subdevice=PCI_ANY_ID, class=0, class_mask=0;
108 unsigned long driver_data=0; 108 unsigned long driver_data=0;
109 int fields=0; 109 int fields=0;
110 int retval; 110 int retval = 0;
111 111
112 fields = sscanf(buf, "%x %x %x %x %x %x %lx", 112 fields = sscanf(buf, "%x %x %x %x %x %x %lx",
113 &vendor, &device, &subvendor, &subdevice, 113 &vendor, &device, &subvendor, &subdevice,
@@ -115,6 +115,26 @@ store_new_id(struct device_driver *driver, const char *buf, size_t count)
115 if (fields < 2) 115 if (fields < 2)
116 return -EINVAL; 116 return -EINVAL;
117 117
118 if (fields != 7) {
119 struct pci_dev *pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
120 if (!pdev)
121 return -ENOMEM;
122
123 pdev->vendor = vendor;
124 pdev->device = device;
125 pdev->subsystem_vendor = subvendor;
126 pdev->subsystem_device = subdevice;
127 pdev->class = class;
128
129 if (pci_match_id(pdrv->id_table, pdev))
130 retval = -EEXIST;
131
132 kfree(pdev);
133
134 if (retval)
135 return retval;
136 }
137
118 /* Only accept driver_data values that match an existing id_table 138 /* Only accept driver_data values that match an existing id_table
119 entry */ 139 entry */
120 if (ids) { 140 if (ids) {
@@ -216,6 +236,13 @@ const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
216 return NULL; 236 return NULL;
217} 237}
218 238
239static const struct pci_device_id pci_device_id_any = {
240 .vendor = PCI_ANY_ID,
241 .device = PCI_ANY_ID,
242 .subvendor = PCI_ANY_ID,
243 .subdevice = PCI_ANY_ID,
244};
245
219/** 246/**
220 * pci_match_device - Tell if a PCI device structure has a matching PCI device id structure 247 * pci_match_device - Tell if a PCI device structure has a matching PCI device id structure
221 * @drv: the PCI driver to match against 248 * @drv: the PCI driver to match against
@@ -229,18 +256,30 @@ static const struct pci_device_id *pci_match_device(struct pci_driver *drv,
229 struct pci_dev *dev) 256 struct pci_dev *dev)
230{ 257{
231 struct pci_dynid *dynid; 258 struct pci_dynid *dynid;
259 const struct pci_device_id *found_id = NULL;
260
261 /* When driver_override is set, only bind to the matching driver */
262 if (dev->driver_override && strcmp(dev->driver_override, drv->name))
263 return NULL;
232 264
233 /* Look at the dynamic ids first, before the static ones */ 265 /* Look at the dynamic ids first, before the static ones */
234 spin_lock(&drv->dynids.lock); 266 spin_lock(&drv->dynids.lock);
235 list_for_each_entry(dynid, &drv->dynids.list, node) { 267 list_for_each_entry(dynid, &drv->dynids.list, node) {
236 if (pci_match_one_device(&dynid->id, dev)) { 268 if (pci_match_one_device(&dynid->id, dev)) {
237 spin_unlock(&drv->dynids.lock); 269 found_id = &dynid->id;
238 return &dynid->id; 270 break;
239 } 271 }
240 } 272 }
241 spin_unlock(&drv->dynids.lock); 273 spin_unlock(&drv->dynids.lock);
242 274
243 return pci_match_id(drv->id_table, dev); 275 if (!found_id)
276 found_id = pci_match_id(drv->id_table, dev);
277
278 /* driver_override will always match, send a dummy id */
279 if (!found_id && dev->driver_override)
280 found_id = &pci_device_id_any;
281
282 return found_id;
244} 283}
245 284
246struct drv_dev_and_id { 285struct drv_dev_and_id {
@@ -580,14 +619,14 @@ static void pci_pm_default_resume(struct pci_dev *pci_dev)
580{ 619{
581 pci_fixup_device(pci_fixup_resume, pci_dev); 620 pci_fixup_device(pci_fixup_resume, pci_dev);
582 621
583 if (!pci_is_bridge(pci_dev)) 622 if (!pci_has_subordinate(pci_dev))
584 pci_enable_wake(pci_dev, PCI_D0, false); 623 pci_enable_wake(pci_dev, PCI_D0, false);
585} 624}
586 625
587static void pci_pm_default_suspend(struct pci_dev *pci_dev) 626static void pci_pm_default_suspend(struct pci_dev *pci_dev)
588{ 627{
589 /* Disable non-bridge devices without PM support */ 628 /* Disable non-bridge devices without PM support */
590 if (!pci_is_bridge(pci_dev)) 629 if (!pci_has_subordinate(pci_dev))
591 pci_disable_enabled_device(pci_dev); 630 pci_disable_enabled_device(pci_dev);
592} 631}
593 632
@@ -717,7 +756,7 @@ static int pci_pm_suspend_noirq(struct device *dev)
717 756
718 if (!pci_dev->state_saved) { 757 if (!pci_dev->state_saved) {
719 pci_save_state(pci_dev); 758 pci_save_state(pci_dev);
720 if (!pci_is_bridge(pci_dev)) 759 if (!pci_has_subordinate(pci_dev))
721 pci_prepare_to_sleep(pci_dev); 760 pci_prepare_to_sleep(pci_dev);
722 } 761 }
723 762
@@ -971,7 +1010,7 @@ static int pci_pm_poweroff_noirq(struct device *dev)
971 return error; 1010 return error;
972 } 1011 }
973 1012
974 if (!pci_dev->state_saved && !pci_is_bridge(pci_dev)) 1013 if (!pci_dev->state_saved && !pci_has_subordinate(pci_dev))
975 pci_prepare_to_sleep(pci_dev); 1014 pci_prepare_to_sleep(pci_dev);
976 1015
977 /* 1016 /*
@@ -1325,8 +1364,6 @@ static int pci_uevent(struct device *dev, struct kobj_uevent_env *env)
1325 return -ENODEV; 1364 return -ENODEV;
1326 1365
1327 pdev = to_pci_dev(dev); 1366 pdev = to_pci_dev(dev);
1328 if (!pdev)
1329 return -ENODEV;
1330 1367
1331 if (add_uevent_var(env, "PCI_CLASS=%04X", pdev->class)) 1368 if (add_uevent_var(env, "PCI_CLASS=%04X", pdev->class))
1332 return -ENOMEM; 1369 return -ENOMEM;
@@ -1347,6 +1384,7 @@ static int pci_uevent(struct device *dev, struct kobj_uevent_env *env)
1347 (u8)(pdev->class >> 16), (u8)(pdev->class >> 8), 1384 (u8)(pdev->class >> 16), (u8)(pdev->class >> 8),
1348 (u8)(pdev->class))) 1385 (u8)(pdev->class)))
1349 return -ENOMEM; 1386 return -ENOMEM;
1387
1350 return 0; 1388 return 0;
1351} 1389}
1352 1390
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 4e0acefb7565..84c350994b06 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -29,6 +29,7 @@
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/vgaarb.h> 30#include <linux/vgaarb.h>
31#include <linux/pm_runtime.h> 31#include <linux/pm_runtime.h>
32#include <linux/of.h>
32#include "pci.h" 33#include "pci.h"
33 34
34static int sysfs_initialized; /* = 0 */ 35static int sysfs_initialized; /* = 0 */
@@ -416,6 +417,20 @@ static ssize_t d3cold_allowed_show(struct device *dev,
416static DEVICE_ATTR_RW(d3cold_allowed); 417static DEVICE_ATTR_RW(d3cold_allowed);
417#endif 418#endif
418 419
420#ifdef CONFIG_OF
421static ssize_t devspec_show(struct device *dev,
422 struct device_attribute *attr, char *buf)
423{
424 struct pci_dev *pdev = to_pci_dev(dev);
425 struct device_node *np = pci_device_to_OF_node(pdev);
426
427 if (np == NULL || np->full_name == NULL)
428 return 0;
429 return sprintf(buf, "%s", np->full_name);
430}
431static DEVICE_ATTR_RO(devspec);
432#endif
433
419#ifdef CONFIG_PCI_IOV 434#ifdef CONFIG_PCI_IOV
420static ssize_t sriov_totalvfs_show(struct device *dev, 435static ssize_t sriov_totalvfs_show(struct device *dev,
421 struct device_attribute *attr, 436 struct device_attribute *attr,
@@ -499,6 +514,45 @@ static struct device_attribute sriov_numvfs_attr =
499 sriov_numvfs_show, sriov_numvfs_store); 514 sriov_numvfs_show, sriov_numvfs_store);
500#endif /* CONFIG_PCI_IOV */ 515#endif /* CONFIG_PCI_IOV */
501 516
517static ssize_t driver_override_store(struct device *dev,
518 struct device_attribute *attr,
519 const char *buf, size_t count)
520{
521 struct pci_dev *pdev = to_pci_dev(dev);
522 char *driver_override, *old = pdev->driver_override, *cp;
523
524 if (count > PATH_MAX)
525 return -EINVAL;
526
527 driver_override = kstrndup(buf, count, GFP_KERNEL);
528 if (!driver_override)
529 return -ENOMEM;
530
531 cp = strchr(driver_override, '\n');
532 if (cp)
533 *cp = '\0';
534
535 if (strlen(driver_override)) {
536 pdev->driver_override = driver_override;
537 } else {
538 kfree(driver_override);
539 pdev->driver_override = NULL;
540 }
541
542 kfree(old);
543
544 return count;
545}
546
547static ssize_t driver_override_show(struct device *dev,
548 struct device_attribute *attr, char *buf)
549{
550 struct pci_dev *pdev = to_pci_dev(dev);
551
552 return sprintf(buf, "%s\n", pdev->driver_override);
553}
554static DEVICE_ATTR_RW(driver_override);
555
502static struct attribute *pci_dev_attrs[] = { 556static struct attribute *pci_dev_attrs[] = {
503 &dev_attr_resource.attr, 557 &dev_attr_resource.attr,
504 &dev_attr_vendor.attr, 558 &dev_attr_vendor.attr,
@@ -521,6 +575,10 @@ static struct attribute *pci_dev_attrs[] = {
521#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI) 575#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
522 &dev_attr_d3cold_allowed.attr, 576 &dev_attr_d3cold_allowed.attr,
523#endif 577#endif
578#ifdef CONFIG_OF
579 &dev_attr_devspec.attr,
580#endif
581 &dev_attr_driver_override.attr,
524 NULL, 582 NULL,
525}; 583};
526 584
@@ -1255,11 +1313,6 @@ static struct bin_attribute pcie_config_attr = {
1255 .write = pci_write_config, 1313 .write = pci_write_config,
1256}; 1314};
1257 1315
1258int __weak pcibios_add_platform_entries(struct pci_dev *dev)
1259{
1260 return 0;
1261}
1262
1263static ssize_t reset_store(struct device *dev, 1316static ssize_t reset_store(struct device *dev,
1264 struct device_attribute *attr, const char *buf, 1317 struct device_attribute *attr, const char *buf,
1265 size_t count) 1318 size_t count)
@@ -1375,11 +1428,6 @@ int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev)
1375 pdev->rom_attr = attr; 1428 pdev->rom_attr = attr;
1376 } 1429 }
1377 1430
1378 /* add platform-specific attributes */
1379 retval = pcibios_add_platform_entries(pdev);
1380 if (retval)
1381 goto err_rom_file;
1382
1383 /* add sysfs entries for various capabilities */ 1431 /* add sysfs entries for various capabilities */
1384 retval = pci_create_capabilities_sysfs(pdev); 1432 retval = pci_create_capabilities_sysfs(pdev);
1385 if (retval) 1433 if (retval)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7325d43bf030..fd958c8ebd83 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1468,6 +1468,17 @@ void __weak pcibios_release_device(struct pci_dev *dev) {}
1468 */ 1468 */
1469void __weak pcibios_disable_device (struct pci_dev *dev) {} 1469void __weak pcibios_disable_device (struct pci_dev *dev) {}
1470 1470
1471/**
1472 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1473 * @irq: ISA IRQ to penalize
1474 * @active: IRQ active or not
1475 *
1476 * Permits the platform to provide architecture-specific functionality when
1477 * penalizing ISA IRQs. This is the default implementation. Architecture
1478 * implementations can override this.
1479 */
1480void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1481
1471static void do_pci_disable_device(struct pci_dev *dev) 1482static void do_pci_disable_device(struct pci_dev *dev)
1472{ 1483{
1473 u16 pci_command; 1484 u16 pci_command;
@@ -3305,8 +3316,27 @@ static void pci_dev_unlock(struct pci_dev *dev)
3305 pci_cfg_access_unlock(dev); 3316 pci_cfg_access_unlock(dev);
3306} 3317}
3307 3318
3319/**
3320 * pci_reset_notify - notify device driver of reset
3321 * @dev: device to be notified of reset
3322 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3323 * completed
3324 *
3325 * Must be called prior to device access being disabled and after device
3326 * access is restored.
3327 */
3328static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3329{
3330 const struct pci_error_handlers *err_handler =
3331 dev->driver ? dev->driver->err_handler : NULL;
3332 if (err_handler && err_handler->reset_notify)
3333 err_handler->reset_notify(dev, prepare);
3334}
3335
3308static void pci_dev_save_and_disable(struct pci_dev *dev) 3336static void pci_dev_save_and_disable(struct pci_dev *dev)
3309{ 3337{
3338 pci_reset_notify(dev, true);
3339
3310 /* 3340 /*
3311 * Wake-up device prior to save. PM registers default to D0 after 3341 * Wake-up device prior to save. PM registers default to D0 after
3312 * reset and a simple register restore doesn't reliably return 3342 * reset and a simple register restore doesn't reliably return
@@ -3328,6 +3358,7 @@ static void pci_dev_save_and_disable(struct pci_dev *dev)
3328static void pci_dev_restore(struct pci_dev *dev) 3358static void pci_dev_restore(struct pci_dev *dev)
3329{ 3359{
3330 pci_restore_state(dev); 3360 pci_restore_state(dev);
3361 pci_reset_notify(dev, false);
3331} 3362}
3332 3363
3333static int pci_dev_reset(struct pci_dev *dev, int probe) 3364static int pci_dev_reset(struct pci_dev *dev, int probe)
@@ -3344,6 +3375,7 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
3344 3375
3345 return rc; 3376 return rc;
3346} 3377}
3378
3347/** 3379/**
3348 * __pci_reset_function - reset a PCI device function 3380 * __pci_reset_function - reset a PCI device function
3349 * @dev: PCI device to reset 3381 * @dev: PCI device to reset
@@ -4125,7 +4157,7 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode,
4125 u16 cmd; 4157 u16 cmd;
4126 int rc; 4158 int rc;
4127 4159
4128 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 4160 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4129 4161
4130 /* ARCH specific VGA enables */ 4162 /* ARCH specific VGA enables */
4131 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 4163 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 6bd082299e31..0601890db22d 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -77,7 +77,7 @@ static inline void pci_wakeup_event(struct pci_dev *dev)
77 pm_wakeup_event(&dev->dev, 100); 77 pm_wakeup_event(&dev->dev, 100);
78} 78}
79 79
80static inline bool pci_is_bridge(struct pci_dev *pci_dev) 80static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
81{ 81{
82 return !!(pci_dev->subordinate); 82 return !!(pci_dev->subordinate);
83} 83}
@@ -201,11 +201,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
201 struct resource *res, unsigned int reg); 201 struct resource *res, unsigned int reg);
202int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type); 202int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
203void pci_configure_ari(struct pci_dev *dev); 203void pci_configure_ari(struct pci_dev *dev);
204void __ref __pci_bus_size_bridges(struct pci_bus *bus, 204void __pci_bus_size_bridges(struct pci_bus *bus,
205 struct list_head *realloc_head); 205 struct list_head *realloc_head);
206void __ref __pci_bus_assign_resources(const struct pci_bus *bus, 206void __pci_bus_assign_resources(const struct pci_bus *bus,
207 struct list_head *realloc_head, 207 struct list_head *realloc_head,
208 struct list_head *fail_head); 208 struct list_head *fail_head);
209 209
210/** 210/**
211 * pci_ari_enabled - query ARI forwarding status 211 * pci_ari_enabled - query ARI forwarding status
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 986f8eadfd39..2f0ce668a775 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -99,7 +99,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
99 for (i = 0; i < nr_entries; i++) 99 for (i = 0; i < nr_entries; i++)
100 msix_entries[i].entry = i; 100 msix_entries[i].entry = i;
101 101
102 status = pci_enable_msix(dev, msix_entries, nr_entries); 102 status = pci_enable_msix_exact(dev, msix_entries, nr_entries);
103 if (status) 103 if (status)
104 goto Exit; 104 goto Exit;
105 105
@@ -171,7 +171,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
171 pci_disable_msix(dev); 171 pci_disable_msix(dev);
172 172
173 /* Now allocate the MSI-X vectors for real */ 173 /* Now allocate the MSI-X vectors for real */
174 status = pci_enable_msix(dev, msix_entries, nvec); 174 status = pci_enable_msix_exact(dev, msix_entries, nvec);
175 if (status) 175 if (status)
176 goto Exit; 176 goto Exit;
177 } 177 }
@@ -379,10 +379,13 @@ int pcie_port_device_register(struct pci_dev *dev)
379 /* 379 /*
380 * Initialize service irqs. Don't use service devices that 380 * Initialize service irqs. Don't use service devices that
381 * require interrupts if there is no way to generate them. 381 * require interrupts if there is no way to generate them.
382 * However, some drivers may have a polling mode (e.g. pciehp_poll_mode)
383 * that can be used in the absence of irqs. Allow them to determine
384 * if that is to be used.
382 */ 385 */
383 status = init_service_irqs(dev, irqs, capabilities); 386 status = init_service_irqs(dev, irqs, capabilities);
384 if (status) { 387 if (status) {
385 capabilities &= PCIE_PORT_SERVICE_VC; 388 capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
386 if (!capabilities) 389 if (!capabilities)
387 goto error_disable; 390 goto error_disable;
388 } 391 }
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ef09f5f2fe6c..2bbf5221afb3 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -171,9 +171,10 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
171 struct resource *res, unsigned int pos) 171 struct resource *res, unsigned int pos)
172{ 172{
173 u32 l, sz, mask; 173 u32 l, sz, mask;
174 u64 l64, sz64, mask64;
174 u16 orig_cmd; 175 u16 orig_cmd;
175 struct pci_bus_region region, inverted_region; 176 struct pci_bus_region region, inverted_region;
176 bool bar_too_big = false, bar_disabled = false; 177 bool bar_too_big = false, bar_too_high = false, bar_invalid = false;
177 178
178 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 179 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
179 180
@@ -226,9 +227,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
226 } 227 }
227 228
228 if (res->flags & IORESOURCE_MEM_64) { 229 if (res->flags & IORESOURCE_MEM_64) {
229 u64 l64 = l; 230 l64 = l;
230 u64 sz64 = sz; 231 sz64 = sz;
231 u64 mask64 = mask | (u64)~0 << 32; 232 mask64 = mask | (u64)~0 << 32;
232 233
233 pci_read_config_dword(dev, pos + 4, &l); 234 pci_read_config_dword(dev, pos + 4, &l);
234 pci_write_config_dword(dev, pos + 4, ~0); 235 pci_write_config_dword(dev, pos + 4, ~0);
@@ -243,19 +244,22 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
243 if (!sz64) 244 if (!sz64)
244 goto fail; 245 goto fail;
245 246
246 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 247 if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
248 sz64 > 0x100000000ULL) {
249 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
250 res->start = 0;
251 res->end = 0;
247 bar_too_big = true; 252 bar_too_big = true;
248 goto fail; 253 goto out;
249 } 254 }
250 255
251 if ((sizeof(resource_size_t) < 8) && l) { 256 if ((sizeof(dma_addr_t) < 8) && l) {
252 /* Address above 32-bit boundary; disable the BAR */ 257 /* Above 32-bit boundary; try to reallocate */
253 pci_write_config_dword(dev, pos, 0);
254 pci_write_config_dword(dev, pos + 4, 0);
255 res->flags |= IORESOURCE_UNSET; 258 res->flags |= IORESOURCE_UNSET;
256 region.start = 0; 259 res->start = 0;
257 region.end = sz64; 260 res->end = sz64;
258 bar_disabled = true; 261 bar_too_high = true;
262 goto out;
259 } else { 263 } else {
260 region.start = l64; 264 region.start = l64;
261 region.end = l64 + sz64; 265 region.end = l64 + sz64;
@@ -285,11 +289,10 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
285 * be claimed by the device. 289 * be claimed by the device.
286 */ 290 */
287 if (inverted_region.start != region.start) { 291 if (inverted_region.start != region.start) {
288 dev_info(&dev->dev, "reg 0x%x: initial BAR value %pa invalid; forcing reassignment\n",
289 pos, &region.start);
290 res->flags |= IORESOURCE_UNSET; 292 res->flags |= IORESOURCE_UNSET;
291 res->end -= res->start;
292 res->start = 0; 293 res->start = 0;
294 res->end = region.end - region.start;
295 bar_invalid = true;
293 } 296 }
294 297
295 goto out; 298 goto out;
@@ -303,8 +306,15 @@ out:
303 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 306 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
304 307
305 if (bar_too_big) 308 if (bar_too_big)
306 dev_err(&dev->dev, "reg 0x%x: can't handle 64-bit BAR\n", pos); 309 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
307 if (res->flags && !bar_disabled) 310 pos, (unsigned long long) sz64);
311 if (bar_too_high)
312 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n",
313 pos, (unsigned long long) l64);
314 if (bar_invalid)
315 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
316 pos, (unsigned long long) region.start);
317 if (res->flags)
308 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); 318 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
309 319
310 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 320 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
@@ -465,7 +475,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
465 475
466 if (dev->transparent) { 476 if (dev->transparent) {
467 pci_bus_for_each_resource(child->parent, res, i) { 477 pci_bus_for_each_resource(child->parent, res, i) {
468 if (res) { 478 if (res && res->flags) {
469 pci_bus_add_resource(child, res, 479 pci_bus_add_resource(child, res,
470 PCI_SUBTRACTIVE_DECODE); 480 PCI_SUBTRACTIVE_DECODE);
471 dev_printk(KERN_DEBUG, &dev->dev, 481 dev_printk(KERN_DEBUG, &dev->dev,
@@ -719,7 +729,7 @@ add_dev:
719 return child; 729 return child;
720} 730}
721 731
722struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 732struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
723{ 733{
724 struct pci_bus *child; 734 struct pci_bus *child;
725 735
@@ -984,6 +994,43 @@ void set_pcie_hotplug_bridge(struct pci_dev *pdev)
984 994
985 995
986/** 996/**
997 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
998 * @dev: PCI device
999 *
1000 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1001 * when forwarding a type1 configuration request the bridge must check that
1002 * the extended register address field is zero. The bridge is not permitted
1003 * to forward the transactions and must handle it as an Unsupported Request.
1004 * Some bridges do not follow this rule and simply drop the extended register
1005 * bits, resulting in the standard config space being aliased, every 256
1006 * bytes across the entire configuration space. Test for this condition by
1007 * comparing the first dword of each potential alias to the vendor/device ID.
1008 * Known offenders:
1009 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1010 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1011 */
1012static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1013{
1014#ifdef CONFIG_PCI_QUIRKS
1015 int pos;
1016 u32 header, tmp;
1017
1018 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1019
1020 for (pos = PCI_CFG_SPACE_SIZE;
1021 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1022 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1023 || header != tmp)
1024 return false;
1025 }
1026
1027 return true;
1028#else
1029 return false;
1030#endif
1031}
1032
1033/**
987 * pci_cfg_space_size - get the configuration space size of the PCI device. 1034 * pci_cfg_space_size - get the configuration space size of the PCI device.
988 * @dev: PCI device 1035 * @dev: PCI device
989 * 1036 *
@@ -1001,7 +1048,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
1001 1048
1002 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1049 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1003 goto fail; 1050 goto fail;
1004 if (status == 0xffffffff) 1051 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1005 goto fail; 1052 goto fail;
1006 1053
1007 return PCI_CFG_SPACE_EXP_SIZE; 1054 return PCI_CFG_SPACE_EXP_SIZE;
@@ -1215,6 +1262,7 @@ static void pci_release_dev(struct device *dev)
1215 pci_release_of_node(pci_dev); 1262 pci_release_of_node(pci_dev);
1216 pcibios_release_device(pci_dev); 1263 pcibios_release_device(pci_dev);
1217 pci_bus_put(pci_dev->bus); 1264 pci_bus_put(pci_dev->bus);
1265 kfree(pci_dev->driver_override);
1218 kfree(pci_dev); 1266 kfree(pci_dev);
1219} 1267}
1220 1268
@@ -1369,7 +1417,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1369 WARN_ON(ret < 0); 1417 WARN_ON(ret < 0);
1370} 1418}
1371 1419
1372struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) 1420struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1373{ 1421{
1374 struct pci_dev *dev; 1422 struct pci_dev *dev;
1375 1423
@@ -1617,7 +1665,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1617 */ 1665 */
1618void pcie_bus_configure_settings(struct pci_bus *bus) 1666void pcie_bus_configure_settings(struct pci_bus *bus)
1619{ 1667{
1620 u8 smpss; 1668 u8 smpss = 0;
1621 1669
1622 if (!bus->self) 1670 if (!bus->self)
1623 return; 1671 return;
@@ -1670,8 +1718,7 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
1670 1718
1671 for (pass=0; pass < 2; pass++) 1719 for (pass=0; pass < 2; pass++)
1672 list_for_each_entry(dev, &bus->devices, bus_list) { 1720 list_for_each_entry(dev, &bus->devices, bus_list) {
1673 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1721 if (pci_is_bridge(dev))
1674 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1675 max = pci_scan_bridge(bus, dev, max, pass); 1722 max = pci_scan_bridge(bus, dev, max, pass);
1676 } 1723 }
1677 1724
@@ -1958,7 +2005,7 @@ EXPORT_SYMBOL(pci_scan_bus);
1958 * 2005 *
1959 * Returns the max number of subordinate bus discovered. 2006 * Returns the max number of subordinate bus discovered.
1960 */ 2007 */
1961unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 2008unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1962{ 2009{
1963 unsigned int max; 2010 unsigned int max;
1964 struct pci_bus *bus = bridge->subordinate; 2011 struct pci_bus *bus = bridge->subordinate;
@@ -1981,7 +2028,7 @@ unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1981 * 2028 *
1982 * Returns the max number of subordinate bus discovered. 2029 * Returns the max number of subordinate bus discovered.
1983 */ 2030 */
1984unsigned int __ref pci_rescan_bus(struct pci_bus *bus) 2031unsigned int pci_rescan_bus(struct pci_bus *bus)
1985{ 2032{
1986 unsigned int max; 2033 unsigned int max;
1987 2034
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index e7292065a1b1..d3f29dd29876 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2954,6 +2954,7 @@ static void disable_igfx_irq(struct pci_dev *dev)
2954} 2954}
2955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 2955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2956DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 2956DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2957DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
2957 2958
2958/* 2959/*
2959 * PCI devices which are on Intel chips can skip the 10ms delay 2960 * PCI devices which are on Intel chips can skip the 10ms delay
@@ -2991,6 +2992,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2991 quirk_broken_intx_masking); 2992 quirk_broken_intx_masking);
2992DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 2993DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2993 quirk_broken_intx_masking); 2994 quirk_broken_intx_masking);
2995/*
2996 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
2997 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
2998 *
2999 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3000 */
3001DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3002 quirk_broken_intx_masking);
2994 3003
2995static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3004static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2996 struct pci_fixup *end) 3005 struct pci_fixup *end)
@@ -3333,6 +3342,81 @@ int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3333 return -ENOTTY; 3342 return -ENOTTY;
3334} 3343}
3335 3344
3345static void quirk_dma_func0_alias(struct pci_dev *dev)
3346{
3347 if (PCI_FUNC(dev->devfn) != 0) {
3348 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3349 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3350 }
3351}
3352
3353/*
3354 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3355 *
3356 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3357 */
3358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3359DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3360
3361static void quirk_dma_func1_alias(struct pci_dev *dev)
3362{
3363 if (PCI_FUNC(dev->devfn) != 1) {
3364 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3365 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3366 }
3367}
3368
3369/*
3370 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3371 * SKUs function 1 is present and is a legacy IDE controller, in other
3372 * SKUs this function is not present, making this a ghost requester.
3373 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3374 */
3375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3376 quirk_dma_func1_alias);
3377/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3379 quirk_dma_func1_alias);
3380/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3381DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3382 quirk_dma_func1_alias);
3383/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3385 quirk_dma_func1_alias);
3386/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3387DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3388 quirk_dma_func1_alias);
3389/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3390DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3391 quirk_dma_func1_alias);
3392/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3393DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3394 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3395 quirk_dma_func1_alias);
3396
3397/*
3398 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3399 * using the wrong DMA alias for the device. Some of these devices can be
3400 * used as either forward or reverse bridges, so we need to test whether the
3401 * device is operating in the correct mode. We could probably apply this
3402 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3403 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3404 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3405 */
3406static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3407{
3408 if (!pci_is_root_bus(pdev->bus) &&
3409 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3410 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3411 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3412 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3413}
3414/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3416 quirk_use_pcie_bridge_dma_alias);
3417/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3418DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3419
3336static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev) 3420static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3337{ 3421{
3338 if (!PCI_FUNC(dev->devfn)) 3422 if (!PCI_FUNC(dev->devfn))
@@ -3453,6 +3537,8 @@ static const u16 pci_quirk_intel_pch_acs_ids[] = {
3453 /* Wildcat PCH */ 3537 /* Wildcat PCH */
3454 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 3538 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3455 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 3539 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3540 /* Patsburg (X79) PCH */
3541 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3456}; 3542};
3457 3543
3458static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 3544static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index 4a1b972efe7f..0e9a00e5ca60 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -7,7 +7,6 @@
7 * Copyright (C) 2003 -- 2004 Greg Kroah-Hartman <greg@kroah.com> 7 * Copyright (C) 2003 -- 2004 Greg Kroah-Hartman <greg@kroah.com>
8 */ 8 */
9 9
10#include <linux/init.h>
11#include <linux/pci.h> 10#include <linux/pci.h>
12#include <linux/slab.h> 11#include <linux/slab.h>
13#include <linux/module.h> 12#include <linux/module.h>
@@ -18,6 +17,93 @@ DECLARE_RWSEM(pci_bus_sem);
18EXPORT_SYMBOL_GPL(pci_bus_sem); 17EXPORT_SYMBOL_GPL(pci_bus_sem);
19 18
20/* 19/*
20 * pci_for_each_dma_alias - Iterate over DMA aliases for a device
21 * @pdev: starting downstream device
22 * @fn: function to call for each alias
23 * @data: opaque data to pass to @fn
24 *
25 * Starting @pdev, walk up the bus calling @fn for each possible alias
26 * of @pdev at the root bus.
27 */
28int pci_for_each_dma_alias(struct pci_dev *pdev,
29 int (*fn)(struct pci_dev *pdev,
30 u16 alias, void *data), void *data)
31{
32 struct pci_bus *bus;
33 int ret;
34
35 ret = fn(pdev, PCI_DEVID(pdev->bus->number, pdev->devfn), data);
36 if (ret)
37 return ret;
38
39 /*
40 * If the device is broken and uses an alias requester ID for
41 * DMA, iterate over that too.
42 */
43 if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN)) {
44 ret = fn(pdev, PCI_DEVID(pdev->bus->number,
45 pdev->dma_alias_devfn), data);
46 if (ret)
47 return ret;
48 }
49
50 for (bus = pdev->bus; !pci_is_root_bus(bus); bus = bus->parent) {
51 struct pci_dev *tmp;
52
53 /* Skip virtual buses */
54 if (!bus->self)
55 continue;
56
57 tmp = bus->self;
58
59 /*
60 * PCIe-to-PCI/X bridges alias transactions from downstream
61 * devices using the subordinate bus number (PCI Express to
62 * PCI/PCI-X Bridge Spec, rev 1.0, sec 2.3). For all cases
63 * where the upstream bus is PCI/X we alias to the bridge
64 * (there are various conditions in the previous reference
65 * where the bridge may take ownership of transactions, even
66 * when the secondary interface is PCI-X).
67 */
68 if (pci_is_pcie(tmp)) {
69 switch (pci_pcie_type(tmp)) {
70 case PCI_EXP_TYPE_ROOT_PORT:
71 case PCI_EXP_TYPE_UPSTREAM:
72 case PCI_EXP_TYPE_DOWNSTREAM:
73 continue;
74 case PCI_EXP_TYPE_PCI_BRIDGE:
75 ret = fn(tmp,
76 PCI_DEVID(tmp->subordinate->number,
77 PCI_DEVFN(0, 0)), data);
78 if (ret)
79 return ret;
80 continue;
81 case PCI_EXP_TYPE_PCIE_BRIDGE:
82 ret = fn(tmp,
83 PCI_DEVID(tmp->bus->number,
84 tmp->devfn), data);
85 if (ret)
86 return ret;
87 continue;
88 }
89 } else {
90 if (tmp->dev_flags & PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS)
91 ret = fn(tmp,
92 PCI_DEVID(tmp->subordinate->number,
93 PCI_DEVFN(0, 0)), data);
94 else
95 ret = fn(tmp,
96 PCI_DEVID(tmp->bus->number,
97 tmp->devfn), data);
98 if (ret)
99 return ret;
100 }
101 }
102
103 return ret;
104}
105
106/*
21 * find the upstream PCIe-to-PCI bridge of a PCI device 107 * find the upstream PCIe-to-PCI bridge of a PCI device
22 * if the device is PCIE, return NULL 108 * if the device is PCIE, return NULL
23 * if the device isn't connected to a PCIe bridge (that is its parent is a 109 * if the device isn't connected to a PCIe bridge (that is its parent is a
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 138bdd6393be..fd9b545c3cf5 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -713,12 +713,11 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
713 bus resource of a given type. Note: we intentionally skip 713 bus resource of a given type. Note: we intentionally skip
714 the bus resources which have already been assigned (that is, 714 the bus resources which have already been assigned (that is,
715 have non-NULL parent resource). */ 715 have non-NULL parent resource). */
716static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) 716static struct resource *find_free_bus_resource(struct pci_bus *bus,
717 unsigned long type_mask, unsigned long type)
717{ 718{
718 int i; 719 int i;
719 struct resource *r; 720 struct resource *r;
720 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
721 IORESOURCE_PREFETCH;
722 721
723 pci_bus_for_each_resource(bus, r, i) { 722 pci_bus_for_each_resource(bus, r, i) {
724 if (r == &ioport_resource || r == &iomem_resource) 723 if (r == &ioport_resource || r == &iomem_resource)
@@ -815,7 +814,8 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
815 resource_size_t add_size, struct list_head *realloc_head) 814 resource_size_t add_size, struct list_head *realloc_head)
816{ 815{
817 struct pci_dev *dev; 816 struct pci_dev *dev;
818 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 817 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
818 IORESOURCE_IO);
819 resource_size_t size = 0, size0 = 0, size1 = 0; 819 resource_size_t size = 0, size0 = 0, size1 = 0;
820 resource_size_t children_add_size = 0; 820 resource_size_t children_add_size = 0;
821 resource_size_t min_align, align; 821 resource_size_t min_align, align;
@@ -907,36 +907,40 @@ static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
907 * @bus : the bus 907 * @bus : the bus
908 * @mask: mask the resource flag, then compare it with type 908 * @mask: mask the resource flag, then compare it with type
909 * @type: the type of free resource from bridge 909 * @type: the type of free resource from bridge
910 * @type2: second match type
911 * @type3: third match type
910 * @min_size : the minimum memory window that must to be allocated 912 * @min_size : the minimum memory window that must to be allocated
911 * @add_size : additional optional memory window 913 * @add_size : additional optional memory window
912 * @realloc_head : track the additional memory window on this list 914 * @realloc_head : track the additional memory window on this list
913 * 915 *
914 * Calculate the size of the bus and minimal alignment which 916 * Calculate the size of the bus and minimal alignment which
915 * guarantees that all child resources fit in this size. 917 * guarantees that all child resources fit in this size.
918 *
919 * Returns -ENOSPC if there's no available bus resource of the desired type.
920 * Otherwise, sets the bus resource start/end to indicate the required
921 * size, adds things to realloc_head (if supplied), and returns 0.
916 */ 922 */
917static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 923static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
918 unsigned long type, resource_size_t min_size, 924 unsigned long type, unsigned long type2,
919 resource_size_t add_size, 925 unsigned long type3,
920 struct list_head *realloc_head) 926 resource_size_t min_size, resource_size_t add_size,
927 struct list_head *realloc_head)
921{ 928{
922 struct pci_dev *dev; 929 struct pci_dev *dev;
923 resource_size_t min_align, align, size, size0, size1; 930 resource_size_t min_align, align, size, size0, size1;
924 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ 931 resource_size_t aligns[14]; /* Alignments from 1Mb to 8Gb */
925 int order, max_order; 932 int order, max_order;
926 struct resource *b_res = find_free_bus_resource(bus, type); 933 struct resource *b_res = find_free_bus_resource(bus,
927 unsigned int mem64_mask = 0; 934 mask | IORESOURCE_PREFETCH, type);
928 resource_size_t children_add_size = 0; 935 resource_size_t children_add_size = 0;
929 936
930 if (!b_res) 937 if (!b_res)
931 return 0; 938 return -ENOSPC;
932 939
933 memset(aligns, 0, sizeof(aligns)); 940 memset(aligns, 0, sizeof(aligns));
934 max_order = 0; 941 max_order = 0;
935 size = 0; 942 size = 0;
936 943
937 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
938 b_res->flags &= ~IORESOURCE_MEM_64;
939
940 list_for_each_entry(dev, &bus->devices, bus_list) { 944 list_for_each_entry(dev, &bus->devices, bus_list) {
941 int i; 945 int i;
942 946
@@ -944,7 +948,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
944 struct resource *r = &dev->resource[i]; 948 struct resource *r = &dev->resource[i];
945 resource_size_t r_size; 949 resource_size_t r_size;
946 950
947 if (r->parent || (r->flags & mask) != type) 951 if (r->parent || ((r->flags & mask) != type &&
952 (r->flags & mask) != type2 &&
953 (r->flags & mask) != type3))
948 continue; 954 continue;
949 r_size = resource_size(r); 955 r_size = resource_size(r);
950#ifdef CONFIG_PCI_IOV 956#ifdef CONFIG_PCI_IOV
@@ -957,10 +963,17 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
957 continue; 963 continue;
958 } 964 }
959#endif 965#endif
960 /* For bridges size != alignment */ 966 /*
967 * aligns[0] is for 1MB (since bridge memory
968 * windows are always at least 1MB aligned), so
969 * keep "order" from being negative for smaller
970 * resources.
971 */
961 align = pci_resource_alignment(dev, r); 972 align = pci_resource_alignment(dev, r);
962 order = __ffs(align) - 20; 973 order = __ffs(align) - 20;
963 if (order > 11) { 974 if (order < 0)
975 order = 0;
976 if (order >= ARRAY_SIZE(aligns)) {
964 dev_warn(&dev->dev, "disabling BAR %d: %pR " 977 dev_warn(&dev->dev, "disabling BAR %d: %pR "
965 "(bad alignment %#llx)\n", i, r, 978 "(bad alignment %#llx)\n", i, r,
966 (unsigned long long) align); 979 (unsigned long long) align);
@@ -968,15 +981,12 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
968 continue; 981 continue;
969 } 982 }
970 size += r_size; 983 size += r_size;
971 if (order < 0)
972 order = 0;
973 /* Exclude ranges with size > align from 984 /* Exclude ranges with size > align from
974 calculation of the alignment. */ 985 calculation of the alignment. */
975 if (r_size == align) 986 if (r_size == align)
976 aligns[order] += align; 987 aligns[order] += align;
977 if (order > max_order) 988 if (order > max_order)
978 max_order = order; 989 max_order = order;
979 mem64_mask &= r->flags & IORESOURCE_MEM_64;
980 990
981 if (realloc_head) 991 if (realloc_head)
982 children_add_size += get_res_add_size(realloc_head, r); 992 children_add_size += get_res_add_size(realloc_head, r);
@@ -997,18 +1007,18 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
997 "%pR to %pR (unused)\n", b_res, 1007 "%pR to %pR (unused)\n", b_res,
998 &bus->busn_res); 1008 &bus->busn_res);
999 b_res->flags = 0; 1009 b_res->flags = 0;
1000 return 1; 1010 return 0;
1001 } 1011 }
1002 b_res->start = min_align; 1012 b_res->start = min_align;
1003 b_res->end = size0 + min_align - 1; 1013 b_res->end = size0 + min_align - 1;
1004 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; 1014 b_res->flags |= IORESOURCE_STARTALIGN;
1005 if (size1 > size0 && realloc_head) { 1015 if (size1 > size0 && realloc_head) {
1006 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); 1016 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
1007 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " 1017 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
1008 "%pR to %pR add_size %llx\n", b_res, 1018 "%pR to %pR add_size %llx\n", b_res,
1009 &bus->busn_res, (unsigned long long)size1-size0); 1019 &bus->busn_res, (unsigned long long)size1-size0);
1010 } 1020 }
1011 return 1; 1021 return 0;
1012} 1022}
1013 1023
1014unsigned long pci_cardbus_resource_alignment(struct resource *res) 1024unsigned long pci_cardbus_resource_alignment(struct resource *res)
@@ -1113,12 +1123,13 @@ handle_done:
1113 ; 1123 ;
1114} 1124}
1115 1125
1116void __ref __pci_bus_size_bridges(struct pci_bus *bus, 1126void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1117 struct list_head *realloc_head)
1118{ 1127{
1119 struct pci_dev *dev; 1128 struct pci_dev *dev;
1120 unsigned long mask, prefmask; 1129 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1121 resource_size_t additional_mem_size = 0, additional_io_size = 0; 1130 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1131 struct resource *b_res;
1132 int ret;
1122 1133
1123 list_for_each_entry(dev, &bus->devices, bus_list) { 1134 list_for_each_entry(dev, &bus->devices, bus_list) {
1124 struct pci_bus *b = dev->subordinate; 1135 struct pci_bus *b = dev->subordinate;
@@ -1152,41 +1163,93 @@ void __ref __pci_bus_size_bridges(struct pci_bus *bus,
1152 additional_io_size = pci_hotplug_io_size; 1163 additional_io_size = pci_hotplug_io_size;
1153 additional_mem_size = pci_hotplug_mem_size; 1164 additional_mem_size = pci_hotplug_mem_size;
1154 } 1165 }
1155 /* 1166 /* Fall through */
1156 * Follow thru
1157 */
1158 default: 1167 default:
1159 pbus_size_io(bus, realloc_head ? 0 : additional_io_size, 1168 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1160 additional_io_size, realloc_head); 1169 additional_io_size, realloc_head);
1161 /* If the bridge supports prefetchable range, size it 1170
1162 separately. If it doesn't, or its prefetchable window 1171 /*
1163 has already been allocated by arch code, try 1172 * If there's a 64-bit prefetchable MMIO window, compute
1164 non-prefetchable range for both types of PCI memory 1173 * the size required to put all 64-bit prefetchable
1165 resources. */ 1174 * resources in it.
1175 */
1176 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1166 mask = IORESOURCE_MEM; 1177 mask = IORESOURCE_MEM;
1167 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 1178 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1168 if (pbus_size_mem(bus, prefmask, prefmask, 1179 if (b_res[2].flags & IORESOURCE_MEM_64) {
1180 prefmask |= IORESOURCE_MEM_64;
1181 ret = pbus_size_mem(bus, prefmask, prefmask,
1182 prefmask, prefmask,
1169 realloc_head ? 0 : additional_mem_size, 1183 realloc_head ? 0 : additional_mem_size,
1170 additional_mem_size, realloc_head)) 1184 additional_mem_size, realloc_head);
1171 mask = prefmask; /* Success, size non-prefetch only. */ 1185
1172 else 1186 /*
1173 additional_mem_size += additional_mem_size; 1187 * If successful, all non-prefetchable resources
1174 pbus_size_mem(bus, mask, IORESOURCE_MEM, 1188 * and any 32-bit prefetchable resources will go in
1189 * the non-prefetchable window.
1190 */
1191 if (ret == 0) {
1192 mask = prefmask;
1193 type2 = prefmask & ~IORESOURCE_MEM_64;
1194 type3 = prefmask & ~IORESOURCE_PREFETCH;
1195 }
1196 }
1197
1198 /*
1199 * If there is no 64-bit prefetchable window, compute the
1200 * size required to put all prefetchable resources in the
1201 * 32-bit prefetchable window (if there is one).
1202 */
1203 if (!type2) {
1204 prefmask &= ~IORESOURCE_MEM_64;
1205 ret = pbus_size_mem(bus, prefmask, prefmask,
1206 prefmask, prefmask,
1207 realloc_head ? 0 : additional_mem_size,
1208 additional_mem_size, realloc_head);
1209
1210 /*
1211 * If successful, only non-prefetchable resources
1212 * will go in the non-prefetchable window.
1213 */
1214 if (ret == 0)
1215 mask = prefmask;
1216 else
1217 additional_mem_size += additional_mem_size;
1218
1219 type2 = type3 = IORESOURCE_MEM;
1220 }
1221
1222 /*
1223 * Compute the size required to put everything else in the
1224 * non-prefetchable window. This includes:
1225 *
1226 * - all non-prefetchable resources
1227 * - 32-bit prefetchable resources if there's a 64-bit
1228 * prefetchable window or no prefetchable window at all
1229 * - 64-bit prefetchable resources if there's no
1230 * prefetchable window at all
1231 *
1232 * Note that the strategy in __pci_assign_resource() must
1233 * match that used here. Specifically, we cannot put a
1234 * 32-bit prefetchable resource in a 64-bit prefetchable
1235 * window.
1236 */
1237 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1175 realloc_head ? 0 : additional_mem_size, 1238 realloc_head ? 0 : additional_mem_size,
1176 additional_mem_size, realloc_head); 1239 additional_mem_size, realloc_head);
1177 break; 1240 break;
1178 } 1241 }
1179} 1242}
1180 1243
1181void __ref pci_bus_size_bridges(struct pci_bus *bus) 1244void pci_bus_size_bridges(struct pci_bus *bus)
1182{ 1245{
1183 __pci_bus_size_bridges(bus, NULL); 1246 __pci_bus_size_bridges(bus, NULL);
1184} 1247}
1185EXPORT_SYMBOL(pci_bus_size_bridges); 1248EXPORT_SYMBOL(pci_bus_size_bridges);
1186 1249
1187void __ref __pci_bus_assign_resources(const struct pci_bus *bus, 1250void __pci_bus_assign_resources(const struct pci_bus *bus,
1188 struct list_head *realloc_head, 1251 struct list_head *realloc_head,
1189 struct list_head *fail_head) 1252 struct list_head *fail_head)
1190{ 1253{
1191 struct pci_bus *b; 1254 struct pci_bus *b;
1192 struct pci_dev *dev; 1255 struct pci_dev *dev;
@@ -1218,15 +1281,15 @@ void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
1218 } 1281 }
1219} 1282}
1220 1283
1221void __ref pci_bus_assign_resources(const struct pci_bus *bus) 1284void pci_bus_assign_resources(const struct pci_bus *bus)
1222{ 1285{
1223 __pci_bus_assign_resources(bus, NULL, NULL); 1286 __pci_bus_assign_resources(bus, NULL, NULL);
1224} 1287}
1225EXPORT_SYMBOL(pci_bus_assign_resources); 1288EXPORT_SYMBOL(pci_bus_assign_resources);
1226 1289
1227static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, 1290static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1228 struct list_head *add_head, 1291 struct list_head *add_head,
1229 struct list_head *fail_head) 1292 struct list_head *fail_head)
1230{ 1293{
1231 struct pci_bus *b; 1294 struct pci_bus *b;
1232 1295
@@ -1257,42 +1320,66 @@ static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1257static void pci_bridge_release_resources(struct pci_bus *bus, 1320static void pci_bridge_release_resources(struct pci_bus *bus,
1258 unsigned long type) 1321 unsigned long type)
1259{ 1322{
1260 int idx; 1323 struct pci_dev *dev = bus->self;
1261 bool changed = false;
1262 struct pci_dev *dev;
1263 struct resource *r; 1324 struct resource *r;
1264 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 1325 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1265 IORESOURCE_PREFETCH; 1326 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1327 unsigned old_flags = 0;
1328 struct resource *b_res;
1329 int idx = 1;
1266 1330
1267 dev = bus->self; 1331 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1268 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; 1332
1269 idx++) { 1333 /*
1270 r = &dev->resource[idx]; 1334 * 1. if there is io port assign fail, will release bridge
1271 if ((r->flags & type_mask) != type) 1335 * io port.
1272 continue; 1336 * 2. if there is non pref mmio assign fail, release bridge
1273 if (!r->parent) 1337 * nonpref mmio.
1274 continue; 1338 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1275 /* 1339 * is 64bit, release bridge pref mmio.
1276 * if there are children under that, we should release them 1340 * 4. if there is pref mmio assign fail, and bridge pref is
1277 * all 1341 * 32bit mmio, release bridge pref mmio
1278 */ 1342 * 5. if there is pref mmio assign fail, and bridge pref is not
1279 release_child_resources(r); 1343 * assigned, release bridge nonpref mmio.
1280 if (!release_resource(r)) { 1344 */
1281 dev_printk(KERN_DEBUG, &dev->dev, 1345 if (type & IORESOURCE_IO)
1282 "resource %d %pR released\n", idx, r); 1346 idx = 0;
1283 /* keep the old size */ 1347 else if (!(type & IORESOURCE_PREFETCH))
1284 r->end = resource_size(r) - 1; 1348 idx = 1;
1285 r->start = 0; 1349 else if ((type & IORESOURCE_MEM_64) &&
1286 r->flags = 0; 1350 (b_res[2].flags & IORESOURCE_MEM_64))
1287 changed = true; 1351 idx = 2;
1288 } 1352 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1289 } 1353 (b_res[2].flags & IORESOURCE_PREFETCH))
1354 idx = 2;
1355 else
1356 idx = 1;
1357
1358 r = &b_res[idx];
1359
1360 if (!r->parent)
1361 return;
1362
1363 /*
1364 * if there are children under that, we should release them
1365 * all
1366 */
1367 release_child_resources(r);
1368 if (!release_resource(r)) {
1369 type = old_flags = r->flags & type_mask;
1370 dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
1371 PCI_BRIDGE_RESOURCES + idx, r);
1372 /* keep the old size */
1373 r->end = resource_size(r) - 1;
1374 r->start = 0;
1375 r->flags = 0;
1290 1376
1291 if (changed) {
1292 /* avoiding touch the one without PREF */ 1377 /* avoiding touch the one without PREF */
1293 if (type & IORESOURCE_PREFETCH) 1378 if (type & IORESOURCE_PREFETCH)
1294 type = IORESOURCE_PREFETCH; 1379 type = IORESOURCE_PREFETCH;
1295 __pci_setup_bridge(bus, type); 1380 __pci_setup_bridge(bus, type);
1381 /* for next child res under same bridge */
1382 r->flags = old_flags;
1296 } 1383 }
1297} 1384}
1298 1385
@@ -1304,9 +1391,9 @@ enum release_type {
1304 * try to release pci bridge resources that is from leaf bridge, 1391 * try to release pci bridge resources that is from leaf bridge,
1305 * so we can allocate big new one later 1392 * so we can allocate big new one later
1306 */ 1393 */
1307static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, 1394static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1308 unsigned long type, 1395 unsigned long type,
1309 enum release_type rel_type) 1396 enum release_type rel_type)
1310{ 1397{
1311 struct pci_dev *dev; 1398 struct pci_dev *dev;
1312 bool is_leaf_bridge = true; 1399 bool is_leaf_bridge = true;
@@ -1471,7 +1558,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1471 LIST_HEAD(fail_head); 1558 LIST_HEAD(fail_head);
1472 struct pci_dev_resource *fail_res; 1559 struct pci_dev_resource *fail_res;
1473 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 1560 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1474 IORESOURCE_PREFETCH; 1561 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1475 int pci_try_num = 1; 1562 int pci_try_num = 1;
1476 enum enable_type enable_local; 1563 enum enable_type enable_local;
1477 1564
@@ -1629,9 +1716,7 @@ void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1629 1716
1630 down_read(&pci_bus_sem); 1717 down_read(&pci_bus_sem);
1631 list_for_each_entry(dev, &bus->devices, bus_list) 1718 list_for_each_entry(dev, &bus->devices, bus_list)
1632 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 1719 if (pci_is_bridge(dev) && pci_has_subordinate(dev))
1633 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1634 if (dev->subordinate)
1635 __pci_bus_size_bridges(dev->subordinate, 1720 __pci_bus_size_bridges(dev->subordinate,
1636 &add_list); 1721 &add_list);
1637 up_read(&pci_bus_sem); 1722 up_read(&pci_bus_sem);
diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
index 9bd6864ec5d3..dbc4ffcf42de 100644
--- a/drivers/pci/setup-irq.c
+++ b/drivers/pci/setup-irq.c
@@ -10,7 +10,6 @@
10 */ 10 */
11 11
12 12
13#include <linux/init.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15#include <linux/pci.h> 14#include <linux/pci.h>
16#include <linux/errno.h> 15#include <linux/errno.h>
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 7eed671d5586..33f9e32d94d0 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -16,7 +16,6 @@
16 * Resource sorting 16 * Resource sorting
17 */ 17 */
18 18
19#include <linux/init.h>
20#include <linux/kernel.h> 19#include <linux/kernel.h>
21#include <linux/export.h> 20#include <linux/export.h>
22#include <linux/pci.h> 21#include <linux/pci.h>
@@ -209,21 +208,42 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
209 208
210 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 209 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
211 210
212 /* First, try exact prefetching match.. */ 211 /*
212 * First, try exact prefetching match. Even if a 64-bit
213 * prefetchable bridge window is below 4GB, we can't put a 32-bit
214 * prefetchable resource in it because pbus_size_mem() assumes a
215 * 64-bit window will contain no 32-bit resources. If we assign
216 * things differently than they were sized, not everything will fit.
217 */
213 ret = pci_bus_alloc_resource(bus, res, size, align, min, 218 ret = pci_bus_alloc_resource(bus, res, size, align, min,
214 IORESOURCE_PREFETCH, 219 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
215 pcibios_align_resource, dev); 220 pcibios_align_resource, dev);
221 if (ret == 0)
222 return 0;
216 223
217 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) { 224 /*
218 /* 225 * If the prefetchable window is only 32 bits wide, we can put
219 * That failed. 226 * 64-bit prefetchable resources in it.
220 * 227 */
221 * But a prefetching area can handle a non-prefetching 228 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
222 * window (it will just not perform as well). 229 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
223 */ 230 ret = pci_bus_alloc_resource(bus, res, size, align, min,
224 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 231 IORESOURCE_PREFETCH,
225 pcibios_align_resource, dev); 232 pcibios_align_resource, dev);
233 if (ret == 0)
234 return 0;
226 } 235 }
236
237 /*
238 * If we didn't find a better match, we can put any memory resource
239 * in a non-prefetchable window. If this resource is 32 bits and
240 * non-prefetchable, the first call already tried the only possibility
241 * so we don't need to try again.
242 */
243 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
244 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
245 pcibios_align_resource, dev);
246
227 return ret; 247 return ret;
228} 248}
229 249
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 11:35:37 -0400