11 files changed, 242 insertions, 123 deletions

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 3dc25fad490c..c4b6568e486d 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -32,7 +32,10 @@ config PCI_IMX6
 
 config PCI_TEGRA
         bool "NVIDIA Tegra PCIe controller"
-        depends on ARCH_TEGRA
+        depends on ARCH_TEGRA && !ARM64
+        help
+          Say Y here if you want support for the PCIe host controller found
+          on NVIDIA Tegra SoCs.
 
 config PCI_RCAR_GEN2
         bool "Renesas R-Car Gen2 Internal PCI controller"
@@ -91,4 +94,12 @@ config PCI_XGENE
           There are 5 internal PCIe ports available. Each port is GEN3 capable
           and have varied lanes from x1 to x8.
 
+config PCI_LAYERSCAPE
+        bool "Freescale Layerscape PCIe controller"
+        depends on OF && ARM
+        select PCIE_DW
+        select MFD_SYSCON
+        help
+          Say Y here if you want PCIe controller support on Layerscape SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 26b3461d68d7..44c26998027f 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
 obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
+obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 52b34fee07fd..8c6969747acd 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -270,8 +270,8 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-static int add_pcie_port(struct dra7xx_pcie *dra7xx,
-                          struct platform_device *pdev)
+static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
+                                       struct platform_device *pdev)
 {
         int ret;
         struct pcie_port *pp;
@@ -398,7 +398,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, dra7xx);
 
-        ret = add_pcie_port(dra7xx, pdev);
+        ret = dra7xx_add_pcie_port(dra7xx, pdev);
         if (ret < 0)
                 goto err_add_port;
 
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c5d0ca384502..850c9f951a3f 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -312,7 +312,6 @@ static void exynos_pcie_assert_reset(struct pcie_port *pp)
         if (exynos_pcie->reset_gpio >= 0)
                 devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
                                 GPIOF_OUT_INIT_HIGH, "RESET");
-        return;
 }
 
 static int exynos_pcie_establish_link(struct pcie_port *pp)
@@ -388,7 +387,6 @@ static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
 
         val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
         exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
-        return;
 }
 
 static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
@@ -400,7 +398,6 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
         val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
                 IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
         exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
-        return;
 }
 
 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
@@ -429,7 +426,6 @@ static void exynos_pcie_msi_init(struct pcie_port *pp)
         val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
         val |= IRQ_MSI_ENABLE;
         exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
-        return;
 }
 
 static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
@@ -438,8 +434,6 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
 
         if (IS_ENABLED(CONFIG_PCI_MSI))
                 exynos_pcie_msi_init(pp);
-
-        return;
 }
 
 static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
@@ -448,7 +442,6 @@ static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
         exynos_pcie_sideband_dbi_r_mode(pp, true);
         *val = readl(dbi_base);
         exynos_pcie_sideband_dbi_r_mode(pp, false);
-        return;
 }
 
 static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
@@ -457,7 +450,6 @@ static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
         exynos_pcie_sideband_dbi_w_mode(pp, true);
         writel(val, dbi_base);
         exynos_pcie_sideband_dbi_w_mode(pp, false);
-        return;
 }
 
 static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
@@ -509,8 +501,8 @@ static struct pcie_host_ops exynos_pcie_host_ops = {
         .host_init = exynos_pcie_host_init,
 };
 
-static int __init add_pcie_port(struct pcie_port *pp,
-                                struct platform_device *pdev)
+static int __init exynos_add_pcie_port(struct pcie_port *pp,
+                                       struct platform_device *pdev)
 {
         int ret;
 
@@ -615,7 +607,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
                 goto fail_bus_clk;
         }
 
-        ret = add_pcie_port(pp, pdev);
+        ret = exynos_add_pcie_port(pp, pdev);
         if (ret < 0)
                 goto fail_bus_clk;
 
@@ -656,11 +648,11 @@ static struct platform_driver exynos_pcie_driver = {
 
 /* Exynos PCIe driver does not allow module unload */
 
-static int __init pcie_init(void)
+static int __init exynos_pcie_init(void)
 {
         return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
 }
-subsys_initcall(pcie_init);
+subsys_initcall(exynos_pcie_init);
 
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
 MODULE_DESCRIPTION("Samsung PCIe host controller driver");
diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c
index 3d2076f59911..18959075d164 100644
--- a/drivers/pci/host/pci-host-generic.c
+++ b/drivers/pci/host/pci-host-generic.c
@@ -32,7 +32,7 @@ struct gen_pci_cfg_bus_ops {
 
 struct gen_pci_cfg_windows {
         struct resource                         res;
-        struct resource                         bus_range;
+        struct resource                         *bus_range;
         void __iomem                            **win;
 
         const struct gen_pci_cfg_bus_ops        *ops;
@@ -50,7 +50,7 @@ static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
 {
         struct pci_sys_data *sys = bus->sysdata;
         struct gen_pci *pci = sys->private_data;
-        resource_size_t idx = bus->number - pci->cfg.bus_range.start;
+        resource_size_t idx = bus->number - pci->cfg.bus_range->start;
 
         return pci->cfg.win[idx] + ((devfn << 8) | where);
 }
@@ -66,7 +66,7 @@ static void __iomem *gen_pci_map_cfg_bus_ecam(struct pci_bus *bus,
 {
         struct pci_sys_data *sys = bus->sysdata;
         struct gen_pci *pci = sys->private_data;
-        resource_size_t idx = bus->number - pci->cfg.bus_range.start;
+        resource_size_t idx = bus->number - pci->cfg.bus_range->start;
 
         return pci->cfg.win[idx] + ((devfn << 12) | where);
 }
@@ -138,106 +138,50 @@ static const struct of_device_id gen_pci_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, gen_pci_of_match);
 
-static int gen_pci_calc_io_offset(struct device *dev,
-                                  struct of_pci_range *range,
-                                  struct resource *res,
-                                  resource_size_t *offset)
-{
-        static atomic_t wins = ATOMIC_INIT(0);
-        int err, idx, max_win;
-        unsigned int window;
-
-        if (!PAGE_ALIGNED(range->cpu_addr))
-                return -EINVAL;
-
-        max_win = (IO_SPACE_LIMIT + 1) / SZ_64K;
-        idx = atomic_inc_return(&wins);
-        if (idx > max_win)
-                return -ENOSPC;
-
-        window = (idx - 1) * SZ_64K;
-        err = pci_ioremap_io(window, range->cpu_addr);
-        if (err)
-                return err;
-
-        of_pci_range_to_resource(range, dev->of_node, res);
-        res->start = window;
-        res->end = res->start + range->size - 1;
-        *offset = window - range->pci_addr;
-        return 0;
-}
-
-static int gen_pci_calc_mem_offset(struct device *dev,
-                                   struct of_pci_range *range,
-                                   struct resource *res,
-                                   resource_size_t *offset)
-{
-        of_pci_range_to_resource(range, dev->of_node, res);
-        *offset = range->cpu_addr - range->pci_addr;
-        return 0;
-}
-
 static void gen_pci_release_of_pci_ranges(struct gen_pci *pci)
 {
-        struct pci_host_bridge_window *win;
-
-        list_for_each_entry(win, &pci->resources, list)
-                release_resource(win->res);
-
         pci_free_resource_list(&pci->resources);
 }
 
 static int gen_pci_parse_request_of_pci_ranges(struct gen_pci *pci)
 {
-        struct of_pci_range range;
-        struct of_pci_range_parser parser;
         int err, res_valid = 0;
         struct device *dev = pci->host.dev.parent;
         struct device_node *np = dev->of_node;
+        resource_size_t iobase;
+        struct pci_host_bridge_window *win;
 
-        if (of_pci_range_parser_init(&parser, np)) {
-                dev_err(dev, "missing \"ranges\" property\n");
-                return -EINVAL;
-        }
-
-        for_each_of_pci_range(&parser, &range) {
-                struct resource *parent, *res;
-                resource_size_t offset;
-                u32 restype = range.flags & IORESOURCE_TYPE_BITS;
+        err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
+                                               &iobase);
+        if (err)
+                return err;
 
-                res = devm_kmalloc(dev, sizeof(*res), GFP_KERNEL);
-                if (!res) {
-                        err = -ENOMEM;
-                        goto out_release_res;
-                }
+        list_for_each_entry(win, &pci->resources, list) {
+                struct resource *parent, *res = win->res;
 
-                switch (restype) {
+                switch (resource_type(res)) {
                 case IORESOURCE_IO:
                         parent = &ioport_resource;
-                        err = gen_pci_calc_io_offset(dev, &range, res, &offset);
+                        err = pci_remap_iospace(res, iobase);
+                        if (err) {
+                                dev_warn(dev, "error %d: failed to map resource %pR\n",
+                                         err, res);
+                                continue;
+                        }
                         break;
                 case IORESOURCE_MEM:
                         parent = &iomem_resource;
-                        err = gen_pci_calc_mem_offset(dev, &range, res, &offset);
-                        res_valid |= !(res->flags & IORESOURCE_PREFETCH || err);
+                        res_valid |= !(res->flags & IORESOURCE_PREFETCH);
                         break;
+                case IORESOURCE_BUS:
+                        pci->cfg.bus_range = res;
                 default:
-                        err = -EINVAL;
-                        continue;
-                }
-
-                if (err) {
-                        dev_warn(dev,
-                                 "error %d: failed to add resource [type 0x%x, %lld bytes]\n",
-                                 err, restype, range.size);
                         continue;
                 }
 
-                err = request_resource(parent, res);
+                err = devm_request_resource(dev, parent, res);
                 if (err)
                         goto out_release_res;
-
-                pci_add_resource_offset(&pci->resources, res, offset);
         }
 
         if (!res_valid) {
@@ -262,38 +206,30 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
         struct device *dev = pci->host.dev.parent;
         struct device_node *np = dev->of_node;
 
-        if (of_pci_parse_bus_range(np, &pci->cfg.bus_range))
-                pci->cfg.bus_range = (struct resource) {
-                        .name   = np->name,
-                        .start  = 0,
-                        .end    = 0xff,
-                        .flags  = IORESOURCE_BUS,
-                };
-
         err = of_address_to_resource(np, 0, &pci->cfg.res);
         if (err) {
                 dev_err(dev, "missing \"reg\" property\n");
                 return err;
         }
 
-        pci->cfg.win = devm_kcalloc(dev, resource_size(&pci->cfg.bus_range),
+        /* Limit the bus-range to fit within reg */
+        bus_max = pci->cfg.bus_range->start +
+                  (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
+        pci->cfg.bus_range->end = min_t(resource_size_t,
+                                        pci->cfg.bus_range->end, bus_max);
+
+        pci->cfg.win = devm_kcalloc(dev, resource_size(pci->cfg.bus_range),
                                     sizeof(*pci->cfg.win), GFP_KERNEL);
         if (!pci->cfg.win)
                 return -ENOMEM;
 
-        /* Limit the bus-range to fit within reg */
-        bus_max = pci->cfg.bus_range.start +
-                  (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
-        pci->cfg.bus_range.end = min_t(resource_size_t, pci->cfg.bus_range.end,
-                                       bus_max);
-
         /* Map our Configuration Space windows */
         if (!devm_request_mem_region(dev, pci->cfg.res.start,
                                      resource_size(&pci->cfg.res),
                                      "Configuration Space"))
                 return -ENOMEM;
 
-        bus_range = &pci->cfg.bus_range;
+        bus_range = pci->cfg.bus_range;
         for (busn = bus_range->start; busn <= bus_range->end; ++busn) {
                 u32 idx = busn - bus_range->start;
                 u32 sz = 1 << pci->cfg.ops->bus_shift;
@@ -305,8 +241,6 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
                         return -ENOMEM;
         }
 
-        /* Register bus resource */
-        pci_add_resource(&pci->resources, bus_range);
         return 0;
 }
 
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 233fe8a88264..8a7530b3b62a 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -526,8 +526,8 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp,
                 }
 
                 ret = devm_request_irq(&pdev->dev, pp->msi_irq,
-                                       imx6_pcie_msi_handler,
-                                       IRQF_SHARED, "mx6-pcie-msi", pp);
+                                       imx6_pcie_msi_handler,
+                                       IRQF_SHARED, "mx6-pcie-msi", pp);
                 if (ret) {
                         dev_err(&pdev->dev, "failed to request MSI irq\n");
                         return -ENODEV;
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
new file mode 100644
index 000000000000..6697b1a4d4fa
--- /dev/null
+++ b/drivers/pci/host/pci-layerscape.c
@@ -0,0 +1,179 @@
+/*
+ * PCIe host controller driver for Freescale Layerscape SoCs
+ *
+ * Copyright (C) 2014 Freescale Semiconductor.
+ *
+  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+#include "pcie-designware.h"
+
+/* PEX1/2 Misc Ports Status Register */
+#define SCFG_PEXMSCPORTSR(pex_idx)      (0x94 + (pex_idx) * 4)
+#define LTSSM_STATE_SHIFT       20
+#define LTSSM_STATE_MASK        0x3f
+#define LTSSM_PCIE_L0           0x11 /* L0 state */
+
+/* Symbol Timer Register and Filter Mask Register 1 */
+#define PCIE_STRFMR1 0x71c
+
+struct ls_pcie {
+        struct list_head node;
+        struct device *dev;
+        struct pci_bus *bus;
+        void __iomem *dbi;
+        struct regmap *scfg;
+        struct pcie_port pp;
+        int index;
+        int msi_irq;
+};
+
+#define to_ls_pcie(x)   container_of(x, struct ls_pcie, pp)
+
+static int ls_pcie_link_up(struct pcie_port *pp)
+{
+        u32 state;
+        struct ls_pcie *pcie = to_ls_pcie(pp);
+
+        regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
+        state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
+
+        if (state < LTSSM_PCIE_L0)
+                return 0;
+
+        return 1;
+}
+
+static void ls_pcie_host_init(struct pcie_port *pp)
+{
+        struct ls_pcie *pcie = to_ls_pcie(pp);
+        int count = 0;
+        u32 val;
+
+        dw_pcie_setup_rc(pp);
+
+        while (!ls_pcie_link_up(pp)) {
+                usleep_range(100, 1000);
+                count++;
+                if (count >= 200) {
+                        dev_err(pp->dev, "phy link never came up\n");
+                        return;
+                }
+        }
+
+        /*
+         * LS1021A Workaround for internal TKT228622
+         * to fix the INTx hang issue
+         */
+        val = ioread32(pcie->dbi + PCIE_STRFMR1);
+        val &= 0xffff;
+        iowrite32(val, pcie->dbi + PCIE_STRFMR1);
+}
+
+static struct pcie_host_ops ls_pcie_host_ops = {
+        .link_up = ls_pcie_link_up,
+        .host_init = ls_pcie_host_init,
+};
+
+static int ls_add_pcie_port(struct ls_pcie *pcie)
+{
+        struct pcie_port *pp;
+        int ret;
+
+        pp = &pcie->pp;
+        pp->dev = pcie->dev;
+        pp->dbi_base = pcie->dbi;
+        pp->root_bus_nr = -1;
+        pp->ops = &ls_pcie_host_ops;
+
+        ret = dw_pcie_host_init(pp);
+        if (ret) {
+                dev_err(pp->dev, "failed to initialize host\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static int __init ls_pcie_probe(struct platform_device *pdev)
+{
+        struct ls_pcie *pcie;
+        struct resource *dbi_base;
+        u32 index[2];
+        int ret;
+
+        pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+        if (!pcie)
+                return -ENOMEM;
+
+        pcie->dev = &pdev->dev;
+
+        dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+        if (!dbi_base) {
+                dev_err(&pdev->dev, "missing *regs* space\n");
+                return -ENODEV;
+        }
+
+        pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
+        if (IS_ERR(pcie->dbi))
+                return PTR_ERR(pcie->dbi);
+
+        pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+                                                     "fsl,pcie-scfg");
+        if (IS_ERR(pcie->scfg)) {
+                dev_err(&pdev->dev, "No syscfg phandle specified\n");
+                return PTR_ERR(pcie->scfg);
+        }
+
+        ret = of_property_read_u32_array(pdev->dev.of_node,
+                                         "fsl,pcie-scfg", index, 2);
+        if (ret)
+                return ret;
+        pcie->index = index[1];
+
+        ret = ls_add_pcie_port(pcie);
+        if (ret < 0)
+                return ret;
+
+        platform_set_drvdata(pdev, pcie);
+
+        return 0;
+}
+
+static const struct of_device_id ls_pcie_of_match[] = {
+        { .compatible = "fsl,ls1021a-pcie" },
+        { },
+};
+MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
+
+static struct platform_driver ls_pcie_driver = {
+        .driver = {
+                .name = "layerscape-pcie",
+                .owner = THIS_MODULE,
+                .of_match_table = ls_pcie_of_match,
+        },
+};
+
+module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
+
+MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
+MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index b1315e197ffb..e45f88e1244f 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -622,6 +622,7 @@ static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
 
         for (i = 0; i < pcie->nports; i++) {
                 struct mvebu_pcie_port *port = &pcie->ports[i];
+
                 if (bus->number == 0 && port->devfn == devfn)
                         return port;
                 if (bus->number != 0 &&
@@ -751,6 +752,7 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
 
         for (i = 0; i < pcie->nports; i++) {
                 struct mvebu_pcie_port *port = &pcie->ports[i];
+
                 if (!port->base)
                         continue;
                 mvebu_pcie_setup_hw(port);
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index dfed00aa3ac0..f9be37139429 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -380,6 +380,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
         /* Get the I/O and memory ranges from DT */
         for_each_of_pci_range(&parser, &range) {
                 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+
                 if (restype == IORESOURCE_IO) {
                         of_pci_range_to_resource(&range, np, &pp->io);
                         pp->io.name = "I/O";
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 61158e03ab5f..0df9b2941221 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -389,7 +389,7 @@ static void rcar_pcie_add_bus(struct pci_bus *bus)
         }
 }
 
-struct hw_pci rcar_pci = {
+static struct hw_pci rcar_pci = {
         .setup          = rcar_pcie_setup,
         .map_irq        = of_irq_parse_and_map_pci,
         .ops            = &rcar_pcie_ops,
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
index 85f594e1708f..2ca10cc887ee 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -269,7 +269,8 @@ static struct pcie_host_ops spear13xx_pcie_host_ops = {
         .host_init = spear13xx_pcie_host_init,
 };
 
-static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+static int __init spear13xx_add_pcie_port(struct pcie_port *pp,
+                                         struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         int ret;
@@ -308,10 +309,8 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)
         int ret;
 
         spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
-        if (!spear13xx_pcie) {
-                dev_err(dev, "no memory for SPEAr13xx pcie\n");
+        if (!spear13xx_pcie)
                 return -ENOMEM;
-        }
 
         spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
         if (IS_ERR(spear13xx_pcie->phy)) {
@@ -352,7 +351,7 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)
         if (of_property_read_bool(np, "st,pcie-is-gen1"))
                 spear13xx_pcie->is_gen1 = true;
 
-        ret = add_pcie_port(pp, pdev);
+        ret = spear13xx_add_pcie_port(pp, pdev);
         if (ret < 0)
                 goto fail_clk;
 
@@ -382,11 +381,11 @@ static struct platform_driver spear13xx_pcie_driver __initdata = {
 
 /* SPEAr13xx PCIe driver does not allow module unload */
 
-static int __init pcie_init(void)
+static int __init spear13xx_pcie_init(void)
 {
         return platform_driver_register(&spear13xx_pcie_driver);
 }
-module_init(pcie_init);
+module_init(spear13xx_pcie_init);
 
 MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
 MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");