aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/Makefile7
-rw-r--r--drivers/pci/access.c2
-rw-r--r--drivers/pci/hotplug/pciehp.h134
-rw-r--r--drivers/pci/hotplug/pciehp_core.c108
-rw-r--r--drivers/pci/hotplug/pciehp_ctrl.c1980
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c125
-rw-r--r--drivers/pci/hotplug/pciehp_pci.c840
-rw-r--r--drivers/pci/hotplug/pciehprm.h52
-rw-r--r--drivers/pci/hotplug/pciehprm_acpi.c1727
-rw-r--r--drivers/pci/hotplug/pciehprm_nonacpi.c464
-rw-r--r--drivers/pci/hotplug/pciehprm_nonacpi.h56
-rw-r--r--drivers/pci/hotplug/rpadlpar_core.c81
-rw-r--r--drivers/pci/hotplug/rpaphp.h2
-rw-r--r--drivers/pci/hotplug/rpaphp_pci.c76
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c2
-rw-r--r--drivers/pci/hotplug/shpchp_pci.c2
-rw-r--r--drivers/pci/msi.c20
-rw-r--r--drivers/pci/pci-acpi.c12
-rw-r--r--drivers/pci/pci-driver.c11
-rw-r--r--drivers/pci/pci.c46
-rw-r--r--drivers/pci/quirks.c19
21 files changed, 510 insertions, 5256 deletions
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 716df015f8d0..6707df968934 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,6 +6,9 @@ obj-y += access.o bus.o probe.o remove.o pci.o quirks.o \
6 pci-driver.o search.o pci-sysfs.o rom.o setup-res.o 6 pci-driver.o search.o pci-sysfs.o rom.o setup-res.o
7obj-$(CONFIG_PROC_FS) += proc.o 7obj-$(CONFIG_PROC_FS) += proc.o
8 8
9# Build PCI Express stuff if needed
10obj-$(CONFIG_PCIEPORTBUS) += pcie/
11
9obj-$(CONFIG_HOTPLUG) += hotplug.o 12obj-$(CONFIG_HOTPLUG) += hotplug.o
10 13
11# Build the PCI Hotplug drivers if we were asked to 14# Build the PCI Hotplug drivers if we were asked to
@@ -40,7 +43,3 @@ endif
40ifeq ($(CONFIG_PCI_DEBUG),y) 43ifeq ($(CONFIG_PCI_DEBUG),y)
41EXTRA_CFLAGS += -DDEBUG 44EXTRA_CFLAGS += -DDEBUG
42endif 45endif
43
44# Build PCI Express stuff if needed
45obj-$(CONFIG_PCIEPORTBUS) += pcie/
46
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 2a42add7f563..ea16805a153c 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -2,6 +2,8 @@
2#include <linux/module.h> 2#include <linux/module.h>
3#include <linux/ioport.h> 3#include <linux/ioport.h>
4 4
5#include "pci.h"
6
5/* 7/*
6 * This interrupt-safe spinlock protects all accesses to PCI 8 * This interrupt-safe spinlock protects all accesses to PCI
7 * configuration space. 9 * configuration space.
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 061ead21ef14..6a61b9f286e1 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -32,8 +32,6 @@
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/pci.h> 33#include <linux/pci.h>
34#include <linux/delay.h> 34#include <linux/delay.h>
35#include <asm/semaphore.h>
36#include <asm/io.h>
37#include <linux/pcieport_if.h> 35#include <linux/pcieport_if.h>
38#include "pci_hotplug.h" 36#include "pci_hotplug.h"
39 37
@@ -42,6 +40,7 @@
42extern int pciehp_poll_mode; 40extern int pciehp_poll_mode;
43extern int pciehp_poll_time; 41extern int pciehp_poll_time;
44extern int pciehp_debug; 42extern int pciehp_debug;
43extern int pciehp_force;
45 44
46/*#define dbg(format, arg...) do { if (pciehp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/ 45/*#define dbg(format, arg...) do { if (pciehp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
47#define dbg(format, arg...) do { if (pciehp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0) 46#define dbg(format, arg...) do { if (pciehp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
@@ -49,25 +48,11 @@ extern int pciehp_debug;
49#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg) 48#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
50#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) 49#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
51 50
52struct pci_func { 51struct hotplug_params {
53 struct pci_func *next; 52 u8 cache_line_size;
54 u8 bus; 53 u8 latency_timer;
55 u8 device; 54 u8 enable_serr;
56 u8 function; 55 u8 enable_perr;
57 u8 is_a_board;
58 u16 status;
59 u8 configured;
60 u8 switch_save;
61 u8 presence_save;
62 u32 base_length[0x06];
63 u8 base_type[0x06];
64 u16 reserved2;
65 u32 config_space[0x20];
66 struct pci_resource *mem_head;
67 struct pci_resource *p_mem_head;
68 struct pci_resource *io_head;
69 struct pci_resource *bus_head;
70 struct pci_dev* pci_dev;
71}; 56};
72 57
73struct slot { 58struct slot {
@@ -75,13 +60,7 @@ struct slot {
75 u8 bus; 60 u8 bus;
76 u8 device; 61 u8 device;
77 u32 number; 62 u32 number;
78 u8 is_a_board;
79 u8 configured;
80 u8 state; 63 u8 state;
81 u8 switch_save;
82 u8 presence_save;
83 u32 capabilities;
84 u16 reserved2;
85 struct timer_list task_event; 64 struct timer_list task_event;
86 u8 hp_slot; 65 u8 hp_slot;
87 struct controller *ctrl; 66 struct controller *ctrl;
@@ -90,42 +69,47 @@ struct slot {
90 struct list_head slot_list; 69 struct list_head slot_list;
91}; 70};
92 71
93struct pci_resource {
94 struct pci_resource * next;
95 u32 base;
96 u32 length;
97};
98
99struct event_info { 72struct event_info {
100 u32 event_type; 73 u32 event_type;
101 u8 hp_slot; 74 u8 hp_slot;
102}; 75};
103 76
77typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
78
79struct php_ctlr_state_s {
80 struct php_ctlr_state_s *pnext;
81 struct pci_dev *pci_dev;
82 unsigned int irq;
83 unsigned long flags; /* spinlock's */
84 u32 slot_device_offset;
85 u32 num_slots;
86 struct timer_list int_poll_timer; /* Added for poll event */
87 php_intr_callback_t attention_button_callback;
88 php_intr_callback_t switch_change_callback;
89 php_intr_callback_t presence_change_callback;
90 php_intr_callback_t power_fault_callback;
91 void *callback_instance_id;
92 struct ctrl_reg *creg; /* Ptr to controller register space */
93};
94
95#define MAX_EVENTS 10
104struct controller { 96struct controller {
105 struct controller *next; 97 struct controller *next;
106 struct semaphore crit_sect; /* critical section semaphore */ 98 struct semaphore crit_sect; /* critical section semaphore */
107 void *hpc_ctlr_handle; /* HPC controller handle */ 99 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
108 int num_slots; /* Number of slots on ctlr */ 100 int num_slots; /* Number of slots on ctlr */
109 int slot_num_inc; /* 1 or -1 */ 101 int slot_num_inc; /* 1 or -1 */
110 struct pci_resource *mem_head;
111 struct pci_resource *p_mem_head;
112 struct pci_resource *io_head;
113 struct pci_resource *bus_head;
114 struct pci_dev *pci_dev; 102 struct pci_dev *pci_dev;
115 struct pci_bus *pci_bus; 103 struct pci_bus *pci_bus;
116 struct event_info event_queue[10]; 104 struct event_info event_queue[MAX_EVENTS];
117 struct slot *slot; 105 struct slot *slot;
118 struct hpc_ops *hpc_ops; 106 struct hpc_ops *hpc_ops;
119 wait_queue_head_t queue; /* sleep & wake process */ 107 wait_queue_head_t queue; /* sleep & wake process */
120 u8 next_event; 108 u8 next_event;
121 u8 seg;
122 u8 bus; 109 u8 bus;
123 u8 device; 110 u8 device;
124 u8 function; 111 u8 function;
125 u8 rev;
126 u8 slot_device_offset; 112 u8 slot_device_offset;
127 u8 add_support;
128 enum pci_bus_speed speed;
129 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */ 113 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */
130 u8 slot_bus; /* Bus where the slots handled by this controller sit */ 114 u8 slot_bus; /* Bus where the slots handled by this controller sit */
131 u8 ctrlcap; 115 u8 ctrlcap;
@@ -133,20 +117,6 @@ struct controller {
133 u8 cap_base; 117 u8 cap_base;
134}; 118};
135 119
136struct irq_mapping {
137 u8 barber_pole;
138 u8 valid_INT;
139 u8 interrupt[4];
140};
141
142struct resource_lists {
143 struct pci_resource *mem_head;
144 struct pci_resource *p_mem_head;
145 struct pci_resource *io_head;
146 struct pci_resource *bus_head;
147 struct irq_mapping *irqs;
148};
149
150#define INT_BUTTON_IGNORE 0 120#define INT_BUTTON_IGNORE 0
151#define INT_PRESENCE_ON 1 121#define INT_PRESENCE_ON 1
152#define INT_PRESENCE_OFF 2 122#define INT_PRESENCE_OFF 2
@@ -200,21 +170,14 @@ struct resource_lists {
200 * error Messages 170 * error Messages
201 */ 171 */
202#define msg_initialization_err "Initialization failure, error=%d\n" 172#define msg_initialization_err "Initialization failure, error=%d\n"
203#define msg_HPC_rev_error "Unsupported revision of the PCI hot plug controller found.\n"
204#define msg_HPC_non_pcie "The PCI hot plug controller is not supported by this driver.\n"
205#define msg_HPC_not_supported "This system is not supported by this version of pciephd module. Upgrade to a newer version of pciehpd\n"
206#define msg_unable_to_save "Unable to store PCI hot plug add resource information. This system must be rebooted before adding any PCI devices.\n"
207#define msg_button_on "PCI slot #%d - powering on due to button press.\n" 173#define msg_button_on "PCI slot #%d - powering on due to button press.\n"
208#define msg_button_off "PCI slot #%d - powering off due to button press.\n" 174#define msg_button_off "PCI slot #%d - powering off due to button press.\n"
209#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n" 175#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
210#define msg_button_ignore "PCI slot #%d - button press ignored. (action in progress...)\n" 176#define msg_button_ignore "PCI slot #%d - button press ignored. (action in progress...)\n"
211 177
212/* controller functions */ 178/* controller functions */
213extern int pciehprm_find_available_resources (struct controller *ctrl);
214extern int pciehp_event_start_thread (void); 179extern int pciehp_event_start_thread (void);
215extern void pciehp_event_stop_thread (void); 180extern void pciehp_event_stop_thread (void);
216extern struct pci_func *pciehp_slot_create (unsigned char busnumber);
217extern struct pci_func *pciehp_slot_find (unsigned char bus, unsigned char device, unsigned char index);
218extern int pciehp_enable_slot (struct slot *slot); 181extern int pciehp_enable_slot (struct slot *slot);
219extern int pciehp_disable_slot (struct slot *slot); 182extern int pciehp_disable_slot (struct slot *slot);
220 183
@@ -224,25 +187,17 @@ extern u8 pciehp_handle_presence_change (u8 hp_slot, void *inst_id);
224extern u8 pciehp_handle_power_fault (u8 hp_slot, void *inst_id); 187extern u8 pciehp_handle_power_fault (u8 hp_slot, void *inst_id);
225/* extern void long_delay (int delay); */ 188/* extern void long_delay (int delay); */
226 189
227/* resource functions */
228extern int pciehp_resource_sort_and_combine (struct pci_resource **head);
229
230/* pci functions */ 190/* pci functions */
231extern int pciehp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num); 191extern int pciehp_configure_device (struct slot *p_slot);
232/*extern int pciehp_get_bus_dev (struct controller *ctrl, u8 *bus_num, u8 *dev_num, struct slot *slot);*/ 192extern int pciehp_unconfigure_device (struct slot *p_slot);
233extern int pciehp_save_config (struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num); 193extern int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev);
234extern int pciehp_save_used_resources (struct controller *ctrl, struct pci_func * func, int flag); 194extern void pciehp_get_hp_params_from_firmware(struct pci_dev *dev,
235extern int pciehp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot); 195 struct hotplug_params *hpp);
236extern void pciehp_destroy_board_resources (struct pci_func * func); 196
237extern int pciehp_return_board_resources (struct pci_func * func, struct resource_lists * resources);
238extern void pciehp_destroy_resource_list (struct resource_lists * resources);
239extern int pciehp_configure_device (struct controller* ctrl, struct pci_func* func);
240extern int pciehp_unconfigure_device (struct pci_func* func);
241 197
242 198
243/* Global variables */ 199/* Global variables */
244extern struct controller *pciehp_ctrl_list; 200extern struct controller *pciehp_ctrl_list;
245extern struct pci_func *pciehp_slot_list[256];
246 201
247/* Inline functions */ 202/* Inline functions */
248 203
@@ -252,12 +207,9 @@ static inline struct slot *pciehp_find_slot(struct controller *ctrl, u8 device)
252 207
253 p_slot = ctrl->slot; 208 p_slot = ctrl->slot;
254 209
255 dbg("p_slot = %p\n", p_slot);
256
257 while (p_slot && (p_slot->device != device)) { 210 while (p_slot && (p_slot->device != device)) {
258 tmp_slot = p_slot; 211 tmp_slot = p_slot;
259 p_slot = p_slot->next; 212 p_slot = p_slot->next;
260 dbg("In while loop, p_slot = %p\n", p_slot);
261 } 213 }
262 if (p_slot == NULL) { 214 if (p_slot == NULL) {
263 err("ERROR: pciehp_find_slot device=0x%x\n", device); 215 err("ERROR: pciehp_find_slot device=0x%x\n", device);
@@ -273,7 +225,6 @@ static inline int wait_for_ctrl_irq(struct controller *ctrl)
273 225
274 DECLARE_WAITQUEUE(wait, current); 226 DECLARE_WAITQUEUE(wait, current);
275 227
276 dbg("%s : start\n", __FUNCTION__);
277 add_wait_queue(&ctrl->queue, &wait); 228 add_wait_queue(&ctrl->queue, &wait);
278 if (!pciehp_poll_mode) 229 if (!pciehp_poll_mode)
279 /* Sleep for up to 1 second */ 230 /* Sleep for up to 1 second */
@@ -285,19 +236,9 @@ static inline int wait_for_ctrl_irq(struct controller *ctrl)
285 if (signal_pending(current)) 236 if (signal_pending(current))
286 retval = -EINTR; 237 retval = -EINTR;
287 238
288 dbg("%s : end\n", __FUNCTION__);
289 return retval; 239 return retval;
290} 240}
291 241
292/* Puts node back in the resource list pointed to by head */
293static inline void return_resource(struct pci_resource **head, struct pci_resource *node)
294{
295 if (!node || !head)
296 return;
297 node->next = *head;
298 *head = node;
299}
300
301#define SLOT_NAME_SIZE 10 242#define SLOT_NAME_SIZE 10
302 243
303static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot) 244static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot)
@@ -311,14 +252,7 @@ enum php_ctlr_type {
311 ACPI 252 ACPI
312}; 253};
313 254
314typedef u8(*php_intr_callback_t) (unsigned int change_id, void *instance_id); 255int pcie_init(struct controller *ctrl, struct pcie_device *dev);
315
316int pcie_init(struct controller *ctrl, struct pcie_device *dev,
317 php_intr_callback_t attention_button_callback,
318 php_intr_callback_t switch_change_callback,
319 php_intr_callback_t presence_change_callback,
320 php_intr_callback_t power_fault_callback);
321
322 256
323/* This has no meaning for PCI Express, as there is only 1 slot per port */ 257/* This has no meaning for PCI Express, as there is only 1 slot per port */
324int pcie_get_ctlr_slot_config(struct controller *ctrl, 258int pcie_get_ctlr_slot_config(struct controller *ctrl,
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index cafc7eadcf80..8df704860348 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -27,27 +27,20 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/moduleparam.h> 31#include <linux/moduleparam.h>
33#include <linux/kernel.h> 32#include <linux/kernel.h>
34#include <linux/types.h> 33#include <linux/types.h>
35#include <linux/proc_fs.h>
36#include <linux/slab.h>
37#include <linux/workqueue.h>
38#include <linux/pci.h> 34#include <linux/pci.h>
39#include <linux/init.h>
40#include <asm/uaccess.h>
41#include "pciehp.h" 35#include "pciehp.h"
42#include "pciehprm.h"
43#include <linux/interrupt.h> 36#include <linux/interrupt.h>
44 37
45/* Global variables */ 38/* Global variables */
46int pciehp_debug; 39int pciehp_debug;
47int pciehp_poll_mode; 40int pciehp_poll_mode;
48int pciehp_poll_time; 41int pciehp_poll_time;
42int pciehp_force;
49struct controller *pciehp_ctrl_list; 43struct controller *pciehp_ctrl_list;
50struct pci_func *pciehp_slot_list[256];
51 44
52#define DRIVER_VERSION "0.4" 45#define DRIVER_VERSION "0.4"
53#define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>" 46#define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>"
@@ -60,9 +53,11 @@ MODULE_LICENSE("GPL");
60module_param(pciehp_debug, bool, 0644); 53module_param(pciehp_debug, bool, 0644);
61module_param(pciehp_poll_mode, bool, 0644); 54module_param(pciehp_poll_mode, bool, 0644);
62module_param(pciehp_poll_time, int, 0644); 55module_param(pciehp_poll_time, int, 0644);
56module_param(pciehp_force, bool, 0644);
63MODULE_PARM_DESC(pciehp_debug, "Debugging mode enabled or not"); 57MODULE_PARM_DESC(pciehp_debug, "Debugging mode enabled or not");
64MODULE_PARM_DESC(pciehp_poll_mode, "Using polling mechanism for hot-plug events or not"); 58MODULE_PARM_DESC(pciehp_poll_mode, "Using polling mechanism for hot-plug events or not");
65MODULE_PARM_DESC(pciehp_poll_time, "Polling mechanism frequency, in seconds"); 59MODULE_PARM_DESC(pciehp_poll_time, "Polling mechanism frequency, in seconds");
60MODULE_PARM_DESC(pciehp_force, "Force pciehp, even if _OSC and OSHP are missing");
66 61
67#define PCIE_MODULE_NAME "pciehp" 62#define PCIE_MODULE_NAME "pciehp"
68 63
@@ -114,8 +109,6 @@ static int init_slots(struct controller *ctrl)
114 u32 slot_number; 109 u32 slot_number;
115 int result = -ENOMEM; 110 int result = -ENOMEM;
116 111
117 dbg("%s\n",__FUNCTION__);
118
119 number_of_slots = ctrl->num_slots; 112 number_of_slots = ctrl->num_slots;
120 slot_device = ctrl->slot_device_offset; 113 slot_device = ctrl->slot_device_offset;
121 slot_number = ctrl->first_slot; 114 slot_number = ctrl->first_slot;
@@ -370,7 +363,6 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
370 u8 value; 363 u8 value;
371 struct pci_dev *pdev; 364 struct pci_dev *pdev;
372 365
373 dbg("%s: Called by hp_drv\n", __FUNCTION__);
374 ctrl = kmalloc(sizeof(*ctrl), GFP_KERNEL); 366 ctrl = kmalloc(sizeof(*ctrl), GFP_KERNEL);
375 if (!ctrl) { 367 if (!ctrl) {
376 err("%s : out of memory\n", __FUNCTION__); 368 err("%s : out of memory\n", __FUNCTION__);
@@ -378,22 +370,15 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
378 } 370 }
379 memset(ctrl, 0, sizeof(struct controller)); 371 memset(ctrl, 0, sizeof(struct controller));
380 372
381 dbg("%s: DRV_thread pid = %d\n", __FUNCTION__, current->pid);
382
383 pdev = dev->port; 373 pdev = dev->port;
374 ctrl->pci_dev = pdev;
384 375
385 rc = pcie_init(ctrl, dev, 376 rc = pcie_init(ctrl, dev);
386 (php_intr_callback_t) pciehp_handle_attention_button,
387 (php_intr_callback_t) pciehp_handle_switch_change,
388 (php_intr_callback_t) pciehp_handle_presence_change,
389 (php_intr_callback_t) pciehp_handle_power_fault);
390 if (rc) { 377 if (rc) {
391 dbg("%s: controller initialization failed\n", PCIE_MODULE_NAME); 378 dbg("%s: controller initialization failed\n", PCIE_MODULE_NAME);
392 goto err_out_free_ctrl; 379 goto err_out_free_ctrl;
393 } 380 }
394 381
395 ctrl->pci_dev = pdev;
396
397 pci_set_drvdata(pdev, ctrl); 382 pci_set_drvdata(pdev, ctrl);
398 383
399 ctrl->pci_bus = kmalloc(sizeof(*ctrl->pci_bus), GFP_KERNEL); 384 ctrl->pci_bus = kmalloc(sizeof(*ctrl->pci_bus), GFP_KERNEL);
@@ -402,7 +387,6 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
402 rc = -ENOMEM; 387 rc = -ENOMEM;
403 goto err_out_unmap_mmio_region; 388 goto err_out_unmap_mmio_region;
404 } 389 }
405 dbg("%s: ctrl->pci_bus %p\n", __FUNCTION__, ctrl->pci_bus);
406 memcpy (ctrl->pci_bus, pdev->bus, sizeof (*ctrl->pci_bus)); 390 memcpy (ctrl->pci_bus, pdev->bus, sizeof (*ctrl->pci_bus));
407 ctrl->bus = pdev->bus->number; /* ctrl bus */ 391 ctrl->bus = pdev->bus->number; /* ctrl bus */
408 ctrl->slot_bus = pdev->subordinate->number; /* bus controlled by this HPC */ 392 ctrl->slot_bus = pdev->subordinate->number; /* bus controlled by this HPC */
@@ -424,25 +408,6 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
424 first_device_num = ctrl->slot_device_offset; 408 first_device_num = ctrl->slot_device_offset;
425 num_ctlr_slots = ctrl->num_slots; 409 num_ctlr_slots = ctrl->num_slots;
426 410
427 /* Store PCI Config Space for all devices on this bus */
428 dbg("%s: Before calling pciehp_save_config, ctrl->bus %x,ctrl->slot_bus %x\n",
429 __FUNCTION__,ctrl->bus, ctrl->slot_bus);
430 rc = pciehp_save_config(ctrl, ctrl->slot_bus, num_ctlr_slots, first_device_num);
431 if (rc) {
432 err("%s: unable to save PCI configuration data, error %d\n", __FUNCTION__, rc);
433 goto err_out_free_ctrl_bus;
434 }
435
436 /* Get IO, memory, and IRQ resources for new devices */
437 rc = pciehprm_find_available_resources(ctrl);
438 ctrl->add_support = !rc;
439
440 if (rc) {
441 dbg("pciehprm_find_available_resources = %#x\n", rc);
442 err("unable to locate PCI configuration resources for hot plug add.\n");
443 goto err_out_free_ctrl_bus;
444 }
445
446 /* Setup the slot information structures */ 411 /* Setup the slot information structures */
447 rc = init_slots(ctrl); 412 rc = init_slots(ctrl);
448 if (rc) { 413 if (rc) {
@@ -451,7 +416,6 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
451 } 416 }
452 417
453 t_slot = pciehp_find_slot(ctrl, first_device_num); 418 t_slot = pciehp_find_slot(ctrl, first_device_num);
454 dbg("%s: t_slot %p\n", __FUNCTION__, t_slot);
455 419
456 /* Finish setting up the hot plug ctrl device */ 420 /* Finish setting up the hot plug ctrl device */
457 ctrl->next_event = 0; 421 ctrl->next_event = 0;
@@ -468,7 +432,6 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
468 down(&ctrl->crit_sect); 432 down(&ctrl->crit_sect);
469 433
470 t_slot->hpc_ops->get_adapter_status(t_slot, &value); /* Check if slot is occupied */ 434 t_slot->hpc_ops->get_adapter_status(t_slot, &value); /* Check if slot is occupied */
471 dbg("%s: adpater value %x\n", __FUNCTION__, value);
472 435
473 if ((POWER_CTRL(ctrl->ctrlcap)) && !value) { 436 if ((POWER_CTRL(ctrl->ctrlcap)) && !value) {
474 rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/ 437 rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/
@@ -501,7 +464,6 @@ err_out_none:
501 464
502static int pcie_start_thread(void) 465static int pcie_start_thread(void)
503{ 466{
504 int loop;
505 int retval = 0; 467 int retval = 0;
506 468
507 dbg("Initialize + Start the notification/polling mechanism \n"); 469 dbg("Initialize + Start the notification/polling mechanism \n");
@@ -512,32 +474,11 @@ static int pcie_start_thread(void)
512 return retval; 474 return retval;
513 } 475 }
514 476
515 dbg("Initialize slot lists\n");
516 /* One slot list for each bus in the system */
517 for (loop = 0; loop < 256; loop++) {
518 pciehp_slot_list[loop] = NULL;
519 }
520
521 return retval; 477 return retval;
522} 478}
523 479
524static inline void __exit
525free_pciehp_res(struct pci_resource *res)
526{
527 struct pci_resource *tres;
528
529 while (res) {
530 tres = res;
531 res = res->next;
532 kfree(tres);
533 }
534}
535
536static void __exit unload_pciehpd(void) 480static void __exit unload_pciehpd(void)
537{ 481{
538 struct pci_func *next;
539 struct pci_func *TempSlot;
540 int loop;
541 struct controller *ctrl; 482 struct controller *ctrl;
542 struct controller *tctrl; 483 struct controller *tctrl;
543 484
@@ -546,11 +487,6 @@ static void __exit unload_pciehpd(void)
546 while (ctrl) { 487 while (ctrl) {
547 cleanup_slots(ctrl); 488 cleanup_slots(ctrl);
548 489
549 free_pciehp_res(ctrl->io_head);
550 free_pciehp_res(ctrl->mem_head);
551 free_pciehp_res(ctrl->p_mem_head);
552 free_pciehp_res(ctrl->bus_head);
553
554 kfree (ctrl->pci_bus); 490 kfree (ctrl->pci_bus);
555 491
556 ctrl->hpc_ops->release_ctlr(ctrl); 492 ctrl->hpc_ops->release_ctlr(ctrl);
@@ -561,20 +497,6 @@ static void __exit unload_pciehpd(void)
561 kfree(tctrl); 497 kfree(tctrl);
562 } 498 }
563 499
564 for (loop = 0; loop < 256; loop++) {
565 next = pciehp_slot_list[loop];
566 while (next != NULL) {
567 free_pciehp_res(next->io_head);
568 free_pciehp_res(next->mem_head);
569 free_pciehp_res(next->p_mem_head);
570 free_pciehp_res(next->bus_head);
571
572 TempSlot = next;
573 next = next->next;
574 kfree(TempSlot);
575 }
576 }
577
578 /* Stop the notification mechanism */ 500 /* Stop the notification mechanism */
579 pciehp_event_stop_thread(); 501 pciehp_event_stop_thread();
580 502
@@ -639,21 +561,16 @@ static int __init pcied_init(void)
639 if (retval) 561 if (retval)
640 goto error_hpc_init; 562 goto error_hpc_init;
641 563
642 retval = pciehprm_init(PCI); 564 retval = pcie_port_service_register(&hpdriver_portdrv);
643 if (!retval) { 565 dbg("pcie_port_service_register = %d\n", retval);
644 retval = pcie_port_service_register(&hpdriver_portdrv); 566 info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
645 dbg("pcie_port_service_register = %d\n", retval); 567 if (retval)
646 info(DRIVER_DESC " version: " DRIVER_VERSION "\n"); 568 dbg("%s: Failure to register service\n", __FUNCTION__);
647 if (retval)
648 dbg("%s: Failure to register service\n", __FUNCTION__);
649 }
650 569
651error_hpc_init: 570error_hpc_init:
652 if (retval) { 571 if (retval) {
653 pciehprm_cleanup();
654 pciehp_event_stop_thread(); 572 pciehp_event_stop_thread();
655 } else 573 };
656 pciehprm_print_pirt();
657 574
658 return retval; 575 return retval;
659} 576}
@@ -663,9 +580,6 @@ static void __exit pcied_cleanup(void)
663 dbg("unload_pciehpd()\n"); 580 dbg("unload_pciehpd()\n");
664 unload_pciehpd(); 581 unload_pciehpd();
665 582
666 pciehprm_cleanup();
667
668 dbg("pcie_port_service_unregister\n");
669 pcie_port_service_unregister(&hpdriver_portdrv); 583 pcie_port_service_unregister(&hpdriver_portdrv);
670 584
671 info(DRIVER_DESC " version: " DRIVER_VERSION " unloaded\n"); 585 info(DRIVER_DESC " version: " DRIVER_VERSION " unloaded\n");
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c
index 898f6da6f0de..83c4b865718a 100644
--- a/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/drivers/pci/hotplug/pciehp_ctrl.c
@@ -27,25 +27,14 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/slab.h>
35#include <linux/workqueue.h>
36#include <linux/interrupt.h>
37#include <linux/delay.h>
38#include <linux/wait.h>
39#include <linux/smp_lock.h> 33#include <linux/smp_lock.h>
40#include <linux/pci.h> 34#include <linux/pci.h>
41#include "../pci.h" 35#include "../pci.h"
42#include "pciehp.h" 36#include "pciehp.h"
43#include "pciehprm.h"
44 37
45static u32 configure_new_device(struct controller *ctrl, struct pci_func *func,
46 u8 behind_bridge, struct resource_lists *resources, u8 bridge_bus, u8 bridge_dev);
47static int configure_new_function( struct controller *ctrl, struct pci_func *func,
48 u8 behind_bridge, struct resource_lists *resources, u8 bridge_bus, u8 bridge_dev);
49static void interrupt_event_handler(struct controller *ctrl); 38static void interrupt_event_handler(struct controller *ctrl);
50 39
51static struct semaphore event_semaphore; /* mutex for process loop (up if something to process) */ 40static struct semaphore event_semaphore; /* mutex for process loop (up if something to process) */
@@ -60,22 +49,18 @@ u8 pciehp_handle_attention_button(u8 hp_slot, void *inst_id)
60 struct slot *p_slot; 49 struct slot *p_slot;
61 u8 rc = 0; 50 u8 rc = 0;
62 u8 getstatus; 51 u8 getstatus;
63 struct pci_func *func;
64 struct event_info *taskInfo; 52 struct event_info *taskInfo;
65 53
66 /* Attention Button Change */ 54 /* Attention Button Change */
67 dbg("pciehp: Attention button interrupt received.\n"); 55 dbg("pciehp: Attention button interrupt received.\n");
68 56
69 func = pciehp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
70
71 /* This is the structure that tells the worker thread what to do */ 57 /* This is the structure that tells the worker thread what to do */
72 taskInfo = &(ctrl->event_queue[ctrl->next_event]); 58 taskInfo = &(ctrl->event_queue[ctrl->next_event]);
73 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 59 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
74 60
75 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
76 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 61 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
77 62
78 ctrl->next_event = (ctrl->next_event + 1) % 10; 63 ctrl->next_event = (ctrl->next_event + 1) % MAX_EVENTS;
79 taskInfo->hp_slot = hp_slot; 64 taskInfo->hp_slot = hp_slot;
80 65
81 rc++; 66 rc++;
@@ -117,24 +102,20 @@ u8 pciehp_handle_switch_change(u8 hp_slot, void *inst_id)
117 struct slot *p_slot; 102 struct slot *p_slot;
118 u8 rc = 0; 103 u8 rc = 0;
119 u8 getstatus; 104 u8 getstatus;
120 struct pci_func *func;
121 struct event_info *taskInfo; 105 struct event_info *taskInfo;
122 106
123 /* Switch Change */ 107 /* Switch Change */
124 dbg("pciehp: Switch interrupt received.\n"); 108 dbg("pciehp: Switch interrupt received.\n");
125 109
126 func = pciehp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
127
128 /* This is the structure that tells the worker thread 110 /* This is the structure that tells the worker thread
129 * what to do 111 * what to do
130 */ 112 */
131 taskInfo = &(ctrl->event_queue[ctrl->next_event]); 113 taskInfo = &(ctrl->event_queue[ctrl->next_event]);
132 ctrl->next_event = (ctrl->next_event + 1) % 10; 114 ctrl->next_event = (ctrl->next_event + 1) % MAX_EVENTS;
133 taskInfo->hp_slot = hp_slot; 115 taskInfo->hp_slot = hp_slot;
134 116
135 rc++; 117 rc++;
136 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 118 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
137 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
138 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 119 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
139 120
140 if (getstatus) { 121 if (getstatus) {
@@ -142,14 +123,12 @@ u8 pciehp_handle_switch_change(u8 hp_slot, void *inst_id)
142 * Switch opened 123 * Switch opened
143 */ 124 */
144 info("Latch open on Slot(%d)\n", ctrl->first_slot + hp_slot); 125 info("Latch open on Slot(%d)\n", ctrl->first_slot + hp_slot);
145 func->switch_save = 0;
146 taskInfo->event_type = INT_SWITCH_OPEN; 126 taskInfo->event_type = INT_SWITCH_OPEN;
147 } else { 127 } else {
148 /* 128 /*
149 * Switch closed 129 * Switch closed
150 */ 130 */
151 info("Latch close on Slot(%d)\n", ctrl->first_slot + hp_slot); 131 info("Latch close on Slot(%d)\n", ctrl->first_slot + hp_slot);
152 func->switch_save = 0x10;
153 taskInfo->event_type = INT_SWITCH_CLOSE; 132 taskInfo->event_type = INT_SWITCH_CLOSE;
154 } 133 }
155 134
@@ -163,20 +142,17 @@ u8 pciehp_handle_presence_change(u8 hp_slot, void *inst_id)
163{ 142{
164 struct controller *ctrl = (struct controller *) inst_id; 143 struct controller *ctrl = (struct controller *) inst_id;
165 struct slot *p_slot; 144 struct slot *p_slot;
166 u8 rc = 0; 145 u8 presence_save, rc = 0;
167 struct pci_func *func;
168 struct event_info *taskInfo; 146 struct event_info *taskInfo;
169 147
170 /* Presence Change */ 148 /* Presence Change */
171 dbg("pciehp: Presence/Notify input change.\n"); 149 dbg("pciehp: Presence/Notify input change.\n");
172 150
173 func = pciehp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
174
175 /* This is the structure that tells the worker thread 151 /* This is the structure that tells the worker thread
176 * what to do 152 * what to do
177 */ 153 */
178 taskInfo = &(ctrl->event_queue[ctrl->next_event]); 154 taskInfo = &(ctrl->event_queue[ctrl->next_event]);
179 ctrl->next_event = (ctrl->next_event + 1) % 10; 155 ctrl->next_event = (ctrl->next_event + 1) % MAX_EVENTS;
180 taskInfo->hp_slot = hp_slot; 156 taskInfo->hp_slot = hp_slot;
181 157
182 rc++; 158 rc++;
@@ -185,8 +161,8 @@ u8 pciehp_handle_presence_change(u8 hp_slot, void *inst_id)
185 /* Switch is open, assume a presence change 161 /* Switch is open, assume a presence change
186 * Save the presence state 162 * Save the presence state
187 */ 163 */
188 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save)); 164 p_slot->hpc_ops->get_adapter_status(p_slot, &presence_save);
189 if (func->presence_save) { 165 if (presence_save) {
190 /* 166 /*
191 * Card Present 167 * Card Present
192 */ 168 */
@@ -211,19 +187,16 @@ u8 pciehp_handle_power_fault(u8 hp_slot, void *inst_id)
211 struct controller *ctrl = (struct controller *) inst_id; 187 struct controller *ctrl = (struct controller *) inst_id;
212 struct slot *p_slot; 188 struct slot *p_slot;
213 u8 rc = 0; 189 u8 rc = 0;
214 struct pci_func *func;
215 struct event_info *taskInfo; 190 struct event_info *taskInfo;
216 191
217 /* power fault */ 192 /* power fault */
218 dbg("pciehp: Power fault interrupt received.\n"); 193 dbg("pciehp: Power fault interrupt received.\n");
219 194
220 func = pciehp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
221
222 /* this is the structure that tells the worker thread 195 /* this is the structure that tells the worker thread
223 * what to do 196 * what to do
224 */ 197 */
225 taskInfo = &(ctrl->event_queue[ctrl->next_event]); 198 taskInfo = &(ctrl->event_queue[ctrl->next_event]);
226 ctrl->next_event = (ctrl->next_event + 1) % 10; 199 ctrl->next_event = (ctrl->next_event + 1) % MAX_EVENTS;
227 taskInfo->hp_slot = hp_slot; 200 taskInfo->hp_slot = hp_slot;
228 201
229 rc++; 202 rc++;
@@ -234,7 +207,6 @@ u8 pciehp_handle_power_fault(u8 hp_slot, void *inst_id)
234 * power fault Cleared 207 * power fault Cleared
235 */ 208 */
236 info("Power fault cleared on Slot(%d)\n", ctrl->first_slot + hp_slot); 209 info("Power fault cleared on Slot(%d)\n", ctrl->first_slot + hp_slot);
237 func->status = 0x00;
238 taskInfo->event_type = INT_POWER_FAULT_CLEAR; 210 taskInfo->event_type = INT_POWER_FAULT_CLEAR;
239 } else { 211 } else {
240 /* 212 /*
@@ -242,8 +214,6 @@ u8 pciehp_handle_power_fault(u8 hp_slot, void *inst_id)
242 */ 214 */
243 info("Power fault on Slot(%d)\n", ctrl->first_slot + hp_slot); 215 info("Power fault on Slot(%d)\n", ctrl->first_slot + hp_slot);
244 taskInfo->event_type = INT_POWER_FAULT; 216 taskInfo->event_type = INT_POWER_FAULT;
245 /* set power fault status for this board */
246 func->status = 0xFF;
247 info("power fault bit %x set\n", hp_slot); 217 info("power fault bit %x set\n", hp_slot);
248 } 218 }
249 if (rc) 219 if (rc)
@@ -252,810 +222,6 @@ u8 pciehp_handle_power_fault(u8 hp_slot, void *inst_id)
252 return rc; 222 return rc;
253} 223}
254 224
255
256/**
257 * sort_by_size: sort nodes by their length, smallest first.
258 *
259 * @head: list to sort
260 */
261static int sort_by_size(struct pci_resource **head)
262{
263 struct pci_resource *current_res;
264 struct pci_resource *next_res;
265 int out_of_order = 1;
266
267 if (!(*head))
268 return 1;
269
270 if (!((*head)->next))
271 return 0;
272
273 while (out_of_order) {
274 out_of_order = 0;
275
276 /* Special case for swapping list head */
277 if (((*head)->next) &&
278 ((*head)->length > (*head)->next->length)) {
279 out_of_order++;
280 current_res = *head;
281 *head = (*head)->next;
282 current_res->next = (*head)->next;
283 (*head)->next = current_res;
284 }
285
286 current_res = *head;
287
288 while (current_res->next && current_res->next->next) {
289 if (current_res->next->length > current_res->next->next->length) {
290 out_of_order++;
291 next_res = current_res->next;
292 current_res->next = current_res->next->next;
293 current_res = current_res->next;
294 next_res->next = current_res->next;
295 current_res->next = next_res;
296 } else
297 current_res = current_res->next;
298 }
299 } /* End of out_of_order loop */
300
301 return 0;
302}
303
304
305/*
306 * sort_by_max_size
307 *
308 * Sorts nodes on the list by their length.
309 * Largest first.
310 *
311 */
312static int sort_by_max_size(struct pci_resource **head)
313{
314 struct pci_resource *current_res;
315 struct pci_resource *next_res;
316 int out_of_order = 1;
317
318 if (!(*head))
319 return 1;
320
321 if (!((*head)->next))
322 return 0;
323
324 while (out_of_order) {
325 out_of_order = 0;
326
327 /* Special case for swapping list head */
328 if (((*head)->next) &&
329 ((*head)->length < (*head)->next->length)) {
330 out_of_order++;
331 current_res = *head;
332 *head = (*head)->next;
333 current_res->next = (*head)->next;
334 (*head)->next = current_res;
335 }
336
337 current_res = *head;
338
339 while (current_res->next && current_res->next->next) {
340 if (current_res->next->length < current_res->next->next->length) {
341 out_of_order++;
342 next_res = current_res->next;
343 current_res->next = current_res->next->next;
344 current_res = current_res->next;
345 next_res->next = current_res->next;
346 current_res->next = next_res;
347 } else
348 current_res = current_res->next;
349 }
350 } /* End of out_of_order loop */
351
352 return 0;
353}
354
355
356/**
357 * do_pre_bridge_resource_split: return one unused resource node
358 * @head: list to scan
359 *
360 */
361static struct pci_resource *
362do_pre_bridge_resource_split(struct pci_resource **head,
363 struct pci_resource **orig_head, u32 alignment)
364{
365 struct pci_resource *prevnode = NULL;
366 struct pci_resource *node;
367 struct pci_resource *split_node;
368 u32 rc;
369 u32 temp_dword;
370 dbg("do_pre_bridge_resource_split\n");
371
372 if (!(*head) || !(*orig_head))
373 return NULL;
374
375 rc = pciehp_resource_sort_and_combine(head);
376
377 if (rc)
378 return NULL;
379
380 if ((*head)->base != (*orig_head)->base)
381 return NULL;
382
383 if ((*head)->length == (*orig_head)->length)
384 return NULL;
385
386
387 /* If we got here, there the bridge requires some of the resource, but
388 * we may be able to split some off of the front
389 */
390 node = *head;
391
392 if (node->length & (alignment -1)) {
393 /* this one isn't an aligned length, so we'll make a new entry
394 * and split it up.
395 */
396 split_node = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
397
398 if (!split_node)
399 return NULL;
400
401 temp_dword = (node->length | (alignment-1)) + 1 - alignment;
402
403 split_node->base = node->base;
404 split_node->length = temp_dword;
405
406 node->length -= temp_dword;
407 node->base += split_node->length;
408
409 /* Put it in the list */
410 *head = split_node;
411 split_node->next = node;
412 }
413
414 if (node->length < alignment)
415 return NULL;
416
417 /* Now unlink it */
418 if (*head == node) {
419 *head = node->next;
420 } else {
421 prevnode = *head;
422 while (prevnode->next != node)
423 prevnode = prevnode->next;
424
425 prevnode->next = node->next;
426 }
427 node->next = NULL;
428
429 return node;
430}
431
432
433/**
434 * do_bridge_resource_split: return one unused resource node
435 * @head: list to scan
436 *
437 */
438static struct pci_resource *
439do_bridge_resource_split(struct pci_resource **head, u32 alignment)
440{
441 struct pci_resource *prevnode = NULL;
442 struct pci_resource *node;
443 u32 rc;
444 u32 temp_dword;
445
446 if (!(*head))
447 return NULL;
448
449 rc = pciehp_resource_sort_and_combine(head);
450
451 if (rc)
452 return NULL;
453
454 node = *head;
455
456 while (node->next) {
457 prevnode = node;
458 node = node->next;
459 kfree(prevnode);
460 }
461
462 if (node->length < alignment) {
463 kfree(node);
464 return NULL;
465 }
466
467 if (node->base & (alignment - 1)) {
468 /* Short circuit if adjusted size is too small */
469 temp_dword = (node->base | (alignment-1)) + 1;
470 if ((node->length - (temp_dword - node->base)) < alignment) {
471 kfree(node);
472 return NULL;
473 }
474
475 node->length -= (temp_dword - node->base);
476 node->base = temp_dword;
477 }
478
479 if (node->length & (alignment - 1)) {
480 /* There's stuff in use after this node */
481 kfree(node);
482 return NULL;
483 }
484
485 return node;
486}
487
488
489/*
490 * get_io_resource
491 *
492 * this function sorts the resource list by size and then
493 * returns the first node of "size" length that is not in the
494 * ISA aliasing window. If it finds a node larger than "size"
495 * it will split it up.
496 *
497 * size must be a power of two.
498 */
499static struct pci_resource *get_io_resource(struct pci_resource **head, u32 size)
500{
501 struct pci_resource *prevnode;
502 struct pci_resource *node;
503 struct pci_resource *split_node = NULL;
504 u32 temp_dword;
505
506 if (!(*head))
507 return NULL;
508
509 if ( pciehp_resource_sort_and_combine(head) )
510 return NULL;
511
512 if ( sort_by_size(head) )
513 return NULL;
514
515 for (node = *head; node; node = node->next) {
516 if (node->length < size)
517 continue;
518
519 if (node->base & (size - 1)) {
520 /* this one isn't base aligned properly
521 so we'll make a new entry and split it up */
522 temp_dword = (node->base | (size-1)) + 1;
523
524 /*/ Short circuit if adjusted size is too small */
525 if ((node->length - (temp_dword - node->base)) < size)
526 continue;
527
528 split_node = kmalloc(sizeof(struct pci_resource),
529 GFP_KERNEL);
530
531 if (!split_node)
532 return NULL;
533
534 split_node->base = node->base;
535 split_node->length = temp_dword - node->base;
536 node->base = temp_dword;
537 node->length -= split_node->length;
538
539 /* Put it in the list */
540 split_node->next = node->next;
541 node->next = split_node;
542 } /* End of non-aligned base */
543
544 /* Don't need to check if too small since we already did */
545 if (node->length > size) {
546 /* this one is longer than we need
547 so we'll make a new entry and split it up */
548 split_node = kmalloc(sizeof(struct pci_resource),
549 GFP_KERNEL);
550
551 if (!split_node)
552 return NULL;
553
554 split_node->base = node->base + size;
555 split_node->length = node->length - size;
556 node->length = size;
557
558 /* Put it in the list */
559 split_node->next = node->next;
560 node->next = split_node;
561 } /* End of too big on top end */
562
563 /* For IO make sure it's not in the ISA aliasing space */
564 if (node->base & 0x300L)
565 continue;
566
567 /* If we got here, then it is the right size
568 Now take it out of the list */
569 if (*head == node) {
570 *head = node->next;
571 } else {
572 prevnode = *head;
573 while (prevnode->next != node)
574 prevnode = prevnode->next;
575
576 prevnode->next = node->next;
577 }
578 node->next = NULL;
579 /* Stop looping */
580 break;
581 }
582
583 return node;
584}
585
586
587/*
588 * get_max_resource
589 *
590 * Gets the largest node that is at least "size" big from the
591 * list pointed to by head. It aligns the node on top and bottom
592 * to "size" alignment before returning it.
593 * J.I. modified to put max size limits of; 64M->32M->16M->8M->4M->1M
594 * This is needed to avoid allocating entire ACPI _CRS res to one child bridge/slot.
595 */
596static struct pci_resource *get_max_resource(struct pci_resource **head, u32 size)
597{
598 struct pci_resource *max;
599 struct pci_resource *temp;
600 struct pci_resource *split_node;
601 u32 temp_dword;
602 u32 max_size[] = { 0x4000000, 0x2000000, 0x1000000, 0x0800000, 0x0400000, 0x0200000, 0x0100000, 0x00 };
603 int i;
604
605 if (!(*head))
606 return NULL;
607
608 if (pciehp_resource_sort_and_combine(head))
609 return NULL;
610
611 if (sort_by_max_size(head))
612 return NULL;
613
614 for (max = *head;max; max = max->next) {
615
616 /* If not big enough we could probably just bail,
617 instead we'll continue to the next. */
618 if (max->length < size)
619 continue;
620
621 if (max->base & (size - 1)) {
622 /* this one isn't base aligned properly
623 so we'll make a new entry and split it up */
624 temp_dword = (max->base | (size-1)) + 1;
625
626 /* Short circuit if adjusted size is too small */
627 if ((max->length - (temp_dword - max->base)) < size)
628 continue;
629
630 split_node = kmalloc(sizeof(struct pci_resource),
631 GFP_KERNEL);
632
633 if (!split_node)
634 return NULL;
635
636 split_node->base = max->base;
637 split_node->length = temp_dword - max->base;
638 max->base = temp_dword;
639 max->length -= split_node->length;
640
641 /* Put it next in the list */
642 split_node->next = max->next;
643 max->next = split_node;
644 }
645
646 if ((max->base + max->length) & (size - 1)) {
647 /* this one isn't end aligned properly at the top
648 so we'll make a new entry and split it up */
649 split_node = kmalloc(sizeof(struct pci_resource),
650 GFP_KERNEL);
651
652 if (!split_node)
653 return NULL;
654 temp_dword = ((max->base + max->length) & ~(size - 1));
655 split_node->base = temp_dword;
656 split_node->length = max->length + max->base
657 - split_node->base;
658 max->length -= split_node->length;
659
660 /* Put it in the list */
661 split_node->next = max->next;
662 max->next = split_node;
663 }
664
665 /* Make sure it didn't shrink too much when we aligned it */
666 if (max->length < size)
667 continue;
668
669 for ( i = 0; max_size[i] > size; i++) {
670 if (max->length > max_size[i]) {
671 split_node = kmalloc(sizeof(struct pci_resource),
672 GFP_KERNEL);
673 if (!split_node)
674 break; /* return NULL; */
675 split_node->base = max->base + max_size[i];
676 split_node->length = max->length - max_size[i];
677 max->length = max_size[i];
678 /* Put it next in the list */
679 split_node->next = max->next;
680 max->next = split_node;
681 break;
682 }
683 }
684
685 /* Now take it out of the list */
686 temp = (struct pci_resource*) *head;
687 if (temp == max) {
688 *head = max->next;
689 } else {
690 while (temp && temp->next != max) {
691 temp = temp->next;
692 }
693
694 temp->next = max->next;
695 }
696
697 max->next = NULL;
698 return max;
699 }
700
701 /* If we get here, we couldn't find one */
702 return NULL;
703}
704
705
706/*
707 * get_resource
708 *
709 * this function sorts the resource list by size and then
710 * returns the first node of "size" length. If it finds a node
711 * larger than "size" it will split it up.
712 *
713 * size must be a power of two.
714 */
715static struct pci_resource *get_resource(struct pci_resource **head, u32 size)
716{
717 struct pci_resource *prevnode;
718 struct pci_resource *node;
719 struct pci_resource *split_node;
720 u32 temp_dword;
721
722 if (!(*head))
723 return NULL;
724
725 if ( pciehp_resource_sort_and_combine(head) )
726 return NULL;
727
728 if ( sort_by_size(head) )
729 return NULL;
730
731 for (node = *head; node; node = node->next) {
732 dbg("%s: req_size =0x%x node=%p, base=0x%x, length=0x%x\n",
733 __FUNCTION__, size, node, node->base, node->length);
734 if (node->length < size)
735 continue;
736
737 if (node->base & (size - 1)) {
738 dbg("%s: not aligned\n", __FUNCTION__);
739 /* this one isn't base aligned properly
740 so we'll make a new entry and split it up */
741 temp_dword = (node->base | (size-1)) + 1;
742
743 /* Short circuit if adjusted size is too small */
744 if ((node->length - (temp_dword - node->base)) < size)
745 continue;
746
747 split_node = kmalloc(sizeof(struct pci_resource),
748 GFP_KERNEL);
749
750 if (!split_node)
751 return NULL;
752
753 split_node->base = node->base;
754 split_node->length = temp_dword - node->base;
755 node->base = temp_dword;
756 node->length -= split_node->length;
757
758 /* Put it in the list */
759 split_node->next = node->next;
760 node->next = split_node;
761 } /* End of non-aligned base */
762
763 /* Don't need to check if too small since we already did */
764 if (node->length > size) {
765 dbg("%s: too big\n", __FUNCTION__);
766 /* this one is longer than we need
767 so we'll make a new entry and split it up */
768 split_node = kmalloc(sizeof(struct pci_resource),
769 GFP_KERNEL);
770
771 if (!split_node)
772 return NULL;
773
774 split_node->base = node->base + size;
775 split_node->length = node->length - size;
776 node->length = size;
777
778 /* Put it in the list */
779 split_node->next = node->next;
780 node->next = split_node;
781 } /* End of too big on top end */
782
783 dbg("%s: got one!!!\n", __FUNCTION__);
784 /* If we got here, then it is the right size
785 Now take it out of the list */
786 if (*head == node) {
787 *head = node->next;
788 } else {
789 prevnode = *head;
790 while (prevnode->next != node)
791 prevnode = prevnode->next;
792
793 prevnode->next = node->next;
794 }
795 node->next = NULL;
796 /* Stop looping */
797 break;
798 }
799 return node;
800}
801
802
803/*
804 * pciehp_resource_sort_and_combine
805 *
806 * Sorts all of the nodes in the list in ascending order by
807 * their base addresses. Also does garbage collection by
808 * combining adjacent nodes.
809 *
810 * returns 0 if success
811 */
812int pciehp_resource_sort_and_combine(struct pci_resource **head)
813{
814 struct pci_resource *node1;
815 struct pci_resource *node2;
816 int out_of_order = 1;
817
818 dbg("%s: head = %p, *head = %p\n", __FUNCTION__, head, *head);
819
820 if (!(*head))
821 return 1;
822
823 dbg("*head->next = %p\n",(*head)->next);
824
825 if (!(*head)->next)
826 return 0; /* only one item on the list, already sorted! */
827
828 dbg("*head->base = 0x%x\n",(*head)->base);
829 dbg("*head->next->base = 0x%x\n",(*head)->next->base);
830 while (out_of_order) {
831 out_of_order = 0;
832
833 /* Special case for swapping list head */
834 if (((*head)->next) &&
835 ((*head)->base > (*head)->next->base)) {
836 node1 = *head;
837 (*head) = (*head)->next;
838 node1->next = (*head)->next;
839 (*head)->next = node1;
840 out_of_order++;
841 }
842
843 node1 = (*head);
844
845 while (node1->next && node1->next->next) {
846 if (node1->next->base > node1->next->next->base) {
847 out_of_order++;
848 node2 = node1->next;
849 node1->next = node1->next->next;
850 node1 = node1->next;
851 node2->next = node1->next;
852 node1->next = node2;
853 } else
854 node1 = node1->next;
855 }
856 } /* End of out_of_order loop */
857
858 node1 = *head;
859
860 while (node1 && node1->next) {
861 if ((node1->base + node1->length) == node1->next->base) {
862 /* Combine */
863 dbg("8..\n");
864 node1->length += node1->next->length;
865 node2 = node1->next;
866 node1->next = node1->next->next;
867 kfree(node2);
868 } else
869 node1 = node1->next;
870 }
871
872 return 0;
873}
874
875
876/**
877 * pciehp_slot_create - Creates a node and adds it to the proper bus.
878 * @busnumber - bus where new node is to be located
879 *
880 * Returns pointer to the new node or NULL if unsuccessful
881 */
882struct pci_func *pciehp_slot_create(u8 busnumber)
883{
884 struct pci_func *new_slot;
885 struct pci_func *next;
886 dbg("%s: busnumber %x\n", __FUNCTION__, busnumber);
887 new_slot = kmalloc(sizeof(struct pci_func), GFP_KERNEL);
888
889 if (new_slot == NULL)
890 return new_slot;
891
892 memset(new_slot, 0, sizeof(struct pci_func));
893
894 new_slot->next = NULL;
895 new_slot->configured = 1;
896
897 if (pciehp_slot_list[busnumber] == NULL) {
898 pciehp_slot_list[busnumber] = new_slot;
899 } else {
900 next = pciehp_slot_list[busnumber];
901 while (next->next != NULL)
902 next = next->next;
903 next->next = new_slot;
904 }
905 return new_slot;
906}
907
908
909/**
910 * slot_remove - Removes a node from the linked list of slots.
911 * @old_slot: slot to remove
912 *
913 * Returns 0 if successful, !0 otherwise.
914 */
915static int slot_remove(struct pci_func * old_slot)
916{
917 struct pci_func *next;
918
919 if (old_slot == NULL)
920 return 1;
921
922 next = pciehp_slot_list[old_slot->bus];
923
924 if (next == NULL)
925 return 1;
926
927 if (next == old_slot) {
928 pciehp_slot_list[old_slot->bus] = old_slot->next;
929 pciehp_destroy_board_resources(old_slot);
930 kfree(old_slot);
931 return 0;
932 }
933
934 while ((next->next != old_slot) && (next->next != NULL)) {
935 next = next->next;
936 }
937
938 if (next->next == old_slot) {
939 next->next = old_slot->next;
940 pciehp_destroy_board_resources(old_slot);
941 kfree(old_slot);
942 return 0;
943 } else
944 return 2;
945}
946
947
948/**
949 * bridge_slot_remove - Removes a node from the linked list of slots.
950 * @bridge: bridge to remove
951 *
952 * Returns 0 if successful, !0 otherwise.
953 */
954static int bridge_slot_remove(struct pci_func *bridge)
955{
956 u8 subordinateBus, secondaryBus;
957 u8 tempBus;
958 struct pci_func *next;
959
960 if (bridge == NULL)
961 return 1;
962
963 secondaryBus = (bridge->config_space[0x06] >> 8) & 0xFF;
964 subordinateBus = (bridge->config_space[0x06] >> 16) & 0xFF;
965
966 for (tempBus = secondaryBus; tempBus <= subordinateBus; tempBus++) {
967 next = pciehp_slot_list[tempBus];
968
969 while (!slot_remove(next)) {
970 next = pciehp_slot_list[tempBus];
971 }
972 }
973
974 next = pciehp_slot_list[bridge->bus];
975
976 if (next == NULL) {
977 return 1;
978 }
979
980 if (next == bridge) {
981 pciehp_slot_list[bridge->bus] = bridge->next;
982 kfree(bridge);
983 return 0;
984 }
985
986 while ((next->next != bridge) && (next->next != NULL)) {
987 next = next->next;
988 }
989
990 if (next->next == bridge) {
991 next->next = bridge->next;
992 kfree(bridge);
993 return 0;
994 } else
995 return 2;
996}
997
998
999/**
1000 * pciehp_slot_find - Looks for a node by bus, and device, multiple functions accessed
1001 * @bus: bus to find
1002 * @device: device to find
1003 * @index: is 0 for first function found, 1 for the second...
1004 *
1005 * Returns pointer to the node if successful, %NULL otherwise.
1006 */
1007struct pci_func *pciehp_slot_find(u8 bus, u8 device, u8 index)
1008{
1009 int found = -1;
1010 struct pci_func *func;
1011
1012 func = pciehp_slot_list[bus];
1013 dbg("%s: bus %x device %x index %x\n",
1014 __FUNCTION__, bus, device, index);
1015 if (func != NULL) {
1016 dbg("%s: func-> bus %x device %x function %x pci_dev %p\n",
1017 __FUNCTION__, func->bus, func->device, func->function,
1018 func->pci_dev);
1019 } else
1020 dbg("%s: func == NULL\n", __FUNCTION__);
1021
1022 if ((func == NULL) || ((func->device == device) && (index == 0)))
1023 return func;
1024
1025 if (func->device == device)
1026 found++;
1027
1028 while (func->next != NULL) {
1029 func = func->next;
1030
1031 dbg("%s: In while loop, func-> bus %x device %x function %x pci_dev %p\n",
1032 __FUNCTION__, func->bus, func->device, func->function,
1033 func->pci_dev);
1034 if (func->device == device)
1035 found++;
1036 dbg("%s: while loop, found %d, index %d\n", __FUNCTION__,
1037 found, index);
1038
1039 if ((found == index) || (func->function == index)) {
1040 dbg("%s: Found bus %x dev %x func %x\n", __FUNCTION__,
1041 func->bus, func->device, func->function);
1042 return func;
1043 }
1044 }
1045
1046 return NULL;
1047}
1048
1049static int is_bridge(struct pci_func * func)
1050{
1051 /* Check the header type */
1052 if (((func->config_space[0x03] >> 16) & 0xFF) == 0x01)
1053 return 1;
1054 else
1055 return 0;
1056}
1057
1058
1059/* The following routines constitute the bulk of the 225/* The following routines constitute the bulk of the
1060 hotplug controller logic 226 hotplug controller logic
1061 */ 227 */
@@ -1100,20 +266,17 @@ static void set_slot_off(struct controller *ctrl, struct slot * pslot)
1100 * Configures board 266 * Configures board
1101 * 267 *
1102 */ 268 */
1103static u32 board_added(struct pci_func * func, struct controller * ctrl) 269static int board_added(struct slot *p_slot)
1104{ 270{
1105 u8 hp_slot; 271 u8 hp_slot;
1106 int index; 272 int rc = 0;
1107 u32 temp_register = 0xFFFFFFFF; 273 struct controller *ctrl = p_slot->ctrl;
1108 u32 rc = 0;
1109 struct pci_func *new_func = NULL;
1110 struct slot *p_slot;
1111 struct resource_lists res_lists;
1112 274
1113 p_slot = pciehp_find_slot(ctrl, func->device); 275 hp_slot = p_slot->device - ctrl->slot_device_offset;
1114 hp_slot = func->device - ctrl->slot_device_offset;
1115 276
1116 dbg("%s: func->device, slot_offset, hp_slot = %d, %d ,%d\n", __FUNCTION__, func->device, ctrl->slot_device_offset, hp_slot); 277 dbg("%s: slot device, slot offset, hp slot = %d, %d ,%d\n",
278 __FUNCTION__, p_slot->device,
279 ctrl->slot_device_offset, hp_slot);
1117 280
1118 /* Wait for exclusive access to hardware */ 281 /* Wait for exclusive access to hardware */
1119 down(&ctrl->crit_sect); 282 down(&ctrl->crit_sect);
@@ -1141,9 +304,7 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
1141 up(&ctrl->crit_sect); 304 up(&ctrl->crit_sect);
1142 305
1143 /* Wait for ~1 second */ 306 /* Wait for ~1 second */
1144 dbg("%s: before long_delay\n", __FUNCTION__);
1145 wait_for_ctrl_irq (ctrl); 307 wait_for_ctrl_irq (ctrl);
1146 dbg("%s: afterlong_delay\n", __FUNCTION__);
1147 308
1148 /* Check link training status */ 309 /* Check link training status */
1149 rc = p_slot->hpc_ops->check_lnk_status(ctrl); 310 rc = p_slot->hpc_ops->check_lnk_status(ctrl);
@@ -1153,98 +314,42 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
1153 return rc; 314 return rc;
1154 } 315 }
1155 316
1156 dbg("%s: func status = %x\n", __FUNCTION__, func->status);
1157
1158 /* Check for a power fault */ 317 /* Check for a power fault */
1159 if (func->status == 0xFF) { 318 if (p_slot->hpc_ops->query_power_fault(p_slot)) {
1160 /* power fault occurred, but it was benign */ 319 dbg("%s: power fault detected\n", __FUNCTION__);
1161 temp_register = 0xFFFFFFFF;
1162 dbg("%s: temp register set to %x by power fault\n", __FUNCTION__, temp_register);
1163 rc = POWER_FAILURE; 320 rc = POWER_FAILURE;
1164 func->status = 0; 321 goto err_exit;
1165 } else {
1166 /* Get vendor/device ID u32 */
1167 rc = pci_bus_read_config_dword (ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function),
1168 PCI_VENDOR_ID, &temp_register);
1169 dbg("%s: pci_bus_read_config_dword returns %d\n", __FUNCTION__, rc);
1170 dbg("%s: temp_register is %x\n", __FUNCTION__, temp_register);
1171
1172 if (rc != 0) {
1173 /* Something's wrong here */
1174 temp_register = 0xFFFFFFFF;
1175 dbg("%s: temp register set to %x by error\n", __FUNCTION__, temp_register);
1176 }
1177 /* Preset return code. It will be changed later if things go okay. */
1178 rc = NO_ADAPTER_PRESENT;
1179 } 322 }
1180 323
1181 /* All F's is an empty slot or an invalid board */ 324 rc = pciehp_configure_device(p_slot);
1182 if (temp_register != 0xFFFFFFFF) { /* Check for a board in the slot */ 325 if (rc) {
1183 res_lists.io_head = ctrl->io_head; 326 err("Cannot add device 0x%x:%x\n", p_slot->bus,
1184 res_lists.mem_head = ctrl->mem_head; 327 p_slot->device);
1185 res_lists.p_mem_head = ctrl->p_mem_head; 328 goto err_exit;
1186 res_lists.bus_head = ctrl->bus_head; 329 }
1187 res_lists.irqs = NULL;
1188
1189 rc = configure_new_device(ctrl, func, 0, &res_lists, 0, 0);
1190 dbg("%s: back from configure_new_device\n", __FUNCTION__);
1191
1192 ctrl->io_head = res_lists.io_head;
1193 ctrl->mem_head = res_lists.mem_head;
1194 ctrl->p_mem_head = res_lists.p_mem_head;
1195 ctrl->bus_head = res_lists.bus_head;
1196
1197 pciehp_resource_sort_and_combine(&(ctrl->mem_head));
1198 pciehp_resource_sort_and_combine(&(ctrl->p_mem_head));
1199 pciehp_resource_sort_and_combine(&(ctrl->io_head));
1200 pciehp_resource_sort_and_combine(&(ctrl->bus_head));
1201
1202 if (rc) {
1203 set_slot_off(ctrl, p_slot);
1204 return rc;
1205 }
1206 pciehp_save_slot_config(ctrl, func);
1207 330
1208 func->status = 0; 331 /*
1209 func->switch_save = 0x10; 332 * Some PCI Express root ports require fixup after hot-plug operation.
1210 func->is_a_board = 0x01; 333 */
334 if (pcie_mch_quirk)
335 pci_fixup_device(pci_fixup_final, ctrl->pci_dev);
336 if (PWR_LED(ctrl->ctrlcap)) {
337 /* Wait for exclusive access to hardware */
338 down(&ctrl->crit_sect);
1211 339
1212 /* next, we will instantiate the linux pci_dev structures 340 p_slot->hpc_ops->green_led_on(p_slot);
1213 * (with appropriate driver notification, if already present)
1214 */
1215 index = 0;
1216 do {
1217 new_func = pciehp_slot_find(ctrl->slot_bus, func->device, index++);
1218 if (new_func && !new_func->pci_dev) {
1219 dbg("%s:call pci_hp_configure_dev, func %x\n",
1220 __FUNCTION__, index);
1221 pciehp_configure_device(ctrl, new_func);
1222 }
1223 } while (new_func);
1224
1225 /*
1226 * Some PCI Express root ports require fixup after hot-plug operation.
1227 */
1228 if (pcie_mch_quirk)
1229 pci_fixup_device(pci_fixup_final, ctrl->pci_dev);
1230
1231 if (PWR_LED(ctrl->ctrlcap)) {
1232 /* Wait for exclusive access to hardware */
1233 down(&ctrl->crit_sect);
1234
1235 p_slot->hpc_ops->green_led_on(p_slot);
1236 341
1237 /* Wait for the command to complete */ 342 /* Wait for the command to complete */
1238 wait_for_ctrl_irq (ctrl); 343 wait_for_ctrl_irq (ctrl);
1239 344
1240 /* Done with exclusive hardware access */ 345 /* Done with exclusive hardware access */
1241 up(&ctrl->crit_sect); 346 up(&ctrl->crit_sect);
1242 } 347 }
1243 } else {
1244 set_slot_off(ctrl, p_slot);
1245 return -1;
1246 }
1247 return 0; 348 return 0;
349
350err_exit:
351 set_slot_off(ctrl, p_slot);
352 return -1;
1248} 353}
1249 354
1250 355
@@ -1252,56 +357,23 @@ static u32 board_added(struct pci_func * func, struct controller * ctrl)
1252 * remove_board - Turns off slot and LED's 357 * remove_board - Turns off slot and LED's
1253 * 358 *
1254 */ 359 */
1255static u32 remove_board(struct pci_func *func, struct controller *ctrl) 360static int remove_board(struct slot *p_slot)
1256{ 361{
1257 int index;
1258 u8 skip = 0;
1259 u8 device; 362 u8 device;
1260 u8 hp_slot; 363 u8 hp_slot;
1261 u32 rc; 364 int rc;
1262 struct resource_lists res_lists; 365 struct controller *ctrl = p_slot->ctrl;
1263 struct pci_func *temp_func;
1264 struct slot *p_slot;
1265
1266 if (func == NULL)
1267 return 1;
1268 366
1269 if (pciehp_unconfigure_device(func)) 367 if (pciehp_unconfigure_device(p_slot))
1270 return 1; 368 return 1;
1271 369
1272 device = func->device; 370 device = p_slot->device;
1273 371
1274 hp_slot = func->device - ctrl->slot_device_offset; 372 hp_slot = p_slot->device - ctrl->slot_device_offset;
1275 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 373 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
1276 374
1277 dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot); 375 dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot);
1278 376
1279 if ((ctrl->add_support) &&
1280 !(func->bus_head || func->mem_head || func->p_mem_head || func->io_head)) {
1281 /* Here we check to see if we've saved any of the board's
1282 * resources already. If so, we'll skip the attempt to
1283 * determine what's being used.
1284 */
1285 index = 0;
1286
1287 temp_func = func;
1288
1289 while ((temp_func = pciehp_slot_find(temp_func->bus, temp_func->device, index++))) {
1290 if (temp_func->bus_head || temp_func->mem_head
1291 || temp_func->p_mem_head || temp_func->io_head) {
1292 skip = 1;
1293 break;
1294 }
1295 }
1296
1297 if (!skip)
1298 rc = pciehp_save_used_resources(ctrl, func, DISABLE_CARD);
1299 }
1300 /* Change status to shutdown */
1301 if (func->is_a_board)
1302 func->status = 0x01;
1303 func->configured = 0;
1304
1305 /* Wait for exclusive access to hardware */ 377 /* Wait for exclusive access to hardware */
1306 down(&ctrl->crit_sect); 378 down(&ctrl->crit_sect);
1307 379
@@ -1328,56 +400,6 @@ static u32 remove_board(struct pci_func *func, struct controller *ctrl)
1328 /* Done with exclusive hardware access */ 400 /* Done with exclusive hardware access */
1329 up(&ctrl->crit_sect); 401 up(&ctrl->crit_sect);
1330 402
1331 if (ctrl->add_support) {
1332 while (func) {
1333 res_lists.io_head = ctrl->io_head;
1334 res_lists.mem_head = ctrl->mem_head;
1335 res_lists.p_mem_head = ctrl->p_mem_head;
1336 res_lists.bus_head = ctrl->bus_head;
1337
1338 dbg("Returning resources to ctlr lists for (B/D/F) = (%#x/%#x/%#x)\n",
1339 func->bus, func->device, func->function);
1340
1341 pciehp_return_board_resources(func, &res_lists);
1342
1343 ctrl->io_head = res_lists.io_head;
1344 ctrl->mem_head = res_lists.mem_head;
1345 ctrl->p_mem_head = res_lists.p_mem_head;
1346 ctrl->bus_head = res_lists.bus_head;
1347
1348 pciehp_resource_sort_and_combine(&(ctrl->mem_head));
1349 pciehp_resource_sort_and_combine(&(ctrl->p_mem_head));
1350 pciehp_resource_sort_and_combine(&(ctrl->io_head));
1351 pciehp_resource_sort_and_combine(&(ctrl->bus_head));
1352
1353 if (is_bridge(func)) {
1354 dbg("PCI Bridge Hot-Remove s:b:d:f(%02x:%02x:%02x:%02x)\n",
1355 ctrl->seg, func->bus, func->device, func->function);
1356 bridge_slot_remove(func);
1357 } else {
1358 dbg("PCI Function Hot-Remove s:b:d:f(%02x:%02x:%02x:%02x)\n",
1359 ctrl->seg, func->bus, func->device, func->function);
1360 slot_remove(func);
1361 }
1362
1363 func = pciehp_slot_find(ctrl->slot_bus, device, 0);
1364 }
1365
1366 /* Setup slot structure with entry for empty slot */
1367 func = pciehp_slot_create(ctrl->slot_bus);
1368
1369 if (func == NULL) {
1370 return 1;
1371 }
1372
1373 func->bus = ctrl->slot_bus;
1374 func->device = device;
1375 func->function = 0;
1376 func->configured = 0;
1377 func->switch_save = 0x10;
1378 func->is_a_board = 0;
1379 }
1380
1381 return 0; 403 return 0;
1382} 404}
1383 405
@@ -1411,13 +433,15 @@ static void pciehp_pushbutton_thread(unsigned long slot)
1411 p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 433 p_slot->hpc_ops->get_power_status(p_slot, &getstatus);
1412 if (getstatus) { 434 if (getstatus) {
1413 p_slot->state = POWEROFF_STATE; 435 p_slot->state = POWEROFF_STATE;
1414 dbg("In power_down_board, b:d(%x:%x)\n", p_slot->bus, p_slot->device); 436 dbg("%s: disabling bus:device(%x:%x)\n", __FUNCTION__,
437 p_slot->bus, p_slot->device);
1415 438
1416 pciehp_disable_slot(p_slot); 439 pciehp_disable_slot(p_slot);
1417 p_slot->state = STATIC_STATE; 440 p_slot->state = STATIC_STATE;
1418 } else { 441 } else {
1419 p_slot->state = POWERON_STATE; 442 p_slot->state = POWERON_STATE;
1420 dbg("In add_board, b:d(%x:%x)\n", p_slot->bus, p_slot->device); 443 dbg("%s: adding bus:device(%x:%x)\n", __FUNCTION__,
444 p_slot->bus, p_slot->device);
1421 445
1422 if (pciehp_enable_slot(p_slot) && PWR_LED(p_slot->ctrl->ctrlcap)) { 446 if (pciehp_enable_slot(p_slot) && PWR_LED(p_slot->ctrl->ctrlcap)) {
1423 /* Wait for exclusive access to hardware */ 447 /* Wait for exclusive access to hardware */
@@ -1459,13 +483,15 @@ static void pciehp_surprise_rm_thread(unsigned long slot)
1459 p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus); 483 p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus);
1460 if (!getstatus) { 484 if (!getstatus) {
1461 p_slot->state = POWEROFF_STATE; 485 p_slot->state = POWEROFF_STATE;
1462 dbg("In removing board, b:d(%x:%x)\n", p_slot->bus, p_slot->device); 486 dbg("%s: removing bus:device(%x:%x)\n",
487 __FUNCTION__, p_slot->bus, p_slot->device);
1463 488
1464 pciehp_disable_slot(p_slot); 489 pciehp_disable_slot(p_slot);
1465 p_slot->state = STATIC_STATE; 490 p_slot->state = STATIC_STATE;
1466 } else { 491 } else {
1467 p_slot->state = POWERON_STATE; 492 p_slot->state = POWERON_STATE;
1468 dbg("In add_board, b:d(%x:%x)\n", p_slot->bus, p_slot->device); 493 dbg("%s: adding bus:device(%x:%x)\n",
494 __FUNCTION__, p_slot->bus, p_slot->device);
1469 495
1470 if (pciehp_enable_slot(p_slot) && PWR_LED(p_slot->ctrl->ctrlcap)) { 496 if (pciehp_enable_slot(p_slot) && PWR_LED(p_slot->ctrl->ctrlcap)) {
1471 /* Wait for exclusive access to hardware */ 497 /* Wait for exclusive access to hardware */
@@ -1531,7 +557,6 @@ int pciehp_event_start_thread(void)
1531 err ("Can't start up our event thread\n"); 557 err ("Can't start up our event thread\n");
1532 return -1; 558 return -1;
1533 } 559 }
1534 dbg("Our event thread pid = %d\n", pid);
1535 return 0; 560 return 0;
1536} 561}
1537 562
@@ -1539,9 +564,7 @@ int pciehp_event_start_thread(void)
1539void pciehp_event_stop_thread(void) 564void pciehp_event_stop_thread(void)
1540{ 565{
1541 event_finished = 1; 566 event_finished = 1;
1542 dbg("event_thread finish command given\n");
1543 up(&event_semaphore); 567 up(&event_semaphore);
1544 dbg("wait for event_thread to exit\n");
1545 down(&event_exit); 568 down(&event_exit);
1546} 569}
1547 570
@@ -1573,7 +596,6 @@ static void interrupt_event_handler(struct controller *ctrl)
1573{ 596{
1574 int loop = 0; 597 int loop = 0;
1575 int change = 1; 598 int change = 1;
1576 struct pci_func *func;
1577 u8 hp_slot; 599 u8 hp_slot;
1578 u8 getstatus; 600 u8 getstatus;
1579 struct slot *p_slot; 601 struct slot *p_slot;
@@ -1581,16 +603,12 @@ static void interrupt_event_handler(struct controller *ctrl)
1581 while (change) { 603 while (change) {
1582 change = 0; 604 change = 0;
1583 605
1584 for (loop = 0; loop < 10; loop++) { 606 for (loop = 0; loop < MAX_EVENTS; loop++) {
1585 if (ctrl->event_queue[loop].event_type != 0) { 607 if (ctrl->event_queue[loop].event_type != 0) {
1586 hp_slot = ctrl->event_queue[loop].hp_slot; 608 hp_slot = ctrl->event_queue[loop].hp_slot;
1587 609
1588 func = pciehp_slot_find(ctrl->slot_bus, (hp_slot + ctrl->slot_device_offset), 0);
1589
1590 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); 610 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
1591 611
1592 dbg("hp_slot %d, func %p, p_slot %p\n", hp_slot, func, p_slot);
1593
1594 if (ctrl->event_queue[loop].event_type == INT_BUTTON_CANCEL) { 612 if (ctrl->event_queue[loop].event_type == INT_BUTTON_CANCEL) {
1595 dbg("button cancel\n"); 613 dbg("button cancel\n");
1596 del_timer(&p_slot->task_event); 614 del_timer(&p_slot->task_event);
@@ -1682,7 +700,6 @@ static void interrupt_event_handler(struct controller *ctrl)
1682 p_slot->task_event.function = (void (*)(unsigned long)) pushbutton_helper_thread; 700 p_slot->task_event.function = (void (*)(unsigned long)) pushbutton_helper_thread;
1683 p_slot->task_event.data = (unsigned long) p_slot; 701 p_slot->task_event.data = (unsigned long) p_slot;
1684 702
1685 dbg("add_timer p_slot = %p\n", (void *) p_slot);
1686 add_timer(&p_slot->task_event); 703 add_timer(&p_slot->task_event);
1687 } 704 }
1688 } 705 }
@@ -1737,13 +754,6 @@ int pciehp_enable_slot(struct slot *p_slot)
1737{ 754{
1738 u8 getstatus = 0; 755 u8 getstatus = 0;
1739 int rc; 756 int rc;
1740 struct pci_func *func;
1741
1742 func = pciehp_slot_find(p_slot->bus, p_slot->device, 0);
1743 if (!func) {
1744 dbg("%s: Error! slot NULL\n", __FUNCTION__);
1745 return 1;
1746 }
1747 757
1748 /* Check to see if (latch closed, card present, power off) */ 758 /* Check to see if (latch closed, card present, power off) */
1749 down(&p_slot->ctrl->crit_sect); 759 down(&p_slot->ctrl->crit_sect);
@@ -1773,45 +783,11 @@ int pciehp_enable_slot(struct slot *p_slot)
1773 } 783 }
1774 up(&p_slot->ctrl->crit_sect); 784 up(&p_slot->ctrl->crit_sect);
1775 785
1776 slot_remove(func);
1777
1778 func = pciehp_slot_create(p_slot->bus);
1779 if (func == NULL)
1780 return 1;
1781
1782 func->bus = p_slot->bus;
1783 func->device = p_slot->device;
1784 func->function = 0;
1785 func->configured = 0;
1786 func->is_a_board = 1;
1787
1788 /* We have to save the presence info for these slots */
1789 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
1790 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 786 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
1791 func->switch_save = !getstatus? 0x10:0;
1792 787
1793 rc = board_added(func, p_slot->ctrl); 788 rc = board_added(p_slot);
1794 if (rc) { 789 if (rc) {
1795 if (is_bridge(func))
1796 bridge_slot_remove(func);
1797 else
1798 slot_remove(func);
1799
1800 /* Setup slot structure with entry for empty slot */
1801 func = pciehp_slot_create(p_slot->bus);
1802 if (func == NULL)
1803 return 1; /* Out of memory */
1804
1805 func->bus = p_slot->bus;
1806 func->device = p_slot->device;
1807 func->function = 0;
1808 func->configured = 0;
1809 func->is_a_board = 1;
1810
1811 /* We have to save the presence info for these slots */
1812 p_slot->hpc_ops->get_adapter_status(p_slot, &(func->presence_save));
1813 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 790 p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
1814 func->switch_save = !getstatus? 0x10:0;
1815 } 791 }
1816 792
1817 if (p_slot) 793 if (p_slot)
@@ -1823,14 +799,8 @@ int pciehp_enable_slot(struct slot *p_slot)
1823 799
1824int pciehp_disable_slot(struct slot *p_slot) 800int pciehp_disable_slot(struct slot *p_slot)
1825{ 801{
1826 u8 class_code, header_type, BCR;
1827 u8 index = 0;
1828 u8 getstatus = 0; 802 u8 getstatus = 0;
1829 u32 rc = 0;
1830 int ret = 0; 803 int ret = 0;
1831 unsigned int devfn;
1832 struct pci_bus *pci_bus = p_slot->ctrl->pci_dev->subordinate;
1833 struct pci_func *func;
1834 804
1835 if (!p_slot->ctrl) 805 if (!p_slot->ctrl)
1836 return 1; 806 return 1;
@@ -1867,838 +837,8 @@ int pciehp_disable_slot(struct slot *p_slot)
1867 837
1868 up(&p_slot->ctrl->crit_sect); 838 up(&p_slot->ctrl->crit_sect);
1869 839
1870 func = pciehp_slot_find(p_slot->bus, p_slot->device, index++); 840 ret = remove_board(p_slot);
1871 841 update_slot_info(p_slot);
1872 /* Make sure there are no video controllers here 842 return ret;
1873 * for all func of p_slot
1874 */
1875 while (func && !rc) {
1876 pci_bus->number = func->bus;
1877 devfn = PCI_DEVFN(func->device, func->function);
1878
1879 /* Check the Class Code */
1880 rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
1881 if (rc)
1882 return rc;
1883
1884 if (class_code == PCI_BASE_CLASS_DISPLAY) {
1885 /* Display/Video adapter (not supported) */
1886 rc = REMOVE_NOT_SUPPORTED;
1887 } else {
1888 /* See if it's a bridge */
1889 rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1890 if (rc)
1891 return rc;
1892
1893 /* If it's a bridge, check the VGA Enable bit */
1894 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1895 rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_BRIDGE_CONTROL, &BCR);
1896 if (rc)
1897 return rc;
1898
1899 /* If the VGA Enable bit is set, remove isn't supported */
1900 if (BCR & PCI_BRIDGE_CTL_VGA) {
1901 rc = REMOVE_NOT_SUPPORTED;
1902 }
1903 }
1904 }
1905
1906 func = pciehp_slot_find(p_slot->bus, p_slot->device, index++);
1907 }
1908
1909 func = pciehp_slot_find(p_slot->bus, p_slot->device, 0);
1910 if ((func != NULL) && !rc) {
1911 rc = remove_board(func, p_slot->ctrl);
1912 } else if (!rc)
1913 rc = 1;
1914
1915 if (p_slot)
1916 update_slot_info(p_slot);
1917
1918 return rc;
1919}
1920
1921
1922/**
1923 * configure_new_device - Configures the PCI header information of one board.
1924 *
1925 * @ctrl: pointer to controller structure
1926 * @func: pointer to function structure
1927 * @behind_bridge: 1 if this is a recursive call, 0 if not
1928 * @resources: pointer to set of resource lists
1929 *
1930 * Returns 0 if success
1931 *
1932 */
1933static u32 configure_new_device(struct controller * ctrl, struct pci_func * func,
1934 u8 behind_bridge, struct resource_lists * resources, u8 bridge_bus, u8 bridge_dev)
1935{
1936 u8 temp_byte, function, max_functions, stop_it;
1937 int rc;
1938 u32 ID;
1939 struct pci_func *new_slot;
1940 struct pci_bus lpci_bus, *pci_bus;
1941 int index;
1942
1943 new_slot = func;
1944
1945 dbg("%s\n", __FUNCTION__);
1946 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
1947 pci_bus = &lpci_bus;
1948 pci_bus->number = func->bus;
1949
1950 /* Check for Multi-function device */
1951 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
1952 if (rc) {
1953 dbg("%s: rc = %d\n", __FUNCTION__, rc);
1954 return rc;
1955 }
1956
1957 if (temp_byte & 0x80) /* Multi-function device */
1958 max_functions = 8;
1959 else
1960 max_functions = 1;
1961
1962 function = 0;
1963
1964 do {
1965 rc = configure_new_function(ctrl, new_slot, behind_bridge,
1966 resources, bridge_bus, bridge_dev);
1967
1968 if (rc) {
1969 dbg("configure_new_function failed: %d\n", rc);
1970 index = 0;
1971
1972 while (new_slot) {
1973 new_slot = pciehp_slot_find(new_slot->bus,
1974 new_slot->device, index++);
1975
1976 if (new_slot)
1977 pciehp_return_board_resources(new_slot,
1978 resources);
1979 }
1980
1981 return rc;
1982 }
1983
1984 function++;
1985
1986 stop_it = 0;
1987
1988 /* The following loop skips to the next present function
1989 * and creates a board structure
1990 */
1991
1992 while ((function < max_functions) && (!stop_it)) {
1993 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(func->device, function), 0x00, &ID);
1994
1995 if (ID == 0xFFFFFFFF) { /* There's nothing there. */
1996 function++;
1997 } else { /* There's something there */
1998 /* Setup slot structure. */
1999 new_slot = pciehp_slot_create(func->bus);
2000
2001 if (new_slot == NULL) {
2002 /* Out of memory */
2003 return 1;
2004 }
2005
2006 new_slot->bus = func->bus;
2007 new_slot->device = func->device;
2008 new_slot->function = function;
2009 new_slot->is_a_board = 1;
2010 new_slot->status = 0;
2011
2012 stop_it++;
2013 }
2014 }
2015
2016 } while (function < max_functions);
2017 dbg("returning from %s\n", __FUNCTION__);
2018
2019 return 0;
2020}
2021
2022/*
2023 * Configuration logic that involves the hotplug data structures and
2024 * their bookkeeping
2025 */
2026
2027/**
2028 * configure_bridge: fill bridge's registers, either configure or disable it.
2029 */
2030static int
2031configure_bridge(struct pci_bus *pci_bus, unsigned int devfn,
2032 struct pci_resource *mem_node,
2033 struct pci_resource **hold_mem_node,
2034 int base_addr, int limit_addr)
2035{
2036 u16 temp_word;
2037 u32 rc;
2038
2039 if (mem_node) {
2040 memcpy(*hold_mem_node, mem_node, sizeof(struct pci_resource));
2041 mem_node->next = NULL;
2042
2043 /* set Mem base and Limit registers */
2044 RES_CHECK(mem_node->base, 16);
2045 temp_word = (u16)(mem_node->base >> 16);
2046 rc = pci_bus_write_config_word(pci_bus, devfn, base_addr, temp_word);
2047
2048 RES_CHECK(mem_node->base + mem_node->length - 1, 16);
2049 temp_word = (u16)((mem_node->base + mem_node->length - 1) >> 16);
2050 rc = pci_bus_write_config_word(pci_bus, devfn, limit_addr, temp_word);
2051 } else {
2052 temp_word = 0xFFFF;
2053 rc = pci_bus_write_config_word(pci_bus, devfn, base_addr, temp_word);
2054
2055 temp_word = 0x0000;
2056 rc = pci_bus_write_config_word(pci_bus, devfn, limit_addr, temp_word);
2057
2058 kfree(*hold_mem_node);
2059 *hold_mem_node = NULL;
2060 }
2061 return rc;
2062}
2063
2064static int
2065configure_new_bridge(struct controller *ctrl, struct pci_func *func,
2066 u8 behind_bridge, struct resource_lists *resources,
2067 struct pci_bus *pci_bus)
2068{
2069 int cloop;
2070 u8 temp_byte;
2071 u8 device;
2072 u16 temp_word;
2073 u32 rc;
2074 u32 ID;
2075 unsigned int devfn;
2076 struct pci_resource *mem_node;
2077 struct pci_resource *p_mem_node;
2078 struct pci_resource *io_node;
2079 struct pci_resource *bus_node;
2080 struct pci_resource *hold_mem_node;
2081 struct pci_resource *hold_p_mem_node;
2082 struct pci_resource *hold_IO_node;
2083 struct pci_resource *hold_bus_node;
2084 struct irq_mapping irqs;
2085 struct pci_func *new_slot;
2086 struct resource_lists temp_resources;
2087
2088 devfn = PCI_DEVFN(func->device, func->function);
2089
2090 /* set Primary bus */
2091 dbg("set Primary bus = 0x%x\n", func->bus);
2092 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_PRIMARY_BUS, func->bus);
2093 if (rc)
2094 return rc;
2095
2096 /* find range of busses to use */
2097 bus_node = get_max_resource(&resources->bus_head, 1L);
2098
2099 /* If we don't have any busses to allocate, we can't continue */
2100 if (!bus_node) {
2101 err("Got NO bus resource to use\n");
2102 return -ENOMEM;
2103 }
2104 dbg("Got ranges of buses to use: base:len=0x%x:%x\n", bus_node->base, bus_node->length);
2105
2106 /* set Secondary bus */
2107 temp_byte = (u8)bus_node->base;
2108 dbg("set Secondary bus = 0x%x\n", temp_byte);
2109 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, temp_byte);
2110 if (rc)
2111 return rc;
2112
2113 /* set subordinate bus */
2114 temp_byte = (u8)(bus_node->base + bus_node->length - 1);
2115 dbg("set subordinate bus = 0x%x\n", temp_byte);
2116 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2117 if (rc)
2118 return rc;
2119
2120 /* Set HP parameters (Cache Line Size, Latency Timer) */
2121 rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_BRIDGE);
2122 if (rc)
2123 return rc;
2124
2125 /* Setup the IO, memory, and prefetchable windows */
2126
2127 io_node = get_max_resource(&(resources->io_head), 0x1000L);
2128 if (io_node) {
2129 dbg("io_node(base, len, next) (%x, %x, %p)\n", io_node->base,
2130 io_node->length, io_node->next);
2131 }
2132
2133 mem_node = get_max_resource(&(resources->mem_head), 0x100000L);
2134 if (mem_node) {
2135 dbg("mem_node(base, len, next) (%x, %x, %p)\n", mem_node->base,
2136 mem_node->length, mem_node->next);
2137 }
2138
2139 if (resources->p_mem_head)
2140 p_mem_node = get_max_resource(&(resources->p_mem_head), 0x100000L);
2141 else {
2142 /*
2143 * In some platform implementation, MEM and PMEM are not
2144 * distinguished, and hence ACPI _CRS has only MEM entries
2145 * for both MEM and PMEM.
2146 */
2147 dbg("using MEM for PMEM\n");
2148 p_mem_node = get_max_resource(&(resources->mem_head), 0x100000L);
2149 }
2150 if (p_mem_node) {
2151 dbg("p_mem_node(base, len, next) (%x, %x, %p)\n", p_mem_node->base,
2152 p_mem_node->length, p_mem_node->next);
2153 }
2154
2155 /* set up the IRQ info */
2156 if (!resources->irqs) {
2157 irqs.barber_pole = 0;
2158 irqs.interrupt[0] = 0;
2159 irqs.interrupt[1] = 0;
2160 irqs.interrupt[2] = 0;
2161 irqs.interrupt[3] = 0;
2162 irqs.valid_INT = 0;
2163 } else {
2164 irqs.barber_pole = resources->irqs->barber_pole;
2165 irqs.interrupt[0] = resources->irqs->interrupt[0];
2166 irqs.interrupt[1] = resources->irqs->interrupt[1];
2167 irqs.interrupt[2] = resources->irqs->interrupt[2];
2168 irqs.interrupt[3] = resources->irqs->interrupt[3];
2169 irqs.valid_INT = resources->irqs->valid_INT;
2170 }
2171
2172 /* set up resource lists that are now aligned on top and bottom
2173 * for anything behind the bridge.
2174 */
2175 temp_resources.bus_head = bus_node;
2176 temp_resources.io_head = io_node;
2177 temp_resources.mem_head = mem_node;
2178 temp_resources.p_mem_head = p_mem_node;
2179 temp_resources.irqs = &irqs;
2180
2181 /* Make copies of the nodes we are going to pass down so that
2182 * if there is a problem,we can just use these to free resources
2183 */
2184 hold_bus_node = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
2185 hold_IO_node = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
2186 hold_mem_node = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
2187 hold_p_mem_node = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
2188
2189 if (!hold_bus_node || !hold_IO_node || !hold_mem_node || !hold_p_mem_node) {
2190 kfree(hold_bus_node);
2191 kfree(hold_IO_node);
2192 kfree(hold_mem_node);
2193 kfree(hold_p_mem_node);
2194
2195 return 1;
2196 }
2197
2198 memcpy(hold_bus_node, bus_node, sizeof(struct pci_resource));
2199
2200 bus_node->base += 1;
2201 bus_node->length -= 1;
2202 bus_node->next = NULL;
2203
2204 /* If we have IO resources copy them and fill in the bridge's
2205 * IO range registers
2206 */
2207 if (io_node) {
2208 memcpy(hold_IO_node, io_node, sizeof(struct pci_resource));
2209 io_node->next = NULL;
2210
2211 /* set IO base and Limit registers */
2212 RES_CHECK(io_node->base, 8);
2213 temp_byte = (u8)(io_node->base >> 8);
2214 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_BASE, temp_byte);
2215
2216 RES_CHECK(io_node->base + io_node->length - 1, 8);
2217 temp_byte = (u8)((io_node->base + io_node->length - 1) >> 8);
2218 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2219 } else {
2220 kfree(hold_IO_node);
2221 hold_IO_node = NULL;
2222 }
2223
2224 /* If we have memory resources copy them and fill in the bridge's
2225 * memory range registers. Otherwise, fill in the range
2226 * registers with values that disable them.
2227 */
2228 rc = configure_bridge(pci_bus, devfn, mem_node, &hold_mem_node,
2229 PCI_MEMORY_BASE, PCI_MEMORY_LIMIT);
2230
2231 /* If we have prefetchable memory resources copy them and
2232 * fill in the bridge's memory range registers. Otherwise,
2233 * fill in the range registers with values that disable them.
2234 */
2235 rc = configure_bridge(pci_bus, devfn, p_mem_node, &hold_p_mem_node,
2236 PCI_PREF_MEMORY_BASE, PCI_PREF_MEMORY_LIMIT);
2237
2238 /* Adjust this to compensate for extra adjustment in first loop */
2239 irqs.barber_pole--;
2240
2241 rc = 0;
2242
2243 /* Here we actually find the devices and configure them */
2244 for (device = 0; (device <= 0x1F) && !rc; device++) {
2245 irqs.barber_pole = (irqs.barber_pole + 1) & 0x03;
2246
2247 ID = 0xFFFFFFFF;
2248 pci_bus->number = hold_bus_node->base;
2249 pci_bus_read_config_dword (pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
2250 pci_bus->number = func->bus;
2251
2252 if (ID != 0xFFFFFFFF) { /* device Present */
2253 /* Setup slot structure. */
2254 new_slot = pciehp_slot_create(hold_bus_node->base);
2255
2256 if (new_slot == NULL) {
2257 /* Out of memory */
2258 rc = -ENOMEM;
2259 continue;
2260 }
2261
2262 new_slot->bus = hold_bus_node->base;
2263 new_slot->device = device;
2264 new_slot->function = 0;
2265 new_slot->is_a_board = 1;
2266 new_slot->status = 0;
2267
2268 rc = configure_new_device(ctrl, new_slot, 1,
2269 &temp_resources, func->bus,
2270 func->device);
2271 dbg("configure_new_device rc=0x%x\n",rc);
2272 } /* End of IF (device in slot?) */
2273 } /* End of FOR loop */
2274
2275 if (rc) {
2276 pciehp_destroy_resource_list(&temp_resources);
2277
2278 return_resource(&(resources->bus_head), hold_bus_node);
2279 return_resource(&(resources->io_head), hold_IO_node);
2280 return_resource(&(resources->mem_head), hold_mem_node);
2281 return_resource(&(resources->p_mem_head), hold_p_mem_node);
2282 return(rc);
2283 }
2284
2285 /* save the interrupt routing information */
2286 if (resources->irqs) {
2287 resources->irqs->interrupt[0] = irqs.interrupt[0];
2288 resources->irqs->interrupt[1] = irqs.interrupt[1];
2289 resources->irqs->interrupt[2] = irqs.interrupt[2];
2290 resources->irqs->interrupt[3] = irqs.interrupt[3];
2291 resources->irqs->valid_INT = irqs.valid_INT;
2292 } else if (!behind_bridge) {
2293 /* We need to hook up the interrupts here */
2294 for (cloop = 0; cloop < 4; cloop++) {
2295 if (irqs.valid_INT & (0x01 << cloop)) {
2296 rc = pciehp_set_irq(func->bus, func->device,
2297 0x0A + cloop, irqs.interrupt[cloop]);
2298 if (rc) {
2299 pciehp_destroy_resource_list (&temp_resources);
2300 return_resource(&(resources->bus_head), hold_bus_node);
2301 return_resource(&(resources->io_head), hold_IO_node);
2302 return_resource(&(resources->mem_head), hold_mem_node);
2303 return_resource(&(resources->p_mem_head), hold_p_mem_node);
2304 return rc;
2305 }
2306 }
2307 } /* end of for loop */
2308 }
2309
2310 /* Return unused bus resources
2311 * First use the temporary node to store information for the board
2312 */
2313 if (hold_bus_node && bus_node && temp_resources.bus_head) {
2314 hold_bus_node->length = bus_node->base - hold_bus_node->base;
2315
2316 hold_bus_node->next = func->bus_head;
2317 func->bus_head = hold_bus_node;
2318
2319 temp_byte = (u8)(temp_resources.bus_head->base - 1);
2320
2321 /* set subordinate bus */
2322 dbg("re-set subordinate bus = 0x%x\n", temp_byte);
2323 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2324
2325 if (temp_resources.bus_head->length == 0) {
2326 kfree(temp_resources.bus_head);
2327 temp_resources.bus_head = NULL;
2328 } else {
2329 dbg("return bus res of b:d(0x%x:%x) base:len(0x%x:%x)\n",
2330 func->bus, func->device, temp_resources.bus_head->base, temp_resources.bus_head->length);
2331 return_resource(&(resources->bus_head), temp_resources.bus_head);
2332 }
2333 }
2334
2335 /* If we have IO space available and there is some left,
2336 * return the unused portion
2337 */
2338 if (hold_IO_node && temp_resources.io_head) {
2339 io_node = do_pre_bridge_resource_split(&(temp_resources.io_head),
2340 &hold_IO_node, 0x1000);
2341
2342 /* Check if we were able to split something off */
2343 if (io_node) {
2344 hold_IO_node->base = io_node->base + io_node->length;
2345
2346 RES_CHECK(hold_IO_node->base, 8);
2347 temp_byte = (u8)((hold_IO_node->base) >> 8);
2348 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_BASE, temp_byte);
2349
2350 return_resource(&(resources->io_head), io_node);
2351 }
2352
2353 io_node = do_bridge_resource_split(&(temp_resources.io_head), 0x1000);
2354
2355 /* Check if we were able to split something off */
2356 if (io_node) {
2357 /* First use the temporary node to store information for the board */
2358 hold_IO_node->length = io_node->base - hold_IO_node->base;
2359
2360 /* If we used any, add it to the board's list */
2361 if (hold_IO_node->length) {
2362 hold_IO_node->next = func->io_head;
2363 func->io_head = hold_IO_node;
2364
2365 RES_CHECK(io_node->base - 1, 8);
2366 temp_byte = (u8)((io_node->base - 1) >> 8);
2367 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2368
2369 return_resource(&(resources->io_head), io_node);
2370 } else {
2371 /* it doesn't need any IO */
2372 temp_byte = 0x00;
2373 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2374
2375 return_resource(&(resources->io_head), io_node);
2376 kfree(hold_IO_node);
2377 }
2378 } else {
2379 /* it used most of the range */
2380 hold_IO_node->next = func->io_head;
2381 func->io_head = hold_IO_node;
2382 }
2383 } else if (hold_IO_node) {
2384 /* it used the whole range */
2385 hold_IO_node->next = func->io_head;
2386 func->io_head = hold_IO_node;
2387 }
2388
2389 /* If we have memory space available and there is some left,
2390 * return the unused portion
2391 */
2392 if (hold_mem_node && temp_resources.mem_head) {
2393 mem_node = do_pre_bridge_resource_split(&(temp_resources.mem_head), &hold_mem_node, 0x100000L);
2394
2395 /* Check if we were able to split something off */
2396 if (mem_node) {
2397 hold_mem_node->base = mem_node->base + mem_node->length;
2398
2399 RES_CHECK(hold_mem_node->base, 16);
2400 temp_word = (u16)((hold_mem_node->base) >> 16);
2401 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
2402
2403 return_resource(&(resources->mem_head), mem_node);
2404 }
2405
2406 mem_node = do_bridge_resource_split(&(temp_resources.mem_head), 0x100000L);
2407
2408 /* Check if we were able to split something off */
2409 if (mem_node) {
2410 /* First use the temporary node to store information for the board */
2411 hold_mem_node->length = mem_node->base - hold_mem_node->base;
2412
2413 if (hold_mem_node->length) {
2414 hold_mem_node->next = func->mem_head;
2415 func->mem_head = hold_mem_node;
2416
2417 /* configure end address */
2418 RES_CHECK(mem_node->base - 1, 16);
2419 temp_word = (u16)((mem_node->base - 1) >> 16);
2420 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
2421
2422 /* Return unused resources to the pool */
2423 return_resource(&(resources->mem_head), mem_node);
2424 } else {
2425 /* it doesn't need any Mem */
2426 temp_word = 0x0000;
2427 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
2428
2429 return_resource(&(resources->mem_head), mem_node);
2430 kfree(hold_mem_node);
2431 }
2432 } else {
2433 /* it used most of the range */
2434 hold_mem_node->next = func->mem_head;
2435 func->mem_head = hold_mem_node;
2436 }
2437 } else if (hold_mem_node) {
2438 /* it used the whole range */
2439 hold_mem_node->next = func->mem_head;
2440 func->mem_head = hold_mem_node;
2441 }
2442
2443 /* If we have prefetchable memory space available and there is some
2444 * left at the end, return the unused portion
2445 */
2446 if (hold_p_mem_node && temp_resources.p_mem_head) {
2447 p_mem_node = do_pre_bridge_resource_split(&(temp_resources.p_mem_head),
2448 &hold_p_mem_node, 0x100000L);
2449
2450 /* Check if we were able to split something off */
2451 if (p_mem_node) {
2452 hold_p_mem_node->base = p_mem_node->base + p_mem_node->length;
2453
2454 RES_CHECK(hold_p_mem_node->base, 16);
2455 temp_word = (u16)((hold_p_mem_node->base) >> 16);
2456 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
2457
2458 return_resource(&(resources->p_mem_head), p_mem_node);
2459 }
2460
2461 p_mem_node = do_bridge_resource_split(&(temp_resources.p_mem_head), 0x100000L);
2462
2463 /* Check if we were able to split something off */
2464 if (p_mem_node) {
2465 /* First use the temporary node to store information for the board */
2466 hold_p_mem_node->length = p_mem_node->base - hold_p_mem_node->base;
2467
2468 /* If we used any, add it to the board's list */
2469 if (hold_p_mem_node->length) {
2470 hold_p_mem_node->next = func->p_mem_head;
2471 func->p_mem_head = hold_p_mem_node;
2472
2473 RES_CHECK(p_mem_node->base - 1, 16);
2474 temp_word = (u16)((p_mem_node->base - 1) >> 16);
2475 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
2476
2477 return_resource(&(resources->p_mem_head), p_mem_node);
2478 } else {
2479 /* it doesn't need any PMem */
2480 temp_word = 0x0000;
2481 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
2482
2483 return_resource(&(resources->p_mem_head), p_mem_node);
2484 kfree(hold_p_mem_node);
2485 }
2486 } else {
2487 /* it used the most of the range */
2488 hold_p_mem_node->next = func->p_mem_head;
2489 func->p_mem_head = hold_p_mem_node;
2490 }
2491 } else if (hold_p_mem_node) {
2492 /* it used the whole range */
2493 hold_p_mem_node->next = func->p_mem_head;
2494 func->p_mem_head = hold_p_mem_node;
2495 }
2496
2497 /* We should be configuring an IRQ and the bridge's base address
2498 * registers if it needs them. Although we have never seen such
2499 * a device
2500 */
2501
2502 pciehprm_enable_card(ctrl, func, PCI_HEADER_TYPE_BRIDGE);
2503
2504 dbg("PCI Bridge Hot-Added s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus, func->device, func->function);
2505
2506 return rc;
2507} 843}
2508 844
2509/**
2510 * configure_new_function - Configures the PCI header information of one device
2511 *
2512 * @ctrl: pointer to controller structure
2513 * @func: pointer to function structure
2514 * @behind_bridge: 1 if this is a recursive call, 0 if not
2515 * @resources: pointer to set of resource lists
2516 *
2517 * Calls itself recursively for bridged devices.
2518 * Returns 0 if success
2519 *
2520 */
2521static int
2522configure_new_function(struct controller *ctrl, struct pci_func *func,
2523 u8 behind_bridge, struct resource_lists *resources,
2524 u8 bridge_bus, u8 bridge_dev)
2525{
2526 int cloop;
2527 u8 temp_byte;
2528 u8 class_code;
2529 u32 rc;
2530 u32 temp_register;
2531 u32 base;
2532 unsigned int devfn;
2533 struct pci_resource *mem_node;
2534 struct pci_resource *io_node;
2535 struct pci_bus lpci_bus, *pci_bus;
2536
2537 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
2538 pci_bus = &lpci_bus;
2539 pci_bus->number = func->bus;
2540 devfn = PCI_DEVFN(func->device, func->function);
2541
2542 /* Check for Bridge */
2543 rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &temp_byte);
2544 if (rc)
2545 return rc;
2546 dbg("%s: bus %x dev %x func %x temp_byte = %x\n", __FUNCTION__,
2547 func->bus, func->device, func->function, temp_byte);
2548
2549 if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
2550 rc = configure_new_bridge(ctrl, func, behind_bridge, resources,
2551 pci_bus);
2552
2553 if (rc)
2554 return rc;
2555 } else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
2556 /* Standard device */
2557 u64 base64;
2558 rc = pci_bus_read_config_byte(pci_bus, devfn, 0x0B, &class_code);
2559
2560 if (class_code == PCI_BASE_CLASS_DISPLAY)
2561 return DEVICE_TYPE_NOT_SUPPORTED;
2562
2563 /* Figure out IO and memory needs */
2564 for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
2565 temp_register = 0xFFFFFFFF;
2566
2567 rc = pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
2568 rc = pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
2569 dbg("Bar[%x]=0x%x on bus:dev:func(0x%x:%x:%x)\n", cloop, temp_register,
2570 func->bus, func->device, func->function);
2571
2572 if (!temp_register)
2573 continue;
2574
2575 base64 = 0L;
2576 if (temp_register & PCI_BASE_ADDRESS_SPACE_IO) {
2577 /* Map IO */
2578
2579 /* set base = amount of IO space */
2580 base = temp_register & 0xFFFFFFFC;
2581 base = ~base + 1;
2582
2583 dbg("NEED IO length(0x%x)\n", base);
2584 io_node = get_io_resource(&(resources->io_head),(ulong)base);
2585
2586 /* allocate the resource to the board */
2587 if (io_node) {
2588 dbg("Got IO base=0x%x(length=0x%x)\n", io_node->base, io_node->length);
2589 base = (u32)io_node->base;
2590 io_node->next = func->io_head;
2591 func->io_head = io_node;
2592 } else {
2593 err("Got NO IO resource(length=0x%x)\n", base);
2594 return -ENOMEM;
2595 }
2596 } else { /* map MEM */
2597 int prefetchable = 1;
2598 struct pci_resource **res_node = &func->p_mem_head;
2599 char *res_type_str = "PMEM";
2600 u32 temp_register2;
2601
2602 if (!(temp_register & PCI_BASE_ADDRESS_MEM_PREFETCH)) {
2603 prefetchable = 0;
2604 res_node = &func->mem_head;
2605 res_type_str++;
2606 }
2607
2608 base = temp_register & 0xFFFFFFF0;
2609 base = ~base + 1;
2610
2611 switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
2612 case PCI_BASE_ADDRESS_MEM_TYPE_32:
2613 dbg("NEED 32 %s bar=0x%x(length=0x%x)\n", res_type_str, temp_register, base);
2614
2615 if (prefetchable && resources->p_mem_head)
2616 mem_node=get_resource(&(resources->p_mem_head), (ulong)base);
2617 else {
2618 if (prefetchable)
2619 dbg("using MEM for PMEM\n");
2620 mem_node = get_resource(&(resources->mem_head), (ulong)base);
2621 }
2622
2623 /* allocate the resource to the board */
2624 if (mem_node) {
2625 base = (u32)mem_node->base;
2626 mem_node->next = *res_node;
2627 *res_node = mem_node;
2628 dbg("Got 32 %s base=0x%x(length=0x%x)\n", res_type_str, mem_node->base,
2629 mem_node->length);
2630 } else {
2631 err("Got NO 32 %s resource(length=0x%x)\n", res_type_str, base);
2632 return -ENOMEM;
2633 }
2634 break;
2635 case PCI_BASE_ADDRESS_MEM_TYPE_64:
2636 rc = pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
2637 dbg("NEED 64 %s bar=0x%x:%x(length=0x%x)\n", res_type_str, temp_register2,
2638 temp_register, base);
2639
2640 if (prefetchable && resources->p_mem_head)
2641 mem_node = get_resource(&(resources->p_mem_head), (ulong)base);
2642 else {
2643 if (prefetchable)
2644 dbg("using MEM for PMEM\n");
2645 mem_node = get_resource(&(resources->mem_head), (ulong)base);
2646 }
2647
2648 /* allocate the resource to the board */
2649 if (mem_node) {
2650 base64 = mem_node->base;
2651 mem_node->next = *res_node;
2652 *res_node = mem_node;
2653 dbg("Got 64 %s base=0x%x:%x(length=%x)\n", res_type_str, (u32)(base64 >> 32),
2654 (u32)base64, mem_node->length);
2655 } else {
2656 err("Got NO 64 %s resource(length=0x%x)\n", res_type_str, base);
2657 return -ENOMEM;
2658 }
2659 break;
2660 default:
2661 dbg("reserved BAR type=0x%x\n", temp_register);
2662 break;
2663 }
2664
2665 }
2666
2667 if (base64) {
2668 rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, (u32)base64);
2669 cloop += 4;
2670 base64 >>= 32;
2671
2672 if (base64) {
2673 dbg("%s: high dword of base64(0x%x) set to 0\n", __FUNCTION__, (u32)base64);
2674 base64 = 0x0L;
2675 }
2676
2677 rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, (u32)base64);
2678 } else {
2679 rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, base);
2680 }
2681 } /* End of base register loop */
2682
2683 /* disable ROM base Address */
2684 rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00);
2685
2686 /* Set HP parameters (Cache Line Size, Latency Timer) */
2687 rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);
2688 if (rc)
2689 return rc;
2690
2691 pciehprm_enable_card(ctrl, func, PCI_HEADER_TYPE_NORMAL);
2692
2693 dbg("PCI function Hot-Added s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus, func->device,
2694 func->function);
2695 } /* End of Not-A-Bridge else */
2696 else {
2697 /* It's some strange type of PCI adapter (Cardbus?) */
2698 return DEVICE_TYPE_NOT_SUPPORTED;
2699 }
2700
2701 func->configured = 1;
2702
2703 return 0;
2704}
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 7a0e27f0e063..0b8b26beb163 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -27,16 +27,12 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/kernel.h> 30#include <linux/kernel.h>
32#include <linux/module.h> 31#include <linux/module.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/slab.h>
35#include <linux/vmalloc.h>
36#include <linux/interrupt.h>
37#include <linux/spinlock.h>
38#include <linux/pci.h> 33#include <linux/pci.h>
39#include <asm/system.h> 34#include <linux/interrupt.h>
35
40#include "../pci.h" 36#include "../pci.h"
41#include "pciehp.h" 37#include "pciehp.h"
42 38
@@ -217,23 +213,6 @@ static int pcie_cap_base = 0; /* Base of the PCI Express capability item struct
217#define MRL_STATE 0x0020 213#define MRL_STATE 0x0020
218#define PRSN_STATE 0x0040 214#define PRSN_STATE 0x0040
219 215
220struct php_ctlr_state_s {
221 struct php_ctlr_state_s *pnext;
222 struct pci_dev *pci_dev;
223 unsigned int irq;
224 unsigned long flags; /* spinlock's */
225 u32 slot_device_offset;
226 u32 num_slots;
227 struct timer_list int_poll_timer; /* Added for poll event */
228 php_intr_callback_t attention_button_callback;
229 php_intr_callback_t switch_change_callback;
230 php_intr_callback_t presence_change_callback;
231 php_intr_callback_t power_fault_callback;
232 void *callback_instance_id;
233 struct ctrl_reg *creg; /* Ptr to controller register space */
234};
235
236
237static spinlock_t hpc_event_lock; 216static spinlock_t hpc_event_lock;
238 217
239DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 218DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
@@ -297,7 +276,6 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd)
297 276
298 DBG_ENTER_ROUTINE 277 DBG_ENTER_ROUTINE
299 278
300 dbg("%s : Enter\n", __FUNCTION__);
301 if (!php_ctlr) { 279 if (!php_ctlr) {
302 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 280 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
303 return -1; 281 return -1;
@@ -308,7 +286,6 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd)
308 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 286 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
309 return retval; 287 return retval;
310 } 288 }
311 dbg("%s : hp_register_read_word SLOT_STATUS %x\n", __FUNCTION__, slot_status);
312 289
313 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { 290 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
314 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue 291 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
@@ -316,14 +293,11 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd)
316 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__); 293 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
317 } 294 }
318 295
319 dbg("%s: Before hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd);
320 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE); 296 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
321 if (retval) { 297 if (retval) {
322 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 298 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
323 return retval; 299 return retval;
324 } 300 }
325 dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd | CMD_CMPL_INTR_ENABLE);
326 dbg("%s : Exit\n", __FUNCTION__);
327 301
328 DBG_LEAVE_ROUTINE 302 DBG_LEAVE_ROUTINE
329 return retval; 303 return retval;
@@ -509,7 +483,6 @@ static int hpc_query_power_fault(struct slot * slot)
509 u16 slot_status; 483 u16 slot_status;
510 u8 pwr_fault; 484 u8 pwr_fault;
511 int retval = 0; 485 int retval = 0;
512 u8 status;
513 486
514 DBG_ENTER_ROUTINE 487 DBG_ENTER_ROUTINE
515 488
@@ -521,15 +494,13 @@ static int hpc_query_power_fault(struct slot * slot)
521 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); 494 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
522 495
523 if (retval) { 496 if (retval) {
524 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 497 err("%s : Cannot check for power fault\n", __FUNCTION__);
525 return retval; 498 return retval;
526 } 499 }
527 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); 500 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
528 status = (pwr_fault != 1) ? 1 : 0;
529 501
530 DBG_LEAVE_ROUTINE 502 DBG_LEAVE_ROUTINE
531 /* Note: Logic 0 => fault */ 503 return pwr_fault;
532 return status;
533} 504}
534 505
535static int hpc_set_attention_status(struct slot *slot, u8 value) 506static int hpc_set_attention_status(struct slot *slot, u8 value)
@@ -539,7 +510,8 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
539 u16 slot_ctrl; 510 u16 slot_ctrl;
540 int rc = 0; 511 int rc = 0;
541 512
542 dbg("%s: \n", __FUNCTION__); 513 DBG_ENTER_ROUTINE
514
543 if (!php_ctlr) { 515 if (!php_ctlr) {
544 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 516 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
545 return -1; 517 return -1;
@@ -555,7 +527,6 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
555 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 527 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
556 return rc; 528 return rc;
557 } 529 }
558 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
559 530
560 switch (value) { 531 switch (value) {
561 case 0 : /* turn off */ 532 case 0 : /* turn off */
@@ -576,6 +547,7 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
576 pcie_write_cmd(slot, slot_cmd); 547 pcie_write_cmd(slot, slot_cmd);
577 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); 548 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
578 549
550 DBG_LEAVE_ROUTINE
579 return rc; 551 return rc;
580} 552}
581 553
@@ -587,7 +559,8 @@ static void hpc_set_green_led_on(struct slot *slot)
587 u16 slot_ctrl; 559 u16 slot_ctrl;
588 int rc = 0; 560 int rc = 0;
589 561
590 dbg("%s: \n", __FUNCTION__); 562 DBG_ENTER_ROUTINE
563
591 if (!php_ctlr) { 564 if (!php_ctlr) {
592 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 565 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
593 return ; 566 return ;
@@ -604,7 +577,6 @@ static void hpc_set_green_led_on(struct slot *slot)
604 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 577 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
605 return; 578 return;
606 } 579 }
607 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
608 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; 580 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
609 if (!pciehp_poll_mode) 581 if (!pciehp_poll_mode)
610 slot_cmd = slot_cmd | HP_INTR_ENABLE; 582 slot_cmd = slot_cmd | HP_INTR_ENABLE;
@@ -612,6 +584,7 @@ static void hpc_set_green_led_on(struct slot *slot)
612 pcie_write_cmd(slot, slot_cmd); 584 pcie_write_cmd(slot, slot_cmd);
613 585
614 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); 586 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
587 DBG_LEAVE_ROUTINE
615 return; 588 return;
616} 589}
617 590
@@ -622,7 +595,8 @@ static void hpc_set_green_led_off(struct slot *slot)
622 u16 slot_ctrl; 595 u16 slot_ctrl;
623 int rc = 0; 596 int rc = 0;
624 597
625 dbg("%s: \n", __FUNCTION__); 598 DBG_ENTER_ROUTINE
599
626 if (!php_ctlr) { 600 if (!php_ctlr) {
627 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 601 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
628 return ; 602 return ;
@@ -639,7 +613,6 @@ static void hpc_set_green_led_off(struct slot *slot)
639 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 613 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
640 return; 614 return;
641 } 615 }
642 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
643 616
644 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; 617 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
645 618
@@ -648,6 +621,7 @@ static void hpc_set_green_led_off(struct slot *slot)
648 pcie_write_cmd(slot, slot_cmd); 621 pcie_write_cmd(slot, slot_cmd);
649 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); 622 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
650 623
624 DBG_LEAVE_ROUTINE
651 return; 625 return;
652} 626}
653 627
@@ -658,7 +632,8 @@ static void hpc_set_green_led_blink(struct slot *slot)
658 u16 slot_ctrl; 632 u16 slot_ctrl;
659 int rc = 0; 633 int rc = 0;
660 634
661 dbg("%s: \n", __FUNCTION__); 635 DBG_ENTER_ROUTINE
636
662 if (!php_ctlr) { 637 if (!php_ctlr) {
663 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 638 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
664 return ; 639 return ;
@@ -675,7 +650,6 @@ static void hpc_set_green_led_blink(struct slot *slot)
675 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 650 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
676 return; 651 return;
677 } 652 }
678 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
679 653
680 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; 654 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
681 655
@@ -684,6 +658,7 @@ static void hpc_set_green_led_blink(struct slot *slot)
684 pcie_write_cmd(slot, slot_cmd); 658 pcie_write_cmd(slot, slot_cmd);
685 659
686 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); 660 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
661 DBG_LEAVE_ROUTINE
687 return; 662 return;
688} 663}
689 664
@@ -775,12 +750,11 @@ static int hpc_power_on_slot(struct slot * slot)
775{ 750{
776 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 751 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
777 u16 slot_cmd; 752 u16 slot_cmd;
778 u16 slot_ctrl; 753 u16 slot_ctrl, slot_status;
779 754
780 int retval = 0; 755 int retval = 0;
781 756
782 DBG_ENTER_ROUTINE 757 DBG_ENTER_ROUTINE
783 dbg("%s: \n", __FUNCTION__);
784 758
785 if (!php_ctlr) { 759 if (!php_ctlr) {
786 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 760 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
@@ -793,14 +767,20 @@ static int hpc_power_on_slot(struct slot * slot)
793 return -1; 767 return -1;
794 } 768 }
795 769
770 /* Clear sticky power-fault bit from previous power failures */
771 hp_register_read_word(php_ctlr->pci_dev,
772 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
773 slot_status &= PWR_FAULT_DETECTED;
774 if (slot_status)
775 hp_register_write_word(php_ctlr->pci_dev,
776 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
777
796 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); 778 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
797 779
798 if (retval) { 780 if (retval) {
799 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 781 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
800 return retval; 782 return retval;
801 } 783 }
802 dbg("%s: SLOT_CTRL %x, value read %xn", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base),
803 slot_ctrl);
804 784
805 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; 785 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
806 786
@@ -829,7 +809,6 @@ static int hpc_power_off_slot(struct slot * slot)
829 int retval = 0; 809 int retval = 0;
830 810
831 DBG_ENTER_ROUTINE 811 DBG_ENTER_ROUTINE
832 dbg("%s: \n", __FUNCTION__);
833 812
834 if (!php_ctlr) { 813 if (!php_ctlr) {
835 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 814 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
@@ -848,8 +827,6 @@ static int hpc_power_off_slot(struct slot * slot)
848 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 827 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
849 return retval; 828 return retval;
850 } 829 }
851 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base),
852 slot_ctrl);
853 830
854 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; 831 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
855 832
@@ -924,7 +901,6 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
924 return IRQ_NONE; 901 return IRQ_NONE;
925 } 902 }
926 903
927 dbg("%s: Set Mask Hot-plug Interrupt Enable\n", __FUNCTION__);
928 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); 904 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
929 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; 905 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
930 906
@@ -933,7 +909,6 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
933 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 909 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
934 return IRQ_NONE; 910 return IRQ_NONE;
935 } 911 }
936 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
937 912
938 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); 913 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
939 if (rc) { 914 if (rc) {
@@ -949,14 +924,12 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
949 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 924 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
950 return IRQ_NONE; 925 return IRQ_NONE;
951 } 926 }
952 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
953 } 927 }
954 928
955 if (intr_loc & CMD_COMPLETED) { 929 if (intr_loc & CMD_COMPLETED) {
956 /* 930 /*
957 * Command Complete Interrupt Pending 931 * Command Complete Interrupt Pending
958 */ 932 */
959 dbg("%s: In Command Complete Interrupt Pending\n", __FUNCTION__);
960 wake_up_interruptible(&ctrl->queue); 933 wake_up_interruptible(&ctrl->queue);
961 } 934 }
962 935
@@ -989,7 +962,6 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
989 } 962 }
990 963
991 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); 964 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
992 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
993 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; 965 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
994 966
995 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); 967 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
@@ -997,14 +969,12 @@ static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
997 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 969 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
998 return IRQ_NONE; 970 return IRQ_NONE;
999 } 971 }
1000 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
1001 972
1002 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); 973 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1003 if (rc) { 974 if (rc) {
1004 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 975 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1005 return IRQ_NONE; 976 return IRQ_NONE;
1006 } 977 }
1007 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
1008 978
1009 /* Clear command complete interrupt caused by this write */ 979 /* Clear command complete interrupt caused by this write */
1010 temp_word = 0x1F; 980 temp_word = 0x1F;
@@ -1248,12 +1218,7 @@ static struct hpc_ops pciehp_hpc_ops = {
1248 .check_lnk_status = hpc_check_lnk_status, 1218 .check_lnk_status = hpc_check_lnk_status,
1249}; 1219};
1250 1220
1251int pcie_init(struct controller * ctrl, 1221int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1252 struct pcie_device *dev,
1253 php_intr_callback_t attention_button_callback,
1254 php_intr_callback_t switch_change_callback,
1255 php_intr_callback_t presence_change_callback,
1256 php_intr_callback_t power_fault_callback)
1257{ 1222{
1258 struct php_ctlr_state_s *php_ctlr, *p; 1223 struct php_ctlr_state_s *php_ctlr, *p;
1259 void *instance_id = ctrl; 1224 void *instance_id = ctrl;
@@ -1282,8 +1247,8 @@ int pcie_init(struct controller * ctrl,
1282 pdev = dev->port; 1247 pdev = dev->port;
1283 php_ctlr->pci_dev = pdev; /* save pci_dev in context */ 1248 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1284 1249
1285 dbg("%s: pdev->vendor %x pdev->device %x\n", __FUNCTION__, 1250 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1286 pdev->vendor, pdev->device); 1251 __FUNCTION__, pdev->vendor, pdev->device);
1287 1252
1288 saved_cap_base = pcie_cap_base; 1253 saved_cap_base = pcie_cap_base;
1289 1254
@@ -1340,8 +1305,6 @@ int pcie_init(struct controller * ctrl,
1340 first = 0; 1305 first = 0;
1341 } 1306 }
1342 1307
1343 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number,
1344 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1345 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) 1308 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1346 if (pci_resource_len(pdev, rc) > 0) 1309 if (pci_resource_len(pdev, rc) > 0)
1347 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc, 1310 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
@@ -1359,13 +1322,12 @@ int pcie_init(struct controller * ctrl,
1359 1322
1360 /* find the IRQ */ 1323 /* find the IRQ */
1361 php_ctlr->irq = dev->irq; 1324 php_ctlr->irq = dev->irq;
1362 dbg("HPC interrupt = %d\n", php_ctlr->irq);
1363 1325
1364 /* Save interrupt callback info */ 1326 /* Save interrupt callback info */
1365 php_ctlr->attention_button_callback = attention_button_callback; 1327 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1366 php_ctlr->switch_change_callback = switch_change_callback; 1328 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1367 php_ctlr->presence_change_callback = presence_change_callback; 1329 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1368 php_ctlr->power_fault_callback = power_fault_callback; 1330 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1369 php_ctlr->callback_instance_id = instance_id; 1331 php_ctlr->callback_instance_id = instance_id;
1370 1332
1371 /* return PCI Controller Info */ 1333 /* return PCI Controller Info */
@@ -1387,15 +1349,12 @@ int pcie_init(struct controller * ctrl,
1387 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 1349 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1388 goto abort_free_ctlr; 1350 goto abort_free_ctlr;
1389 } 1351 }
1390 dbg("%s : Mask HPIE hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, temp_word);
1391 1352
1392 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); 1353 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1393 if (rc) { 1354 if (rc) {
1394 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 1355 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1395 goto abort_free_ctlr; 1356 goto abort_free_ctlr;
1396 } 1357 }
1397 dbg("%s: Mask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base)
1398 , slot_status);
1399 1358
1400 temp_word = 0x1F; /* Clear all events */ 1359 temp_word = 0x1F; /* Clear all events */
1401 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); 1360 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
@@ -1403,7 +1362,6 @@ int pcie_init(struct controller * ctrl,
1403 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 1362 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1404 goto abort_free_ctlr; 1363 goto abort_free_ctlr;
1405 } 1364 }
1406 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), temp_word);
1407 1365
1408 if (pciehp_poll_mode) {/* Install interrupt polling code */ 1366 if (pciehp_poll_mode) {/* Install interrupt polling code */
1409 /* Install and start the interrupt polling timer */ 1367 /* Install and start the interrupt polling timer */
@@ -1419,13 +1377,14 @@ int pcie_init(struct controller * ctrl,
1419 } 1377 }
1420 } 1378 }
1421 1379
1380 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1381 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1382
1422 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); 1383 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1423 if (rc) { 1384 if (rc) {
1424 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 1385 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1425 goto abort_free_ctlr; 1386 goto abort_free_ctlr;
1426 } 1387 }
1427 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1428 dbg("%s: slot_cap %x\n", __FUNCTION__, slot_cap);
1429 1388
1430 intr_enable = intr_enable | PRSN_DETECT_ENABLE; 1389 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1431 1390
@@ -1445,7 +1404,6 @@ int pcie_init(struct controller * ctrl,
1445 } else { 1404 } else {
1446 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; 1405 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1447 } 1406 }
1448 dbg("%s: temp_word %x\n", __FUNCTION__, temp_word);
1449 1407
1450 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ 1408 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1451 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); 1409 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
@@ -1453,14 +1411,11 @@ int pcie_init(struct controller * ctrl,
1453 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 1411 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1454 goto abort_free_ctlr; 1412 goto abort_free_ctlr;
1455 } 1413 }
1456 dbg("%s : Unmask HPIE hp_register_write_word SLOT_CTRL with %x\n", __FUNCTION__, temp_word);
1457 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); 1414 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1458 if (rc) { 1415 if (rc) {
1459 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 1416 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1460 goto abort_free_ctlr; 1417 goto abort_free_ctlr;
1461 } 1418 }
1462 dbg("%s: Unmask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__,
1463 SLOT_STATUS(ctrl->cap_base), slot_status);
1464 1419
1465 temp_word = 0x1F; /* Clear all events */ 1420 temp_word = 0x1F; /* Clear all events */
1466 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); 1421 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
@@ -1468,8 +1423,16 @@ int pcie_init(struct controller * ctrl,
1468 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 1423 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1469 goto abort_free_ctlr; 1424 goto abort_free_ctlr;
1470 } 1425 }
1471 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), temp_word);
1472 1426
1427 if (pciehp_force) {
1428 dbg("Bypassing BIOS check for pciehp use on %s\n",
1429 pci_name(ctrl->pci_dev));
1430 } else {
1431 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1432 if (rc)
1433 goto abort_free_ctlr;
1434 }
1435
1473 /* Add this HPC instance into the HPC list */ 1436 /* Add this HPC instance into the HPC list */
1474 spin_lock(&list_lock); 1437 spin_lock(&list_lock);
1475 if (php_ctlr_list_head == 0) { 1438 if (php_ctlr_list_head == 0) {
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index ff17d8e07e94..647673a7d224 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -27,801 +27,111 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/slab.h>
35#include <linux/workqueue.h>
36#include <linux/proc_fs.h>
37#include <linux/pci.h> 33#include <linux/pci.h>
38#include "../pci.h" 34#include "../pci.h"
39#include "pciehp.h" 35#include "pciehp.h"
40#ifndef CONFIG_IA64
41#include "../../../arch/i386/pci/pci.h" /* horrible hack showing how processor dependant we are... */
42#endif
43 36
44 37
45int pciehp_configure_device (struct controller* ctrl, struct pci_func* func) 38int pciehp_configure_device(struct slot *p_slot)
46{ 39{
47 unsigned char bus; 40 struct pci_dev *dev;
48 struct pci_bus *child; 41 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
49 int num; 42 int num, fn;
50 43
51 if (func->pci_dev == NULL) 44 dev = pci_find_slot(p_slot->bus, PCI_DEVFN(p_slot->device, 0));
52 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function)); 45 if (dev) {
53 46 err("Device %s already exists at %x:%x, cannot hot-add\n",
54 /* Still NULL ? Well then scan for it ! */ 47 pci_name(dev), p_slot->bus, p_slot->device);
55 if (func->pci_dev == NULL) { 48 return -EINVAL;
56 dbg("%s: pci_dev still null. do pci_scan_slot\n", __FUNCTION__);
57
58 num = pci_scan_slot(ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function));
59
60 if (num)
61 pci_bus_add_devices(ctrl->pci_dev->subordinate);
62
63 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
64 if (func->pci_dev == NULL) {
65 dbg("ERROR: pci_dev still null\n");
66 return 0;
67 }
68 } 49 }
69 50
70 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 51 num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0));
71 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus); 52 if (num == 0) {
72 child = pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus); 53 err("No new device found\n");
73 pci_do_scan_bus(child); 54 return -ENODEV;
55 }
74 56
57 for (fn = 0; fn < 8; fn++) {
58 if (!(dev = pci_find_slot(p_slot->bus,
59 PCI_DEVFN(p_slot->device, fn))))
60 continue;
61 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
62 err("Cannot hot-add display device %s\n",
63 pci_name(dev));
64 continue;
65 }
66 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
67 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
68 /* Find an unused bus number for the new bridge */
69 struct pci_bus *child;
70 unsigned char busnr, start = parent->secondary;
71 unsigned char end = parent->subordinate;
72 for (busnr = start; busnr <= end; busnr++) {
73 if (!pci_find_bus(pci_domain_nr(parent),
74 busnr))
75 break;
76 }
77 if (busnr >= end) {
78 err("No free bus for hot-added bridge\n");
79 continue;
80 }
81 child = pci_add_new_bus(parent, dev, busnr);
82 if (!child) {
83 err("Cannot add new bus for %s\n",
84 pci_name(dev));
85 continue;
86 }
87 child->subordinate = pci_do_scan_bus(child);
88 pci_bus_size_bridges(child);
89 }
90 /* TBD: program firmware provided _HPP values */
91 /* program_fw_provided_values(dev); */
75 } 92 }
76 93
94 pci_bus_assign_resources(parent);
95 pci_bus_add_devices(parent);
96 pci_enable_bridges(parent);
77 return 0; 97 return 0;
78} 98}
79 99
80 100int pciehp_unconfigure_device(struct slot *p_slot)
81int pciehp_unconfigure_device(struct pci_func* func)
82{ 101{
83 int rc = 0; 102 int rc = 0;
84 int j; 103 int j;
85 struct pci_bus *pbus; 104 u8 bctl = 0;
86 105
87 dbg("%s: bus/dev/func = %x/%x/%x\n", __FUNCTION__, func->bus, 106 dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus,
88 func->device, func->function); 107 p_slot->device);
89 pbus = func->pci_dev->bus;
90 108
91 for (j=0; j<8 ; j++) { 109 for (j=0; j<8 ; j++) {
92 struct pci_dev* temp = pci_find_slot(func->bus, 110 struct pci_dev* temp = pci_find_slot(p_slot->bus,
93 (func->device << 3) | j); 111 (p_slot->device << 3) | j);
94 if (temp) { 112 if (!temp)
95 pci_remove_bus_device(temp); 113 continue;
114 if ((temp->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
115 err("Cannot remove display device %s\n",
116 pci_name(temp));
117 continue;
96 } 118 }
119 if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
120 pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, &bctl);
121 if (bctl & PCI_BRIDGE_CTL_VGA) {
122 err("Cannot remove display device %s\n",
123 pci_name(temp));
124 continue;
125 }
126 }
127 pci_remove_bus_device(temp);
97 } 128 }
98 /* 129 /*
99 * Some PCI Express root ports require fixup after hot-plug operation. 130 * Some PCI Express root ports require fixup after hot-plug operation.
100 */ 131 */
101 if (pcie_mch_quirk) 132 if (pcie_mch_quirk)
102 pci_fixup_device(pci_fixup_final, pbus->self); 133 pci_fixup_device(pci_fixup_final, p_slot->ctrl->pci_dev);
103 134
104 return rc; 135 return rc;
105} 136}
106 137
107/*
108 * pciehp_set_irq
109 *
110 * @bus_num: bus number of PCI device
111 * @dev_num: device number of PCI device
112 * @slot: pointer to u8 where slot number will be returned
113 */
114int pciehp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
115{
116#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_IO_APIC)
117 int rc;
118 u16 temp_word;
119 struct pci_dev fakedev;
120 struct pci_bus fakebus;
121
122 fakedev.devfn = dev_num << 3;
123 fakedev.bus = &fakebus;
124 fakebus.number = bus_num;
125 dbg("%s: dev %d, bus %d, pin %d, num %d\n",
126 __FUNCTION__, dev_num, bus_num, int_pin, irq_num);
127 rc = pcibios_set_irq_routing(&fakedev, int_pin - 0x0a, irq_num);
128 dbg("%s: rc %d\n", __FUNCTION__, rc);
129 if (!rc)
130 return !rc;
131
132 /* set the Edge Level Control Register (ELCR) */
133 temp_word = inb(0x4d0);
134 temp_word |= inb(0x4d1) << 8;
135
136 temp_word |= 0x01 << irq_num;
137
138 /* This should only be for x86 as it sets the Edge Level Control Register */
139 outb((u8) (temp_word & 0xFF), 0x4d0);
140 outb((u8) ((temp_word & 0xFF00) >> 8), 0x4d1);
141#endif
142 return 0;
143}
144
145/* More PCI configuration routines; this time centered around hotplug controller */
146
147
148/*
149 * pciehp_save_config
150 *
151 * Reads configuration for all slots in a PCI bus and saves info.
152 *
153 * Note: For non-hot plug busses, the slot # saved is the device #
154 *
155 * returns 0 if success
156 */
157int pciehp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num)
158{
159 int rc;
160 u8 class_code;
161 u8 header_type;
162 u32 ID;
163 u8 secondary_bus;
164 struct pci_func *new_slot;
165 int sub_bus;
166 int max_functions;
167 int function;
168 u8 DevError;
169 int device = 0;
170 int cloop = 0;
171 int stop_it;
172 int index;
173 int is_hot_plug = num_ctlr_slots || first_device_num;
174 struct pci_bus lpci_bus, *pci_bus;
175 int FirstSupported, LastSupported;
176
177 dbg("%s: Enter\n", __FUNCTION__);
178
179 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
180 pci_bus = &lpci_bus;
181
182 dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__,
183 num_ctlr_slots, first_device_num);
184
185 /* Decide which slots are supported */
186 if (is_hot_plug) {
187 /*********************************
188 * is_hot_plug is the slot mask
189 *********************************/
190 FirstSupported = first_device_num;
191 LastSupported = FirstSupported + num_ctlr_slots - 1;
192 } else {
193 FirstSupported = 0;
194 LastSupported = 0x1F;
195 }
196
197 dbg("FirstSupported = %d, LastSupported = %d\n", FirstSupported,
198 LastSupported);
199
200 /* Save PCI configuration space for all devices in supported slots */
201 dbg("%s: pci_bus->number = %x\n", __FUNCTION__, pci_bus->number);
202 pci_bus->number = busnumber;
203 dbg("%s: bus = %x, dev = %x\n", __FUNCTION__, busnumber, device);
204 for (device = FirstSupported; device <= LastSupported; device++) {
205 ID = 0xFFFFFFFF;
206 rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0),
207 PCI_VENDOR_ID, &ID);
208
209 if (ID != 0xFFFFFFFF) { /* device in slot */
210 dbg("%s: ID = %x\n", __FUNCTION__, ID);
211 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
212 0x0B, &class_code);
213 if (rc)
214 return rc;
215
216 rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
217 PCI_HEADER_TYPE, &header_type);
218 if (rc)
219 return rc;
220
221 dbg("class_code = %x, header_type = %x\n", class_code, header_type);
222
223 /* If multi-function device, set max_functions to 8 */
224 if (header_type & 0x80)
225 max_functions = 8;
226 else
227 max_functions = 1;
228
229 function = 0;
230
231 do {
232 DevError = 0;
233 dbg("%s: In do loop\n", __FUNCTION__);
234
235 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* P-P Bridge */
236 /* Recurse the subordinate bus
237 * get the subordinate bus number
238 */
239 rc = pci_bus_read_config_byte(pci_bus,
240 PCI_DEVFN(device, function),
241 PCI_SECONDARY_BUS, &secondary_bus);
242 if (rc) {
243 return rc;
244 } else {
245 sub_bus = (int) secondary_bus;
246
247 /* Save secondary bus cfg spc with this recursive call. */
248 rc = pciehp_save_config(ctrl, sub_bus, 0, 0);
249 if (rc)
250 return rc;
251 }
252 }
253
254 index = 0;
255 new_slot = pciehp_slot_find(busnumber, device, index++);
256
257 dbg("%s: new_slot = %p bus %x dev %x fun %x\n",
258 __FUNCTION__, new_slot, busnumber, device, index-1);
259
260 while (new_slot && (new_slot->function != (u8) function)) {
261 new_slot = pciehp_slot_find(busnumber, device, index++);
262 dbg("%s: while loop, new_slot = %p bus %x dev %x fun %x\n",
263 __FUNCTION__, new_slot, busnumber, device, index-1);
264 }
265 if (!new_slot) {
266 /* Setup slot structure. */
267 new_slot = pciehp_slot_create(busnumber);
268 dbg("%s: if, new_slot = %p bus %x dev %x fun %x\n",
269 __FUNCTION__, new_slot, busnumber, device, function);
270
271 if (new_slot == NULL)
272 return(1);
273 }
274
275 new_slot->bus = (u8) busnumber;
276 new_slot->device = (u8) device;
277 new_slot->function = (u8) function;
278 new_slot->is_a_board = 1;
279 new_slot->switch_save = 0x10;
280 /* In case of unsupported board */
281 new_slot->status = DevError;
282 new_slot->pci_dev = pci_find_slot(new_slot->bus,
283 (new_slot->device << 3) | new_slot->function);
284 dbg("new_slot->pci_dev = %p\n", new_slot->pci_dev);
285
286 for (cloop = 0; cloop < 0x20; cloop++) {
287 rc = pci_bus_read_config_dword(pci_bus,
288 PCI_DEVFN(device, function),
289 cloop << 2,
290 (u32 *) &(new_slot->config_space [cloop]));
291 /* dbg("new_slot->config_space[%x] = %x\n",
292 cloop, new_slot->config_space[cloop]); */
293 if (rc)
294 return rc;
295 }
296
297 function++;
298
299 stop_it = 0;
300
301 /* this loop skips to the next present function
302 * reading in Class Code and Header type.
303 */
304
305 while ((function < max_functions)&&(!stop_it)) {
306 dbg("%s: In while loop \n", __FUNCTION__);
307 rc = pci_bus_read_config_dword(pci_bus,
308 PCI_DEVFN(device, function),
309 PCI_VENDOR_ID, &ID);
310
311 if (ID == 0xFFFFFFFF) { /* nothing there. */
312 function++;
313 dbg("Nothing there\n");
314 } else { /* Something there */
315 rc = pci_bus_read_config_byte(pci_bus,
316 PCI_DEVFN(device, function),
317 0x0B, &class_code);
318 if (rc)
319 return rc;
320
321 rc = pci_bus_read_config_byte(pci_bus,
322 PCI_DEVFN(device, function),
323 PCI_HEADER_TYPE, &header_type);
324 if (rc)
325 return rc;
326
327 dbg("class_code = %x, header_type = %x\n", class_code, header_type);
328 stop_it++;
329 }
330 }
331
332 } while (function < max_functions);
333 /* End of IF (device in slot?) */
334 } else if (is_hot_plug) {
335 /* Setup slot structure with entry for empty slot */
336 new_slot = pciehp_slot_create(busnumber);
337
338 if (new_slot == NULL) {
339 return(1);
340 }
341 dbg("new_slot = %p, bus = %x, dev = %x, fun = %x\n", new_slot,
342 new_slot->bus, new_slot->device, new_slot->function);
343
344 new_slot->bus = (u8) busnumber;
345 new_slot->device = (u8) device;
346 new_slot->function = 0;
347 new_slot->is_a_board = 0;
348 new_slot->presence_save = 0;
349 new_slot->switch_save = 0;
350 }
351 } /* End of FOR loop */
352
353 dbg("%s: Exit\n", __FUNCTION__);
354 return(0);
355}
356
357
358/*
359 * pciehp_save_slot_config
360 *
361 * Saves configuration info for all PCI devices in a given slot
362 * including subordinate busses.
363 *
364 * returns 0 if success
365 */
366int pciehp_save_slot_config(struct controller *ctrl, struct pci_func * new_slot)
367{
368 int rc;
369 u8 class_code;
370 u8 header_type;
371 u32 ID;
372 u8 secondary_bus;
373 int sub_bus;
374 int max_functions;
375 int function;
376 int cloop = 0;
377 int stop_it;
378 struct pci_bus lpci_bus, *pci_bus;
379 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
380 pci_bus = &lpci_bus;
381 pci_bus->number = new_slot->bus;
382
383 ID = 0xFFFFFFFF;
384
385 pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, 0),
386 PCI_VENDOR_ID, &ID);
387
388 if (ID != 0xFFFFFFFF) { /* device in slot */
389 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
390 0x0B, &class_code);
391
392 pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
393 PCI_HEADER_TYPE, &header_type);
394
395 if (header_type & 0x80) /* Multi-function device */
396 max_functions = 8;
397 else
398 max_functions = 1;
399
400 function = 0;
401
402 do {
403 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
404 /* Recurse the subordinate bus */
405 pci_bus_read_config_byte(pci_bus,
406 PCI_DEVFN(new_slot->device, function),
407 PCI_SECONDARY_BUS, &secondary_bus);
408
409 sub_bus = (int) secondary_bus;
410
411 /* Save the config headers for the secondary bus. */
412 rc = pciehp_save_config(ctrl, sub_bus, 0, 0);
413
414 if (rc)
415 return rc;
416
417 } /* End of IF */
418
419 new_slot->status = 0;
420
421 for (cloop = 0; cloop < 0x20; cloop++) {
422 pci_bus_read_config_dword(pci_bus,
423 PCI_DEVFN(new_slot->device, function),
424 cloop << 2,
425 (u32 *) &(new_slot->config_space [cloop]));
426 }
427
428 function++;
429
430 stop_it = 0;
431
432 /* this loop skips to the next present function
433 * reading in the Class Code and the Header type.
434 */
435
436 while ((function < max_functions) && (!stop_it)) {
437 pci_bus_read_config_dword(pci_bus,
438 PCI_DEVFN(new_slot->device, function),
439 PCI_VENDOR_ID, &ID);
440
441 if (ID == 0xFFFFFFFF) { /* nothing there. */
442 function++;
443 } else { /* Something there */
444 pci_bus_read_config_byte(pci_bus,
445 PCI_DEVFN(new_slot->device, function),
446 0x0B, &class_code);
447
448 pci_bus_read_config_byte(pci_bus,
449 PCI_DEVFN(new_slot->device, function),
450 PCI_HEADER_TYPE, &header_type);
451
452 stop_it++;
453 }
454 }
455
456 } while (function < max_functions);
457 } /* End of IF (device in slot?) */
458 else {
459 return 2;
460 }
461
462 return 0;
463}
464
465
466/*
467 * pciehp_save_used_resources
468 *
469 * Stores used resource information for existing boards. this is
470 * for boards that were in the system when this driver was loaded.
471 * this function is for hot plug ADD
472 *
473 * returns 0 if success
474 * if disable == 1(DISABLE_CARD),
475 * it loops for all functions of the slot and disables them.
476 * else, it just get resources of the function and return.
477 */
478int pciehp_save_used_resources(struct controller *ctrl, struct pci_func *func, int disable)
479{
480 u8 cloop;
481 u8 header_type;
482 u8 secondary_bus;
483 u8 temp_byte;
484 u16 command;
485 u16 save_command;
486 u16 w_base, w_length;
487 u32 temp_register;
488 u32 save_base;
489 u32 base, length;
490 u64 base64 = 0;
491 int index = 0;
492 unsigned int devfn;
493 struct pci_resource *mem_node = NULL;
494 struct pci_resource *p_mem_node = NULL;
495 struct pci_resource *t_mem_node;
496 struct pci_resource *io_node;
497 struct pci_resource *bus_node;
498 struct pci_bus lpci_bus, *pci_bus;
499 memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
500 pci_bus = &lpci_bus;
501
502 if (disable)
503 func = pciehp_slot_find(func->bus, func->device, index++);
504
505 while ((func != NULL) && func->is_a_board) {
506 pci_bus->number = func->bus;
507 devfn = PCI_DEVFN(func->device, func->function);
508
509 /* Save the command register */
510 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
511
512 if (disable) {
513 /* disable card */
514 command = 0x00;
515 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
516 }
517
518 /* Check for Bridge */
519 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
520
521 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
522 dbg("Save_used_res of PCI bridge b:d=0x%x:%x, sc=0x%x\n",
523 func->bus, func->device, save_command);
524 if (disable) {
525 /* Clear Bridge Control Register */
526 command = 0x00;
527 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
528 }
529
530 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
531 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
532
533 bus_node = kmalloc(sizeof(struct pci_resource),
534 GFP_KERNEL);
535 if (!bus_node)
536 return -ENOMEM;
537
538 bus_node->base = (ulong)secondary_bus;
539 bus_node->length = (ulong)(temp_byte - secondary_bus + 1);
540
541 bus_node->next = func->bus_head;
542 func->bus_head = bus_node;
543
544 /* Save IO base and Limit registers */
545 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &temp_byte);
546 base = temp_byte;
547 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &temp_byte);
548 length = temp_byte;
549
550 if ((base <= length) && (!disable || (save_command & PCI_COMMAND_IO))) {
551 io_node = kmalloc(sizeof(struct pci_resource),
552 GFP_KERNEL);
553 if (!io_node)
554 return -ENOMEM;
555
556 io_node->base = (ulong)(base & PCI_IO_RANGE_MASK) << 8;
557 io_node->length = (ulong)(length - base + 0x10) << 8;
558
559 io_node->next = func->io_head;
560 func->io_head = io_node;
561 }
562
563 /* Save memory base and Limit registers */
564 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
565 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
566
567 if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
568 mem_node = kmalloc(sizeof(struct pci_resource),
569 GFP_KERNEL);
570 if (!mem_node)
571 return -ENOMEM;
572
573 mem_node->base = (ulong)w_base << 16;
574 mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
575
576 mem_node->next = func->mem_head;
577 func->mem_head = mem_node;
578 }
579 /* Save prefetchable memory base and Limit registers */
580 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
581 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
582
583 if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
584 p_mem_node = kmalloc(sizeof(struct pci_resource),
585 GFP_KERNEL);
586 if (!p_mem_node)
587 return -ENOMEM;
588
589 p_mem_node->base = (ulong)w_base << 16;
590 p_mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
591
592 p_mem_node->next = func->p_mem_head;
593 func->p_mem_head = p_mem_node;
594 }
595 } else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
596 dbg("Save_used_res of PCI adapter b:d=0x%x:%x, sc=0x%x\n",
597 func->bus, func->device, save_command);
598
599 /* Figure out IO and memory base lengths */
600 for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
601 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
602
603 temp_register = 0xFFFFFFFF;
604 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
605 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
606
607 if (!disable)
608 pci_bus_write_config_dword(pci_bus, devfn, cloop, save_base);
609
610 if (!temp_register)
611 continue;
612
613 base = temp_register;
614
615 if ((base & PCI_BASE_ADDRESS_SPACE_IO) &&
616 (!disable || (save_command & PCI_COMMAND_IO))) {
617 /* IO base */
618 /* set temp_register = amount of IO space requested */
619 base = base & 0xFFFFFFFCL;
620 base = (~base) + 1;
621
622 io_node = kmalloc(sizeof (struct pci_resource),
623 GFP_KERNEL);
624 if (!io_node)
625 return -ENOMEM;
626
627 io_node->base = (ulong)save_base & PCI_BASE_ADDRESS_IO_MASK;
628 io_node->length = (ulong)base;
629 dbg("sur adapter: IO bar=0x%x(length=0x%x)\n",
630 io_node->base, io_node->length);
631
632 io_node->next = func->io_head;
633 func->io_head = io_node;
634 } else { /* map Memory */
635 int prefetchable = 1;
636 /* struct pci_resources **res_node; */
637 char *res_type_str = "PMEM";
638 u32 temp_register2;
639
640 t_mem_node = kmalloc(sizeof (struct pci_resource),
641 GFP_KERNEL);
642 if (!t_mem_node)
643 return -ENOMEM;
644
645 if (!(base & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
646 (!disable || (save_command & PCI_COMMAND_MEMORY))) {
647 prefetchable = 0;
648 mem_node = t_mem_node;
649 res_type_str++;
650 } else
651 p_mem_node = t_mem_node;
652
653 base = base & 0xFFFFFFF0L;
654 base = (~base) + 1;
655
656 switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
657 case PCI_BASE_ADDRESS_MEM_TYPE_32:
658 if (prefetchable) {
659 p_mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
660 p_mem_node->length = (ulong)base;
661 dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
662 res_type_str,
663 p_mem_node->base,
664 p_mem_node->length);
665
666 p_mem_node->next = func->p_mem_head;
667 func->p_mem_head = p_mem_node;
668 } else {
669 mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
670 mem_node->length = (ulong)base;
671 dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
672 res_type_str,
673 mem_node->base,
674 mem_node->length);
675
676 mem_node->next = func->mem_head;
677 func->mem_head = mem_node;
678 }
679 break;
680 case PCI_BASE_ADDRESS_MEM_TYPE_64:
681 pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
682 base64 = temp_register2;
683 base64 = (base64 << 32) | save_base;
684
685 if (temp_register2) {
686 dbg("sur adapter: 64 %s high dword of base64(0x%x:%x) masked to 0\n",
687 res_type_str, temp_register2, (u32)base64);
688 base64 &= 0x00000000FFFFFFFFL;
689 }
690
691 if (prefetchable) {
692 p_mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
693 p_mem_node->length = base;
694 dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
695 res_type_str,
696 p_mem_node->base,
697 p_mem_node->length);
698
699 p_mem_node->next = func->p_mem_head;
700 func->p_mem_head = p_mem_node;
701 } else {
702 mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
703 mem_node->length = base;
704 dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
705 res_type_str,
706 mem_node->base,
707 mem_node->length);
708
709 mem_node->next = func->mem_head;
710 func->mem_head = mem_node;
711 }
712 cloop += 4;
713 break;
714 default:
715 dbg("asur: reserved BAR type=0x%x\n",
716 temp_register);
717 break;
718 }
719 }
720 } /* End of base register loop */
721 } else { /* Some other unknown header type */
722 dbg("Save_used_res of PCI unknown type b:d=0x%x:%x. skip.\n",
723 func->bus, func->device);
724 }
725
726 /* find the next device in this slot */
727 if (!disable)
728 break;
729 func = pciehp_slot_find(func->bus, func->device, index++);
730 }
731
732 return 0;
733}
734
735
736/**
737 * kfree_resource_list: release memory of all list members
738 * @res: resource list to free
739 */
740static inline void
741return_resource_list(struct pci_resource **func, struct pci_resource **res)
742{
743 struct pci_resource *node;
744 struct pci_resource *t_node;
745
746 node = *func;
747 *func = NULL;
748 while (node) {
749 t_node = node->next;
750 return_resource(res, node);
751 node = t_node;
752 }
753}
754
755/*
756 * pciehp_return_board_resources
757 *
758 * this routine returns all resources allocated to a board to
759 * the available pool.
760 *
761 * returns 0 if success
762 */
763int pciehp_return_board_resources(struct pci_func * func,
764 struct resource_lists * resources)
765{
766 int rc;
767
768 dbg("%s\n", __FUNCTION__);
769
770 if (!func)
771 return 1;
772
773 return_resource_list(&(func->io_head),&(resources->io_head));
774 return_resource_list(&(func->mem_head),&(resources->mem_head));
775 return_resource_list(&(func->p_mem_head),&(resources->p_mem_head));
776 return_resource_list(&(func->bus_head),&(resources->bus_head));
777
778 rc = pciehp_resource_sort_and_combine(&(resources->mem_head));
779 rc |= pciehp_resource_sort_and_combine(&(resources->p_mem_head));
780 rc |= pciehp_resource_sort_and_combine(&(resources->io_head));
781 rc |= pciehp_resource_sort_and_combine(&(resources->bus_head));
782
783 return rc;
784}
785
786/**
787 * kfree_resource_list: release memory of all list members
788 * @res: resource list to free
789 */
790static inline void
791kfree_resource_list(struct pci_resource **r)
792{
793 struct pci_resource *res, *tres;
794
795 res = *r;
796 *r = NULL;
797
798 while (res) {
799 tres = res;
800 res = res->next;
801 kfree(tres);
802 }
803}
804
805/**
806 * pciehp_destroy_resource_list: put node back in the resource list
807 * @resources: list to put nodes back
808 */
809void pciehp_destroy_resource_list(struct resource_lists * resources)
810{
811 kfree_resource_list(&(resources->io_head));
812 kfree_resource_list(&(resources->mem_head));
813 kfree_resource_list(&(resources->p_mem_head));
814 kfree_resource_list(&(resources->bus_head));
815}
816
817/**
818 * pciehp_destroy_board_resources: put node back in the resource list
819 * @resources: list to put nodes back
820 */
821void pciehp_destroy_board_resources(struct pci_func * func)
822{
823 kfree_resource_list(&(func->io_head));
824 kfree_resource_list(&(func->mem_head));
825 kfree_resource_list(&(func->p_mem_head));
826 kfree_resource_list(&(func->bus_head));
827}
diff --git a/drivers/pci/hotplug/pciehprm.h b/drivers/pci/hotplug/pciehprm.h
deleted file mode 100644
index 05f20fbc5f50..000000000000
--- a/drivers/pci/hotplug/pciehprm.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * PCIEHPRM : PCIEHP Resource Manager for ACPI/non-ACPI platform
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001,2003 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29
30#ifndef _PCIEHPRM_H_
31#define _PCIEHPRM_H_
32
33#ifdef CONFIG_HOTPLUG_PCI_PCIE_PHPRM_NONACPI
34#include "pciehprm_nonacpi.h"
35#endif
36
37int pciehprm_init(enum php_ctlr_type ct);
38void pciehprm_cleanup(void);
39int pciehprm_print_pirt(void);
40int pciehprm_find_available_resources(struct controller *ctrl);
41int pciehprm_set_hpp(struct controller *ctrl, struct pci_func *func, u8 card_type);
42void pciehprm_enable_card(struct controller *ctrl, struct pci_func *func, u8 card_type);
43
44#ifdef DEBUG
45#define RES_CHECK(this, bits) \
46 { if (((this) & (bits - 1))) \
47 printk("%s:%d ERR: potential res loss!\n", __FUNCTION__, __LINE__); }
48#else
49#define RES_CHECK(this, bits)
50#endif
51
52#endif /* _PCIEHPRM_H_ */
diff --git a/drivers/pci/hotplug/pciehprm_acpi.c b/drivers/pci/hotplug/pciehprm_acpi.c
index 1406db35b089..ae244e218620 100644
--- a/drivers/pci/hotplug/pciehprm_acpi.c
+++ b/drivers/pci/hotplug/pciehprm_acpi.c
@@ -24,100 +24,20 @@
24 * 24 *
25 */ 25 */
26 26
27#include <linux/config.h>
28#include <linux/module.h> 27#include <linux/module.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
30#include <linux/types.h> 29#include <linux/types.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/init.h>
33#include <linux/acpi.h> 31#include <linux/acpi.h>
34#include <linux/efi.h>
35#include <linux/pci-acpi.h> 32#include <linux/pci-acpi.h>
36#include <asm/uaccess.h>
37#include <asm/system.h>
38#ifdef CONFIG_IA64
39#include <asm/iosapic.h>
40#endif
41#include <acpi/acpi.h>
42#include <acpi/acpi_bus.h> 33#include <acpi/acpi_bus.h>
43#include <acpi/actypes.h> 34#include <acpi/actypes.h>
44#include "pciehp.h" 35#include "pciehp.h"
45#include "pciehprm.h"
46
47#define PCI_MAX_BUS 0x100
48#define ACPI_STA_DEVICE_PRESENT 0x01
49 36
50#define METHOD_NAME__SUN "_SUN" 37#define METHOD_NAME__SUN "_SUN"
51#define METHOD_NAME__HPP "_HPP" 38#define METHOD_NAME__HPP "_HPP"
52#define METHOD_NAME_OSHP "OSHP" 39#define METHOD_NAME_OSHP "OSHP"
53 40
54/* Status code for running acpi method to gain native control */
55#define NC_NOT_RUN 0
56#define OSC_NOT_EXIST 1
57#define OSC_RUN_FAILED 2
58#define OSHP_NOT_EXIST 3
59#define OSHP_RUN_FAILED 4
60#define NC_RUN_SUCCESS 5
61
62#define PHP_RES_BUS 0xA0
63#define PHP_RES_IO 0xA1
64#define PHP_RES_MEM 0xA2
65#define PHP_RES_PMEM 0xA3
66
67#define BRIDGE_TYPE_P2P 0x00
68#define BRIDGE_TYPE_HOST 0x01
69
70/* this should go to drivers/acpi/include/ */
71struct acpi__hpp {
72 u8 cache_line_size;
73 u8 latency_timer;
74 u8 enable_serr;
75 u8 enable_perr;
76};
77
78struct acpi_php_slot {
79 struct acpi_php_slot *next;
80 struct acpi_bridge *bridge;
81 acpi_handle handle;
82 int seg;
83 int bus;
84 int dev;
85 int fun;
86 u32 sun;
87 struct pci_resource *mem_head;
88 struct pci_resource *p_mem_head;
89 struct pci_resource *io_head;
90 struct pci_resource *bus_head;
91 void *slot_ops; /* _STA, _EJx, etc */
92 struct slot *slot;
93}; /* per func */
94
95struct acpi_bridge {
96 struct acpi_bridge *parent;
97 struct acpi_bridge *next;
98 struct acpi_bridge *child;
99 acpi_handle handle;
100 int seg;
101 int pbus; /* pdev->bus->number */
102 int pdevice; /* PCI_SLOT(pdev->devfn) */
103 int pfunction; /* PCI_DEVFN(pdev->devfn) */
104 int bus; /* pdev->subordinate->number */
105 struct acpi__hpp *_hpp;
106 struct acpi_php_slot *slots;
107 struct pci_resource *tmem_head; /* total from crs */
108 struct pci_resource *tp_mem_head; /* total from crs */
109 struct pci_resource *tio_head; /* total from crs */
110 struct pci_resource *tbus_head; /* total from crs */
111 struct pci_resource *mem_head; /* available */
112 struct pci_resource *p_mem_head; /* available */
113 struct pci_resource *io_head; /* available */
114 struct pci_resource *bus_head; /* available */
115 int scanned;
116 int type;
117};
118
119static struct acpi_bridge *acpi_bridges_head;
120
121static u8 * acpi_path_name( acpi_handle handle) 41static u8 * acpi_path_name( acpi_handle handle)
122{ 42{
123 acpi_status status; 43 acpi_status status;
@@ -133,85 +53,43 @@ static u8 * acpi_path_name( acpi_handle handle)
133 return path_name; 53 return path_name;
134} 54}
135 55
136static void acpi_get__hpp ( struct acpi_bridge *ab); 56static acpi_status
137static int acpi_run_oshp ( struct acpi_bridge *ab); 57acpi_run_hpp(acpi_handle handle, struct hotplug_params *hpp)
138static int osc_run_status = NC_NOT_RUN;
139static int oshp_run_status = NC_NOT_RUN;
140
141static int acpi_add_slot_to_php_slots(
142 struct acpi_bridge *ab,
143 int bus_num,
144 acpi_handle handle,
145 u32 adr,
146 u32 sun
147 )
148{
149 struct acpi_php_slot *aps;
150 static long samesun = -1;
151
152 aps = (struct acpi_php_slot *) kmalloc (sizeof(struct acpi_php_slot), GFP_KERNEL);
153 if (!aps) {
154 err ("acpi_pciehprm: alloc for aps fail\n");
155 return -1;
156 }
157 memset(aps, 0, sizeof(struct acpi_php_slot));
158
159 aps->handle = handle;
160 aps->bus = bus_num;
161 aps->dev = (adr >> 16) & 0xffff;
162 aps->fun = adr & 0xffff;
163 aps->sun = sun;
164
165 aps->next = ab->slots; /* cling to the bridge */
166 aps->bridge = ab;
167 ab->slots = aps;
168
169 ab->scanned += 1;
170 if (!ab->_hpp)
171 acpi_get__hpp(ab);
172
173 if (osc_run_status == OSC_NOT_EXIST)
174 oshp_run_status = acpi_run_oshp(ab);
175
176 if (sun != samesun) {
177 info("acpi_pciehprm: Slot sun(%x) at s:b:d:f=0x%02x:%02x:%02x:%02x\n",
178 aps->sun, ab->seg, aps->bus, aps->dev, aps->fun);
179 samesun = sun;
180 }
181 return 0;
182}
183
184static void acpi_get__hpp ( struct acpi_bridge *ab)
185{ 58{
186 acpi_status status; 59 acpi_status status;
187 u8 nui[4]; 60 u8 nui[4];
188 struct acpi_buffer ret_buf = { 0, NULL}; 61 struct acpi_buffer ret_buf = { 0, NULL};
189 union acpi_object *ext_obj, *package; 62 union acpi_object *ext_obj, *package;
190 u8 *path_name = acpi_path_name(ab->handle); 63 u8 *path_name = acpi_path_name(handle);
191 int i, len = 0; 64 int i, len = 0;
192 65
193 /* get _hpp */ 66 /* get _hpp */
194 status = acpi_evaluate_object(ab->handle, METHOD_NAME__HPP, NULL, &ret_buf); 67 status = acpi_evaluate_object(handle, METHOD_NAME__HPP, NULL, &ret_buf);
195 switch (status) { 68 switch (status) {
196 case AE_BUFFER_OVERFLOW: 69 case AE_BUFFER_OVERFLOW:
197 ret_buf.pointer = kmalloc (ret_buf.length, GFP_KERNEL); 70 ret_buf.pointer = kmalloc (ret_buf.length, GFP_KERNEL);
198 if (!ret_buf.pointer) { 71 if (!ret_buf.pointer) {
199 err ("acpi_pciehprm:%s alloc for _HPP fail\n", path_name); 72 err ("%s:%s alloc for _HPP fail\n", __FUNCTION__,
200 return; 73 path_name);
74 return AE_NO_MEMORY;
201 } 75 }
202 status = acpi_evaluate_object(ab->handle, METHOD_NAME__HPP, NULL, &ret_buf); 76 status = acpi_evaluate_object(handle, METHOD_NAME__HPP,
77 NULL, &ret_buf);
203 if (ACPI_SUCCESS(status)) 78 if (ACPI_SUCCESS(status))
204 break; 79 break;
205 default: 80 default:
206 if (ACPI_FAILURE(status)) { 81 if (ACPI_FAILURE(status)) {
207 err("acpi_pciehprm:%s _HPP fail=0x%x\n", path_name, status); 82 dbg("%s:%s _HPP fail=0x%x\n", __FUNCTION__,
208 return; 83 path_name, status);
84 return status;
209 } 85 }
210 } 86 }
211 87
212 ext_obj = (union acpi_object *) ret_buf.pointer; 88 ext_obj = (union acpi_object *) ret_buf.pointer;
213 if (ext_obj->type != ACPI_TYPE_PACKAGE) { 89 if (ext_obj->type != ACPI_TYPE_PACKAGE) {
214 err ("acpi_pciehprm:%s _HPP obj not a package\n", path_name); 90 err ("%s:%s _HPP obj not a package\n", __FUNCTION__,
91 path_name);
92 status = AE_ERROR;
215 goto free_and_return; 93 goto free_and_return;
216 } 94 }
217 95
@@ -224,1514 +102,153 @@ static void acpi_get__hpp ( struct acpi_bridge *ab)
224 nui[i] = (u8)ext_obj->integer.value; 102 nui[i] = (u8)ext_obj->integer.value;
225 break; 103 break;
226 default: 104 default:
227 err ("acpi_pciehprm:%s _HPP obj type incorrect\n", path_name); 105 err ("%s:%s _HPP obj type incorrect\n", __FUNCTION__,
106 path_name);
107 status = AE_ERROR;
228 goto free_and_return; 108 goto free_and_return;
229 } 109 }
230 } 110 }
231 111
232 ab->_hpp = kmalloc (sizeof (struct acpi__hpp), GFP_KERNEL); 112 hpp->cache_line_size = nui[0];
233 if (!ab->_hpp) { 113 hpp->latency_timer = nui[1];
234 err ("acpi_pciehprm:%s alloc for _HPP failed\n", path_name); 114 hpp->enable_serr = nui[2];
235 goto free_and_return; 115 hpp->enable_perr = nui[3];
236 }
237 memset(ab->_hpp, 0, sizeof(struct acpi__hpp));
238 116
239 ab->_hpp->cache_line_size = nui[0]; 117 dbg(" _HPP: cache_line_size=0x%x\n", hpp->cache_line_size);
240 ab->_hpp->latency_timer = nui[1]; 118 dbg(" _HPP: latency timer =0x%x\n", hpp->latency_timer);
241 ab->_hpp->enable_serr = nui[2]; 119 dbg(" _HPP: enable SERR =0x%x\n", hpp->enable_serr);
242 ab->_hpp->enable_perr = nui[3]; 120 dbg(" _HPP: enable PERR =0x%x\n", hpp->enable_perr);
243
244 dbg(" _HPP: cache_line_size=0x%x\n", ab->_hpp->cache_line_size);
245 dbg(" _HPP: latency timer =0x%x\n", ab->_hpp->latency_timer);
246 dbg(" _HPP: enable SERR =0x%x\n", ab->_hpp->enable_serr);
247 dbg(" _HPP: enable PERR =0x%x\n", ab->_hpp->enable_perr);
248 121
249free_and_return: 122free_and_return:
250 kfree(ret_buf.pointer); 123 kfree(ret_buf.pointer);
124 return status;
251} 125}
252 126
253static int acpi_run_oshp ( struct acpi_bridge *ab) 127static acpi_status acpi_run_oshp(acpi_handle handle)
254{ 128{
255 acpi_status status; 129 acpi_status status;
256 u8 *path_name = acpi_path_name(ab->handle); 130 u8 *path_name = acpi_path_name(handle);
257 131
258 /* run OSHP */ 132 /* run OSHP */
259 status = acpi_evaluate_object(ab->handle, METHOD_NAME_OSHP, NULL, NULL); 133 status = acpi_evaluate_object(handle, METHOD_NAME_OSHP, NULL, NULL);
260 if (ACPI_FAILURE(status)) { 134 if (ACPI_FAILURE(status)) {
261 err("acpi_pciehprm:%s OSHP fails=0x%x\n", path_name, status); 135 dbg("%s:%s OSHP fails=0x%x\n", __FUNCTION__, path_name,
262 oshp_run_status = (status == AE_NOT_FOUND) ? OSHP_NOT_EXIST : OSHP_RUN_FAILED; 136 status);
263 } else { 137 } else {
264 oshp_run_status = NC_RUN_SUCCESS; 138 dbg("%s:%s OSHP passes\n", __FUNCTION__, path_name);
265 dbg("acpi_pciehprm:%s OSHP passes =0x%x\n", path_name, status);
266 dbg("acpi_pciehprm:%s oshp_run_status =0x%x\n", path_name, oshp_run_status);
267 }
268 return oshp_run_status;
269}
270
271static acpi_status acpi_evaluate_crs(
272 acpi_handle handle,
273 struct acpi_resource **retbuf
274 )
275{
276 acpi_status status;
277 struct acpi_buffer crsbuf;
278 u8 *path_name = acpi_path_name(handle);
279
280 crsbuf.length = 0;
281 crsbuf.pointer = NULL;
282
283 status = acpi_get_current_resources (handle, &crsbuf);
284
285 switch (status) {
286 case AE_BUFFER_OVERFLOW:
287 break; /* found */
288 case AE_NOT_FOUND:
289 dbg("acpi_pciehprm:%s _CRS not found\n", path_name);
290 return status;
291 default:
292 err ("acpi_pciehprm:%s _CRS fail=0x%x\n", path_name, status);
293 return status;
294 } 139 }
295
296 crsbuf.pointer = kmalloc (crsbuf.length, GFP_KERNEL);
297 if (!crsbuf.pointer) {
298 err ("acpi_pciehprm: alloc %ld bytes for %s _CRS fail\n", (ulong)crsbuf.length, path_name);
299 return AE_NO_MEMORY;
300 }
301
302 status = acpi_get_current_resources (handle, &crsbuf);
303 if (ACPI_FAILURE(status)) {
304 err("acpi_pciehprm: %s _CRS fail=0x%x.\n", path_name, status);
305 kfree(crsbuf.pointer);
306 return status;
307 }
308
309 *retbuf = crsbuf.pointer;
310
311 return status; 140 return status;
312} 141}
313 142
314static void free_pci_resource ( struct pci_resource *aprh) 143static int is_root_bridge(acpi_handle handle)
315{ 144{
316 struct pci_resource *res, *next; 145 acpi_status status;
146 struct acpi_device_info *info;
147 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
148 int i;
317 149
318 for (res = aprh; res; res = next) { 150 status = acpi_get_object_info(handle, &buffer);
319 next = res->next; 151 if (ACPI_SUCCESS(status)) {
320 kfree(res); 152 info = buffer.pointer;
321 } 153 if ((info->valid & ACPI_VALID_HID) &&
322} 154 !strcmp(PCI_ROOT_HID_STRING,
323 155 info->hardware_id.value)) {
324static void print_pci_resource ( struct pci_resource *aprh) 156 acpi_os_free(buffer.pointer);
325{ 157 return 1;
326 struct pci_resource *res; 158 }
327 159 if (info->valid & ACPI_VALID_CID) {
328 for (res = aprh; res; res = res->next) 160 for (i=0; i < info->compatibility_id.count; i++) {
329 dbg(" base= 0x%x length= 0x%x\n", res->base, res->length); 161 if (!strcmp(PCI_ROOT_HID_STRING,
330} 162 info->compatibility_id.id[i].value)) {
331 163 acpi_os_free(buffer.pointer);
332static void print_slot_resources( struct acpi_php_slot *aps) 164 return 1;
333{ 165 }
334 if (aps->bus_head) { 166 }
335 dbg(" BUS Resources:\n");
336 print_pci_resource (aps->bus_head);
337 }
338
339 if (aps->io_head) {
340 dbg(" IO Resources:\n");
341 print_pci_resource (aps->io_head);
342 }
343
344 if (aps->mem_head) {
345 dbg(" MEM Resources:\n");
346 print_pci_resource (aps->mem_head);
347 }
348
349 if (aps->p_mem_head) {
350 dbg(" PMEM Resources:\n");
351 print_pci_resource (aps->p_mem_head);
352 }
353}
354
355static void print_pci_resources( struct acpi_bridge *ab)
356{
357 if (ab->tbus_head) {
358 dbg(" Total BUS Resources:\n");
359 print_pci_resource (ab->tbus_head);
360 }
361 if (ab->bus_head) {
362 dbg(" BUS Resources:\n");
363 print_pci_resource (ab->bus_head);
364 }
365
366 if (ab->tio_head) {
367 dbg(" Total IO Resources:\n");
368 print_pci_resource (ab->tio_head);
369 }
370 if (ab->io_head) {
371 dbg(" IO Resources:\n");
372 print_pci_resource (ab->io_head);
373 }
374
375 if (ab->tmem_head) {
376 dbg(" Total MEM Resources:\n");
377 print_pci_resource (ab->tmem_head);
378 }
379 if (ab->mem_head) {
380 dbg(" MEM Resources:\n");
381 print_pci_resource (ab->mem_head);
382 }
383
384 if (ab->tp_mem_head) {
385 dbg(" Total PMEM Resources:\n");
386 print_pci_resource (ab->tp_mem_head);
387 }
388 if (ab->p_mem_head) {
389 dbg(" PMEM Resources:\n");
390 print_pci_resource (ab->p_mem_head);
391 }
392 if (ab->_hpp) {
393 dbg(" _HPP: cache_line_size=0x%x\n", ab->_hpp->cache_line_size);
394 dbg(" _HPP: latency timer =0x%x\n", ab->_hpp->latency_timer);
395 dbg(" _HPP: enable SERR =0x%x\n", ab->_hpp->enable_serr);
396 dbg(" _HPP: enable PERR =0x%x\n", ab->_hpp->enable_perr);
397 }
398}
399
400static int pciehprm_delete_resource(
401 struct pci_resource **aprh,
402 ulong base,
403 ulong size)
404{
405 struct pci_resource *res;
406 struct pci_resource *prevnode;
407 struct pci_resource *split_node;
408 ulong tbase;
409
410 pciehp_resource_sort_and_combine(aprh);
411
412 for (res = *aprh; res; res = res->next) {
413 if (res->base > base)
414 continue;
415
416 if ((res->base + res->length) < (base + size))
417 continue;
418
419 if (res->base < base) {
420 tbase = base;
421
422 if ((res->length - (tbase - res->base)) < size)
423 continue;
424
425 split_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
426 if (!split_node)
427 return -ENOMEM;
428
429 split_node->base = res->base;
430 split_node->length = tbase - res->base;
431 res->base = tbase;
432 res->length -= split_node->length;
433
434 split_node->next = res->next;
435 res->next = split_node;
436 }
437
438 if (res->length >= size) {
439 split_node = (struct pci_resource*) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
440 if (!split_node)
441 return -ENOMEM;
442
443 split_node->base = res->base + size;
444 split_node->length = res->length - size;
445 res->length = size;
446
447 split_node->next = res->next;
448 res->next = split_node;
449 }
450
451 if (*aprh == res) {
452 *aprh = res->next;
453 } else {
454 prevnode = *aprh;
455 while (prevnode->next != res)
456 prevnode = prevnode->next;
457
458 prevnode->next = res->next;
459 }
460 res->next = NULL;
461 kfree(res);
462 break;
463 }
464
465 return 0;
466}
467
468static int pciehprm_delete_resources(
469 struct pci_resource **aprh,
470 struct pci_resource *this
471 )
472{
473 struct pci_resource *res;
474
475 for (res = this; res; res = res->next)
476 pciehprm_delete_resource(aprh, res->base, res->length);
477
478 return 0;
479}
480
481static int pciehprm_add_resource(
482 struct pci_resource **aprh,
483 ulong base,
484 ulong size)
485{
486 struct pci_resource *res;
487
488 for (res = *aprh; res; res = res->next) {
489 if ((res->base + res->length) == base) {
490 res->length += size;
491 size = 0L;
492 break;
493 } 167 }
494 if (res->next == *aprh)
495 break;
496 } 168 }
497
498 if (size) {
499 res = kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
500 if (!res) {
501 err ("acpi_pciehprm: alloc for res fail\n");
502 return -ENOMEM;
503 }
504 memset(res, 0, sizeof (struct pci_resource));
505
506 res->base = base;
507 res->length = size;
508 res->next = *aprh;
509 *aprh = res;
510 }
511
512 return 0; 169 return 0;
513} 170}
514 171
515static int pciehprm_add_resources( 172int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev)
516 struct pci_resource **aprh,
517 struct pci_resource *this
518 )
519{
520 struct pci_resource *res;
521 int rc = 0;
522
523 for (res = this; res && !rc; res = res->next)
524 rc = pciehprm_add_resource(aprh, res->base, res->length);
525
526 return rc;
527}
528
529static void acpi_parse_io (
530 struct acpi_bridge *ab,
531 union acpi_resource_data *data
532 )
533{ 173{
534 struct acpi_resource_io *dataio; 174 acpi_status status;
535 dataio = (struct acpi_resource_io *) data; 175 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
536 176 struct pci_dev *pdev = dev;
537 dbg("Io Resource\n"); 177 u8 *path_name;
538 dbg(" %d bit decode\n", ACPI_DECODE_16 == dataio->io_decode ? 16:10); 178 /*
539 dbg(" Range minimum base: %08X\n", dataio->min_base_address); 179 * Per PCI firmware specification, we should run the ACPI _OSC
540 dbg(" Range maximum base: %08X\n", dataio->max_base_address); 180 * method to get control of hotplug hardware before using it.
541 dbg(" Alignment: %08X\n", dataio->alignment); 181 * If an _OSC is missing, we look for an OSHP to do the same thing.
542 dbg(" Range Length: %08X\n", dataio->range_length); 182 * To handle different BIOS behavior, we look for _OSC and OSHP
543} 183 * within the scope of the hotplug controller and its parents, upto
544 184 * the host bridge under which this controller exists.
545static void acpi_parse_fixed_io (
546 struct acpi_bridge *ab,
547 union acpi_resource_data *data
548 )
549{
550 struct acpi_resource_fixed_io *datafio;
551 datafio = (struct acpi_resource_fixed_io *) data;
552
553 dbg("Fixed Io Resource\n");
554 dbg(" Range base address: %08X", datafio->base_address);
555 dbg(" Range length: %08X", datafio->range_length);
556}
557
558static void acpi_parse_address16_32 (
559 struct acpi_bridge *ab,
560 union acpi_resource_data *data,
561 acpi_resource_type id
562 )
563{
564 /*
565 * acpi_resource_address16 == acpi_resource_address32
566 * acpi_resource_address16 *data16 = (acpi_resource_address16 *) data;
567 */ 185 */
568 struct acpi_resource_address32 *data32 = (struct acpi_resource_address32 *) data; 186 while (!handle) {
569 struct pci_resource **aprh, **tprh; 187 /*
570 188 * This hotplug controller was not listed in the ACPI name
571 if (id == ACPI_RSTYPE_ADDRESS16) 189 * space at all. Try to get acpi handle of parent pci bus.
572 dbg("acpi_pciehprm:16-Bit Address Space Resource\n"); 190 */
573 else 191 if (!pdev || !pdev->bus->parent)
574 dbg("acpi_pciehprm:32-Bit Address Space Resource\n");
575
576 switch (data32->resource_type) {
577 case ACPI_MEMORY_RANGE:
578 dbg(" Resource Type: Memory Range\n");
579 aprh = &ab->mem_head;
580 tprh = &ab->tmem_head;
581
582 switch (data32->attribute.memory.cache_attribute) {
583 case ACPI_NON_CACHEABLE_MEMORY:
584 dbg(" Type Specific: Noncacheable memory\n");
585 break;
586 case ACPI_CACHABLE_MEMORY:
587 dbg(" Type Specific: Cacheable memory\n");
588 break;
589 case ACPI_WRITE_COMBINING_MEMORY:
590 dbg(" Type Specific: Write-combining memory\n");
591 break;
592 case ACPI_PREFETCHABLE_MEMORY:
593 aprh = &ab->p_mem_head;
594 dbg(" Type Specific: Prefetchable memory\n");
595 break;
596 default:
597 dbg(" Type Specific: Invalid cache attribute\n");
598 break; 192 break;
599 } 193 dbg("Could not find %s in acpi namespace, trying parent\n",
600 194 pci_name(pdev));
601 dbg(" Type Specific: Read%s\n", ACPI_READ_WRITE_MEMORY == data32->attribute.memory.read_write_attribute ? "/Write":" Only"); 195 if (!pdev->bus->parent->self)
602 break; 196 /* Parent must be a host bridge */
603 197 handle = acpi_get_pci_rootbridge_handle(
604 case ACPI_IO_RANGE: 198 pci_domain_nr(pdev->bus->parent),
605 dbg(" Resource Type: I/O Range\n"); 199 pdev->bus->parent->number);
606 aprh = &ab->io_head; 200 else
607 tprh = &ab->tio_head; 201 handle = DEVICE_ACPI_HANDLE(
608 202 &(pdev->bus->parent->self->dev));
609 switch (data32->attribute.io.range_attribute) { 203 pdev = pdev->bus->parent->self;
610 case ACPI_NON_ISA_ONLY_RANGES: 204 }
611 dbg(" Type Specific: Non-ISA Io Addresses\n"); 205
612 break; 206 while (handle) {
613 case ACPI_ISA_ONLY_RANGES: 207 path_name = acpi_path_name(handle);
614 dbg(" Type Specific: ISA Io Addresses\n"); 208 dbg("Trying to get hotplug control for %s \n", path_name);
615 break; 209 status = pci_osc_control_set(handle,
616 case ACPI_ENTIRE_RANGE: 210 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
617 dbg(" Type Specific: ISA and non-ISA Io Addresses\n"); 211 if (status == AE_NOT_FOUND)
618 break; 212 status = acpi_run_oshp(handle);
619 default: 213 if (ACPI_SUCCESS(status)) {
620 dbg(" Type Specific: Invalid range attribute\n"); 214 dbg("Gained control for hotplug HW for pci %s (%s)\n",
215 pci_name(dev), path_name);
216 return 0;
217 }
218 if (is_root_bridge(handle))
621 break; 219 break;
622 } 220 chandle = handle;
623 break; 221 status = acpi_get_parent(chandle, &handle);
624
625 case ACPI_BUS_NUMBER_RANGE:
626 dbg(" Resource Type: Bus Number Range(fixed)\n");
627 /* fixup to be compatible with the rest of php driver */
628 data32->min_address_range++;
629 data32->address_length--;
630 aprh = &ab->bus_head;
631 tprh = &ab->tbus_head;
632 break;
633 default:
634 dbg(" Resource Type: Invalid resource type. Exiting.\n");
635 return;
636 }
637
638 dbg(" Resource %s\n", ACPI_CONSUMER == data32->producer_consumer ? "Consumer":"Producer");
639 dbg(" %s decode\n", ACPI_SUB_DECODE == data32->decode ? "Subtractive":"Positive");
640 dbg(" Min address is %s fixed\n", ACPI_ADDRESS_FIXED == data32->min_address_fixed ? "":"not");
641 dbg(" Max address is %s fixed\n", ACPI_ADDRESS_FIXED == data32->max_address_fixed ? "":"not");
642 dbg(" Granularity: %08X\n", data32->granularity);
643 dbg(" Address range min: %08X\n", data32->min_address_range);
644 dbg(" Address range max: %08X\n", data32->max_address_range);
645 dbg(" Address translation offset: %08X\n", data32->address_translation_offset);
646 dbg(" Address Length: %08X\n", data32->address_length);
647
648 if (0xFF != data32->resource_source.index) {
649 dbg(" Resource Source Index: %X\n", data32->resource_source.index);
650 /* dbg(" Resource Source: %s\n", data32->resource_source.string_ptr); */
651 }
652
653 pciehprm_add_resource(aprh, data32->min_address_range, data32->address_length);
654}
655
656static acpi_status acpi_parse_crs(
657 struct acpi_bridge *ab,
658 struct acpi_resource *crsbuf
659 )
660{
661 acpi_status status = AE_OK;
662 struct acpi_resource *resource = crsbuf;
663 u8 count = 0;
664 u8 done = 0;
665
666 while (!done) {
667 dbg("acpi_pciehprm: PCI bus 0x%x Resource structure %x.\n", ab->bus, count++);
668 switch (resource->id) {
669 case ACPI_RSTYPE_IRQ:
670 dbg("Irq -------- Resource\n");
671 break;
672 case ACPI_RSTYPE_DMA:
673 dbg("DMA -------- Resource\n");
674 break;
675 case ACPI_RSTYPE_START_DPF:
676 dbg("Start DPF -------- Resource\n");
677 break;
678 case ACPI_RSTYPE_END_DPF:
679 dbg("End DPF -------- Resource\n");
680 break;
681 case ACPI_RSTYPE_IO:
682 acpi_parse_io (ab, &resource->data);
683 break;
684 case ACPI_RSTYPE_FIXED_IO:
685 acpi_parse_fixed_io (ab, &resource->data);
686 break;
687 case ACPI_RSTYPE_VENDOR:
688 dbg("Vendor -------- Resource\n");
689 break;
690 case ACPI_RSTYPE_END_TAG:
691 dbg("End_tag -------- Resource\n");
692 done = 1;
693 break;
694 case ACPI_RSTYPE_MEM24:
695 dbg("Mem24 -------- Resource\n");
696 break;
697 case ACPI_RSTYPE_MEM32:
698 dbg("Mem32 -------- Resource\n");
699 break;
700 case ACPI_RSTYPE_FIXED_MEM32:
701 dbg("Fixed Mem32 -------- Resource\n");
702 break;
703 case ACPI_RSTYPE_ADDRESS16:
704 acpi_parse_address16_32(ab, &resource->data, ACPI_RSTYPE_ADDRESS16);
705 break;
706 case ACPI_RSTYPE_ADDRESS32:
707 acpi_parse_address16_32(ab, &resource->data, ACPI_RSTYPE_ADDRESS32);
708 break;
709 case ACPI_RSTYPE_ADDRESS64:
710 info("Address64 -------- Resource unparsed\n");
711 break;
712 case ACPI_RSTYPE_EXT_IRQ:
713 dbg("Ext Irq -------- Resource\n");
714 break;
715 default:
716 dbg("Invalid -------- resource type 0x%x\n", resource->id);
717 break;
718 }
719
720 resource = (struct acpi_resource *) ((char *)resource + resource->length);
721 }
722
723 return status;
724}
725
726static acpi_status acpi_get_crs( struct acpi_bridge *ab)
727{
728 acpi_status status;
729 struct acpi_resource *crsbuf;
730
731 status = acpi_evaluate_crs(ab->handle, &crsbuf);
732 if (ACPI_SUCCESS(status)) {
733 status = acpi_parse_crs(ab, crsbuf);
734 kfree(crsbuf);
735
736 pciehp_resource_sort_and_combine(&ab->bus_head);
737 pciehp_resource_sort_and_combine(&ab->io_head);
738 pciehp_resource_sort_and_combine(&ab->mem_head);
739 pciehp_resource_sort_and_combine(&ab->p_mem_head);
740
741 pciehprm_add_resources (&ab->tbus_head, ab->bus_head);
742 pciehprm_add_resources (&ab->tio_head, ab->io_head);
743 pciehprm_add_resources (&ab->tmem_head, ab->mem_head);
744 pciehprm_add_resources (&ab->tp_mem_head, ab->p_mem_head);
745 }
746
747 return status;
748}
749
750/* find acpi_bridge downword from ab. */
751static struct acpi_bridge *
752find_acpi_bridge_by_bus(
753 struct acpi_bridge *ab,
754 int seg,
755 int bus /* pdev->subordinate->number */
756 )
757{
758 struct acpi_bridge *lab = NULL;
759
760 if (!ab)
761 return NULL;
762
763 if ((ab->bus == bus) && (ab->seg == seg))
764 return ab;
765
766 if (ab->child)
767 lab = find_acpi_bridge_by_bus(ab->child, seg, bus);
768
769 if (!lab)
770 if (ab->next)
771 lab = find_acpi_bridge_by_bus(ab->next, seg, bus);
772
773 return lab;
774}
775
776/*
777 * Build a device tree of ACPI PCI Bridges
778 */
779static void pciehprm_acpi_register_a_bridge (
780 struct acpi_bridge **head,
781 struct acpi_bridge *pab, /* parent bridge to which child bridge is added */
782 struct acpi_bridge *cab /* child bridge to add */
783 )
784{
785 struct acpi_bridge *lpab;
786 struct acpi_bridge *lcab;
787
788 lpab = find_acpi_bridge_by_bus(*head, pab->seg, pab->bus);
789 if (!lpab) {
790 if (!(pab->type & BRIDGE_TYPE_HOST))
791 warn("PCI parent bridge s:b(%x:%x) not in list.\n", pab->seg, pab->bus);
792 pab->next = *head;
793 *head = pab;
794 lpab = pab;
795 }
796
797 if ((cab->type & BRIDGE_TYPE_HOST) && (pab == cab))
798 return;
799
800 lcab = find_acpi_bridge_by_bus(*head, cab->seg, cab->bus);
801 if (lcab) {
802 if ((pab->bus != lcab->parent->bus) || (lcab->bus != cab->bus))
803 err("PCI child bridge s:b(%x:%x) in list with diff parent.\n", cab->seg, cab->bus);
804 return;
805 } else
806 lcab = cab;
807
808 lcab->parent = lpab;
809 lcab->next = lpab->child;
810 lpab->child = lcab;
811}
812
813static acpi_status pciehprm_acpi_build_php_slots_callback(
814 acpi_handle handle,
815 u32 Level,
816 void *context,
817 void **retval
818 )
819{
820 ulong bus_num;
821 ulong seg_num;
822 ulong sun, adr;
823 ulong padr = 0;
824 acpi_handle phandle = NULL;
825 struct acpi_bridge *pab = (struct acpi_bridge *)context;
826 struct acpi_bridge *lab;
827 acpi_status status;
828 u8 *path_name = acpi_path_name(handle);
829
830 /* get _SUN */
831 status = acpi_evaluate_integer(handle, METHOD_NAME__SUN, NULL, &sun);
832 switch(status) {
833 case AE_NOT_FOUND:
834 return AE_OK;
835 default:
836 if (ACPI_FAILURE(status)) {
837 err("acpi_pciehprm:%s _SUN fail=0x%x\n", path_name, status);
838 return status;
839 }
840 }
841
842 /* get _ADR. _ADR must exist if _SUN exists */
843 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, &adr);
844 if (ACPI_FAILURE(status)) {
845 err("acpi_pciehprm:%s _ADR fail=0x%x\n", path_name, status);
846 return status;
847 }
848
849 dbg("acpi_pciehprm:%s sun=0x%08x adr=0x%08x\n", path_name, (u32)sun, (u32)adr);
850
851 status = acpi_get_parent(handle, &phandle);
852 if (ACPI_FAILURE(status)) {
853 err("acpi_pciehprm:%s get_parent fail=0x%x\n", path_name, status);
854 return (status);
855 }
856
857 bus_num = pab->bus;
858 seg_num = pab->seg;
859
860 if (pab->bus == bus_num) {
861 lab = pab;
862 } else {
863 dbg("WARN: pab is not parent\n");
864 lab = find_acpi_bridge_by_bus(pab, seg_num, bus_num);
865 if (!lab) {
866 dbg("acpi_pciehprm: alloc new P2P bridge(%x) for sun(%08x)\n", (u32)bus_num, (u32)sun);
867 lab = (struct acpi_bridge *)kmalloc(sizeof(struct acpi_bridge), GFP_KERNEL);
868 if (!lab) {
869 err("acpi_pciehprm: alloc for ab fail\n");
870 return AE_NO_MEMORY;
871 }
872 memset(lab, 0, sizeof(struct acpi_bridge));
873
874 lab->handle = phandle;
875 lab->pbus = pab->bus;
876 lab->pdevice = (int)(padr >> 16) & 0xffff;
877 lab->pfunction = (int)(padr & 0xffff);
878 lab->bus = (int)bus_num;
879 lab->scanned = 0;
880 lab->type = BRIDGE_TYPE_P2P;
881
882 pciehprm_acpi_register_a_bridge (&acpi_bridges_head, pab, lab);
883 } else
884 dbg("acpi_pciehprm: found P2P bridge(%x) for sun(%08x)\n", (u32)bus_num, (u32)sun);
885 }
886
887 acpi_add_slot_to_php_slots(lab, (int)bus_num, handle, (u32)adr, (u32)sun);
888
889 return (status);
890}
891
892static int pciehprm_acpi_build_php_slots(
893 struct acpi_bridge *ab,
894 u32 depth
895 )
896{
897 acpi_status status;
898 u8 *path_name = acpi_path_name(ab->handle);
899
900 /* Walk down this pci bridge to get _SUNs if any behind P2P */
901 status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
902 ab->handle,
903 depth,
904 pciehprm_acpi_build_php_slots_callback,
905 ab,
906 NULL );
907 if (ACPI_FAILURE(status)) {
908 dbg("acpi_pciehprm:%s walk for _SUN on pci bridge seg:bus(%x:%x) fail=0x%x\n", path_name, ab->seg, ab->bus, status);
909 return -1;
910 }
911
912 return 0;
913}
914
915static void build_a_bridge(
916 struct acpi_bridge *pab,
917 struct acpi_bridge *ab
918 )
919{
920 u8 *path_name = acpi_path_name(ab->handle);
921
922 pciehprm_acpi_register_a_bridge (&acpi_bridges_head, pab, ab);
923
924 switch (ab->type) {
925 case BRIDGE_TYPE_HOST:
926 dbg("acpi_pciehprm: Registered PCI HOST Bridge(%02x) on s:b:d:f(%02x:%02x:%02x:%02x) [%s]\n",
927 ab->bus, ab->seg, ab->pbus, ab->pdevice, ab->pfunction, path_name);
928 break;
929 case BRIDGE_TYPE_P2P:
930 dbg("acpi_pciehprm: Registered PCI P2P Bridge(%02x-%02x) on s:b:d:f(%02x:%02x:%02x:%02x) [%s]\n",
931 ab->pbus, ab->bus, ab->seg, ab->pbus, ab->pdevice, ab->pfunction, path_name);
932 break;
933 };
934
935 /* build any immediate PHP slots under this pci bridge */
936 pciehprm_acpi_build_php_slots(ab, 1);
937}
938
939static struct acpi_bridge * add_p2p_bridge(
940 acpi_handle handle,
941 struct acpi_bridge *pab, /* parent */
942 ulong adr
943 )
944{
945 struct acpi_bridge *ab;
946 struct pci_dev *pdev;
947 ulong devnum, funcnum;
948 u8 *path_name = acpi_path_name(handle);
949
950 ab = (struct acpi_bridge *) kmalloc (sizeof(struct acpi_bridge), GFP_KERNEL);
951 if (!ab) {
952 err("acpi_pciehprm: alloc for ab fail\n");
953 return NULL;
954 }
955 memset(ab, 0, sizeof(struct acpi_bridge));
956
957 devnum = (adr >> 16) & 0xffff;
958 funcnum = adr & 0xffff;
959
960 pdev = pci_find_slot(pab->bus, PCI_DEVFN(devnum, funcnum));
961 if (!pdev || !pdev->subordinate) {
962 err("acpi_pciehprm:%s is not a P2P Bridge\n", path_name);
963 kfree(ab);
964 return NULL;
965 }
966
967 ab->handle = handle;
968 ab->seg = pab->seg;
969 ab->pbus = pab->bus; /* or pdev->bus->number */
970 ab->pdevice = devnum; /* or PCI_SLOT(pdev->devfn) */
971 ab->pfunction = funcnum; /* or PCI_FUNC(pdev->devfn) */
972 ab->bus = pdev->subordinate->number;
973 ab->scanned = 0;
974 ab->type = BRIDGE_TYPE_P2P;
975
976 dbg("acpi_pciehprm: P2P(%x-%x) on pci=b:d:f(%x:%x:%x) acpi=b:d:f(%x:%x:%x) [%s]\n",
977 pab->bus, ab->bus, pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
978 pab->bus, (u32)devnum, (u32)funcnum, path_name);
979
980 build_a_bridge(pab, ab);
981
982 return ab;
983}
984
985static acpi_status scan_p2p_bridge(
986 acpi_handle handle,
987 u32 Level,
988 void *context,
989 void **retval
990 )
991{
992 struct acpi_bridge *pab = (struct acpi_bridge *)context;
993 struct acpi_bridge *ab;
994 acpi_status status;
995 ulong adr = 0;
996 u8 *path_name = acpi_path_name(handle);
997 ulong devnum, funcnum;
998 struct pci_dev *pdev;
999
1000 /* get device, function */
1001 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, &adr);
1002 if (ACPI_FAILURE(status)) {
1003 if (status != AE_NOT_FOUND)
1004 err("acpi_pciehprm:%s _ADR fail=0x%x\n", path_name, status);
1005 return AE_OK;
1006 }
1007
1008 devnum = (adr >> 16) & 0xffff;
1009 funcnum = adr & 0xffff;
1010
1011 pdev = pci_find_slot(pab->bus, PCI_DEVFN(devnum, funcnum));
1012 if (!pdev)
1013 return AE_OK;
1014 if (!pdev->subordinate)
1015 return AE_OK;
1016
1017 ab = add_p2p_bridge(handle, pab, adr);
1018 if (ab) {
1019 status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
1020 handle,
1021 (u32)1,
1022 scan_p2p_bridge,
1023 ab,
1024 NULL);
1025 if (ACPI_FAILURE(status)) 222 if (ACPI_FAILURE(status))
1026 dbg("acpi_pciehprm:%s find_p2p fail=0x%x\n", path_name, status); 223 break;
1027 }
1028
1029 return AE_OK;
1030}
1031
1032static struct acpi_bridge * add_host_bridge(
1033 acpi_handle handle,
1034 ulong segnum,
1035 ulong busnum
1036 )
1037{
1038 ulong adr = 0;
1039 acpi_status status;
1040 struct acpi_bridge *ab;
1041 u8 *path_name = acpi_path_name(handle);
1042
1043 /* get device, function: host br adr is always 0000 though. */
1044 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, &adr);
1045 if (ACPI_FAILURE(status)) {
1046 err("acpi_pciehprm:%s _ADR fail=0x%x\n", path_name, status);
1047 return NULL;
1048 }
1049 dbg("acpi_pciehprm: ROOT PCI seg(0x%x)bus(0x%x)dev(0x%x)func(0x%x) [%s]\n", (u32)segnum,
1050 (u32)busnum, (u32)(adr >> 16) & 0xffff, (u32)adr & 0xffff, path_name);
1051
1052 ab = (struct acpi_bridge *) kmalloc (sizeof(struct acpi_bridge), GFP_KERNEL);
1053 if (!ab) {
1054 err("acpi_pciehprm: alloc for ab fail\n");
1055 return NULL;
1056 }
1057 memset(ab, 0, sizeof(struct acpi_bridge));
1058
1059 ab->handle = handle;
1060 ab->seg = (int)segnum;
1061 ab->bus = ab->pbus = (int)busnum;
1062 ab->pdevice = (int)(adr >> 16) & 0xffff;
1063 ab->pfunction = (int)(adr & 0xffff);
1064 ab->scanned = 0;
1065 ab->type = BRIDGE_TYPE_HOST;
1066
1067 /* get root pci bridge's current resources */
1068 status = acpi_get_crs(ab);
1069 if (ACPI_FAILURE(status)) {
1070 err("acpi_pciehprm:%s evaluate _CRS fail=0x%x\n", path_name, status);
1071 kfree(ab);
1072 return NULL;
1073 }
1074
1075 status = pci_osc_control_set (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1076 if (ACPI_FAILURE(status)) {
1077 err("%s: status %x\n", __FUNCTION__, status);
1078 osc_run_status = (status == AE_NOT_FOUND) ? OSC_NOT_EXIST : OSC_RUN_FAILED;
1079 } else {
1080 osc_run_status = NC_RUN_SUCCESS;
1081 }
1082 dbg("%s: osc_run_status %x\n", __FUNCTION__, osc_run_status);
1083
1084 build_a_bridge(ab, ab);
1085
1086 return ab;
1087}
1088
1089static acpi_status acpi_scan_from_root_pci_callback (
1090 acpi_handle handle,
1091 u32 Level,
1092 void *context,
1093 void **retval
1094 )
1095{
1096 ulong segnum = 0;
1097 ulong busnum = 0;
1098 acpi_status status;
1099 struct acpi_bridge *ab;
1100 u8 *path_name = acpi_path_name(handle);
1101
1102 /* get bus number of this pci root bridge */
1103 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL, &segnum);
1104 if (ACPI_FAILURE(status)) {
1105 if (status != AE_NOT_FOUND) {
1106 err("acpi_pciehprm:%s evaluate _SEG fail=0x%x\n", path_name, status);
1107 return status;
1108 }
1109 segnum = 0;
1110 }
1111
1112 /* get bus number of this pci root bridge */
1113 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN, NULL, &busnum);
1114 if (ACPI_FAILURE(status)) {
1115 err("acpi_pciehprm:%s evaluate _BBN fail=0x%x\n", path_name, status);
1116 return (status);
1117 }
1118
1119 ab = add_host_bridge(handle, segnum, busnum);
1120 if (ab) {
1121 status = acpi_walk_namespace ( ACPI_TYPE_DEVICE,
1122 handle,
1123 1,
1124 scan_p2p_bridge,
1125 ab,
1126 NULL);
1127 if (ACPI_FAILURE(status))
1128 dbg("acpi_pciehprm:%s find_p2p fail=0x%x\n", path_name, status);
1129 } 224 }
1130 225
1131 return AE_OK; 226 err("Cannot get control of hotplug hardware for pci %s\n",
227 pci_name(dev));
228 return -1;
1132} 229}
1133 230
1134static int pciehprm_acpi_scan_pci (void) 231void pciehp_get_hp_params_from_firmware(struct pci_dev *dev,
232 struct hotplug_params *hpp)
1135{ 233{
1136 acpi_status status; 234 acpi_status status = AE_NOT_FOUND;
235 struct pci_dev *pdev = dev;
1137 236
1138 /* 237 /*
1139 * TBD: traverse LDM device tree with the help of 238 * _HPP settings apply to all child buses, until another _HPP is
1140 * unified ACPI augmented for php device population. 239 * encountered. If we don't find an _HPP for the input pci dev,
240 * look for it in the parent device scope since that would apply to
241 * this pci dev. If we don't find any _HPP, use hardcoded defaults
1141 */ 242 */
1142 status = acpi_get_devices ( PCI_ROOT_HID_STRING, 243 while (pdev && (ACPI_FAILURE(status))) {
1143 acpi_scan_from_root_pci_callback, 244 acpi_handle handle = DEVICE_ACPI_HANDLE(&(pdev->dev));
1144 NULL, 245 if (!handle)
1145 NULL ); 246 break;
1146 if (ACPI_FAILURE(status)) { 247 status = acpi_run_hpp(handle, hpp);
1147 err("acpi_pciehprm:get_device PCI ROOT HID fail=0x%x\n", status); 248 if (!(pdev->bus->parent))
1148 return -1; 249 break;
1149 } 250 /* Check if a parent object supports _HPP */
1150 251 pdev = pdev->bus->parent->self;
1151 return 0;
1152}
1153
1154int pciehprm_init(enum php_ctlr_type ctlr_type)
1155{
1156 int rc;
1157
1158 if (ctlr_type != PCI)
1159 return -ENODEV;
1160
1161 dbg("pciehprm ACPI init <enter>\n");
1162 acpi_bridges_head = NULL;
1163
1164 /* construct PCI bus:device tree of acpi_handles */
1165 rc = pciehprm_acpi_scan_pci();
1166 if (rc)
1167 return rc;
1168
1169 if ((oshp_run_status != NC_RUN_SUCCESS) && (osc_run_status != NC_RUN_SUCCESS)) {
1170 err("Fails to gain control of native hot-plug\n");
1171 rc = -ENODEV;
1172 }
1173
1174 dbg("pciehprm ACPI init %s\n", (rc)?"fail":"success");
1175 return rc;
1176}
1177
1178static void free_a_slot(struct acpi_php_slot *aps)
1179{
1180 dbg(" free a php func of slot(0x%02x) on PCI b:d:f=0x%02x:%02x:%02x\n", aps->sun, aps->bus, aps->dev, aps->fun);
1181
1182 free_pci_resource (aps->io_head);
1183 free_pci_resource (aps->bus_head);
1184 free_pci_resource (aps->mem_head);
1185 free_pci_resource (aps->p_mem_head);
1186
1187 kfree(aps);
1188}
1189
1190static void free_a_bridge( struct acpi_bridge *ab)
1191{
1192 struct acpi_php_slot *aps, *next;
1193
1194 switch (ab->type) {
1195 case BRIDGE_TYPE_HOST:
1196 dbg("Free ACPI PCI HOST Bridge(%x) [%s] on s:b:d:f(%x:%x:%x:%x)\n",
1197 ab->bus, acpi_path_name(ab->handle), ab->seg, ab->pbus, ab->pdevice, ab->pfunction);
1198 break;
1199 case BRIDGE_TYPE_P2P:
1200 dbg("Free ACPI PCI P2P Bridge(%x-%x) [%s] on s:b:d:f(%x:%x:%x:%x)\n",
1201 ab->pbus, ab->bus, acpi_path_name(ab->handle), ab->seg, ab->pbus, ab->pdevice, ab->pfunction);
1202 break;
1203 };
1204
1205 /* free slots first */
1206 for (aps = ab->slots; aps; aps = next) {
1207 next = aps->next;
1208 free_a_slot(aps);
1209 }
1210
1211 free_pci_resource (ab->io_head);
1212 free_pci_resource (ab->tio_head);
1213 free_pci_resource (ab->bus_head);
1214 free_pci_resource (ab->tbus_head);
1215 free_pci_resource (ab->mem_head);
1216 free_pci_resource (ab->tmem_head);
1217 free_pci_resource (ab->p_mem_head);
1218 free_pci_resource (ab->tp_mem_head);
1219
1220 kfree(ab);
1221}
1222
1223static void pciehprm_free_bridges ( struct acpi_bridge *ab)
1224{
1225 if (!ab)
1226 return;
1227
1228 if (ab->child)
1229 pciehprm_free_bridges (ab->child);
1230
1231 if (ab->next)
1232 pciehprm_free_bridges (ab->next);
1233
1234 free_a_bridge(ab);
1235}
1236
1237void pciehprm_cleanup(void)
1238{
1239 pciehprm_free_bridges (acpi_bridges_head);
1240}
1241
1242static int get_number_of_slots (
1243 struct acpi_bridge *ab,
1244 int selfonly
1245 )
1246{
1247 struct acpi_php_slot *aps;
1248 int prev_slot = -1;
1249 int slot_num = 0;
1250
1251 for ( aps = ab->slots; aps; aps = aps->next)
1252 if (aps->dev != prev_slot) {
1253 prev_slot = aps->dev;
1254 slot_num++;
1255 }
1256
1257 if (ab->child)
1258 slot_num += get_number_of_slots (ab->child, 0);
1259
1260 if (selfonly)
1261 return slot_num;
1262
1263 if (ab->next)
1264 slot_num += get_number_of_slots (ab->next, 0);
1265
1266 return slot_num;
1267}
1268
1269static int print_acpi_resources (struct acpi_bridge *ab)
1270{
1271 struct acpi_php_slot *aps;
1272 int i;
1273
1274 switch (ab->type) {
1275 case BRIDGE_TYPE_HOST:
1276 dbg("PCI HOST Bridge (%x) [%s]\n", ab->bus, acpi_path_name(ab->handle));
1277 break;
1278 case BRIDGE_TYPE_P2P:
1279 dbg("PCI P2P Bridge (%x-%x) [%s]\n", ab->pbus, ab->bus, acpi_path_name(ab->handle));
1280 break;
1281 };
1282
1283 print_pci_resources (ab);
1284
1285 for ( i = -1, aps = ab->slots; aps; aps = aps->next) {
1286 if (aps->dev == i)
1287 continue;
1288 dbg(" Slot sun(%x) s:b:d:f(%02x:%02x:%02x:%02x)\n", aps->sun, aps->seg, aps->bus, aps->dev, aps->fun);
1289 print_slot_resources(aps);
1290 i = aps->dev;
1291 }
1292
1293 if (ab->child)
1294 print_acpi_resources (ab->child);
1295
1296 if (ab->next)
1297 print_acpi_resources (ab->next);
1298
1299 return 0;
1300}
1301
1302int pciehprm_print_pirt(void)
1303{
1304 dbg("PCIEHPRM ACPI Slots\n");
1305 if (acpi_bridges_head)
1306 print_acpi_resources (acpi_bridges_head);
1307
1308 return 0;
1309}
1310
1311static struct acpi_php_slot * get_acpi_slot (
1312 struct acpi_bridge *ab,
1313 u32 sun
1314 )
1315{
1316 struct acpi_php_slot *aps = NULL;
1317
1318 for ( aps = ab->slots; aps; aps = aps->next)
1319 if (aps->sun == sun)
1320 return aps;
1321
1322 if (!aps && ab->child) {
1323 aps = (struct acpi_php_slot *)get_acpi_slot (ab->child, sun);
1324 if (aps)
1325 return aps;
1326 }
1327
1328 if (!aps && ab->next) {
1329 aps = (struct acpi_php_slot *)get_acpi_slot (ab->next, sun);
1330 if (aps)
1331 return aps;
1332 }
1333
1334 return aps;
1335
1336}
1337
1338#if 0
1339void * pciehprm_get_slot(struct slot *slot)
1340{
1341 struct acpi_bridge *ab = acpi_bridges_head;
1342 struct acpi_php_slot *aps = get_acpi_slot (ab, slot->number);
1343
1344 aps->slot = slot;
1345
1346 dbg("Got acpi slot sun(%x): s:b:d:f(%x:%x:%x:%x)\n", aps->sun, aps->seg, aps->bus, aps->dev, aps->fun);
1347
1348 return (void *)aps;
1349}
1350#endif
1351
1352static void pciehprm_dump_func_res( struct pci_func *fun)
1353{
1354 struct pci_func *func = fun;
1355
1356 if (func->bus_head) {
1357 dbg(": BUS Resources:\n");
1358 print_pci_resource (func->bus_head);
1359 }
1360 if (func->io_head) {
1361 dbg(": IO Resources:\n");
1362 print_pci_resource (func->io_head);
1363 }
1364 if (func->mem_head) {
1365 dbg(": MEM Resources:\n");
1366 print_pci_resource (func->mem_head);
1367 }
1368 if (func->p_mem_head) {
1369 dbg(": PMEM Resources:\n");
1370 print_pci_resource (func->p_mem_head);
1371 }
1372}
1373
1374static void pciehprm_dump_ctrl_res( struct controller *ctlr)
1375{
1376 struct controller *ctrl = ctlr;
1377
1378 if (ctrl->bus_head) {
1379 dbg(": BUS Resources:\n");
1380 print_pci_resource (ctrl->bus_head);
1381 }
1382 if (ctrl->io_head) {
1383 dbg(": IO Resources:\n");
1384 print_pci_resource (ctrl->io_head);
1385 }
1386 if (ctrl->mem_head) {
1387 dbg(": MEM Resources:\n");
1388 print_pci_resource (ctrl->mem_head);
1389 }
1390 if (ctrl->p_mem_head) {
1391 dbg(": PMEM Resources:\n");
1392 print_pci_resource (ctrl->p_mem_head);
1393 }
1394}
1395
1396static int pciehprm_get_used_resources (
1397 struct controller *ctrl,
1398 struct pci_func *func
1399 )
1400{
1401 return pciehp_save_used_resources (ctrl, func, !DISABLE_CARD);
1402}
1403
1404static int configure_existing_function(
1405 struct controller *ctrl,
1406 struct pci_func *func
1407 )
1408{
1409 int rc;
1410
1411 /* see how much resources the func has used. */
1412 rc = pciehprm_get_used_resources (ctrl, func);
1413
1414 if (!rc) {
1415 /* subtract the resources used by the func from ctrl resources */
1416 rc = pciehprm_delete_resources (&ctrl->bus_head, func->bus_head);
1417 rc |= pciehprm_delete_resources (&ctrl->io_head, func->io_head);
1418 rc |= pciehprm_delete_resources (&ctrl->mem_head, func->mem_head);
1419 rc |= pciehprm_delete_resources (&ctrl->p_mem_head, func->p_mem_head);
1420 if (rc)
1421 warn("aCEF: cannot del used resources\n");
1422 } else
1423 err("aCEF: cannot get used resources\n");
1424
1425 return rc;
1426}
1427
1428static int bind_pci_resources_to_slots ( struct controller *ctrl)
1429{
1430 struct pci_func *func, new_func;
1431 int busn = ctrl->slot_bus;
1432 int devn, funn;
1433 u32 vid;
1434
1435 for (devn = 0; devn < 32; devn++) {
1436 for (funn = 0; funn < 8; funn++) {
1437 /*
1438 if (devn == ctrl->device && funn == ctrl->function)
1439 continue;
1440 */
1441 /* find out if this entry is for an occupied slot */
1442 vid = 0xFFFFFFFF;
1443 pci_bus_read_config_dword(ctrl->pci_dev->subordinate, PCI_DEVFN(devn, funn), PCI_VENDOR_ID, &vid);
1444
1445 if (vid != 0xFFFFFFFF) {
1446 dbg("%s: vid = %x\n", __FUNCTION__, vid);
1447 func = pciehp_slot_find(busn, devn, funn);
1448 if (!func) {
1449 memset(&new_func, 0, sizeof(struct pci_func));
1450 new_func.bus = busn;
1451 new_func.device = devn;
1452 new_func.function = funn;
1453 new_func.is_a_board = 1;
1454 configure_existing_function(ctrl, &new_func);
1455 pciehprm_dump_func_res(&new_func);
1456 } else {
1457 configure_existing_function(ctrl, func);
1458 pciehprm_dump_func_res(func);
1459 }
1460 dbg("aCCF:existing PCI 0x%x Func ResourceDump\n", ctrl->bus);
1461 }
1462 }
1463 }
1464
1465 return 0;
1466}
1467
1468static int bind_pci_resources(
1469 struct controller *ctrl,
1470 struct acpi_bridge *ab
1471 )
1472{
1473 int status = 0;
1474
1475 if (ab->bus_head) {
1476 dbg("bapr: BUS Resources add on PCI 0x%x\n", ab->bus);
1477 status = pciehprm_add_resources (&ctrl->bus_head, ab->bus_head);
1478 if (pciehprm_delete_resources (&ab->bus_head, ctrl->bus_head))
1479 warn("bapr: cannot sub BUS Resource on PCI 0x%x\n", ab->bus);
1480 if (status) {
1481 err("bapr: BUS Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1482 return status;
1483 }
1484 } else
1485 info("bapr: No BUS Resource on PCI 0x%x.\n", ab->bus);
1486
1487 if (ab->io_head) {
1488 dbg("bapr: IO Resources add on PCI 0x%x\n", ab->bus);
1489 status = pciehprm_add_resources (&ctrl->io_head, ab->io_head);
1490 if (pciehprm_delete_resources (&ab->io_head, ctrl->io_head))
1491 warn("bapr: cannot sub IO Resource on PCI 0x%x\n", ab->bus);
1492 if (status) {
1493 err("bapr: IO Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1494 return status;
1495 }
1496 } else
1497 info("bapr: No IO Resource on PCI 0x%x.\n", ab->bus);
1498
1499 if (ab->mem_head) {
1500 dbg("bapr: MEM Resources add on PCI 0x%x\n", ab->bus);
1501 status = pciehprm_add_resources (&ctrl->mem_head, ab->mem_head);
1502 if (pciehprm_delete_resources (&ab->mem_head, ctrl->mem_head))
1503 warn("bapr: cannot sub MEM Resource on PCI 0x%x\n", ab->bus);
1504 if (status) {
1505 err("bapr: MEM Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1506 return status;
1507 }
1508 } else
1509 info("bapr: No MEM Resource on PCI 0x%x.\n", ab->bus);
1510
1511 if (ab->p_mem_head) {
1512 dbg("bapr: PMEM Resources add on PCI 0x%x\n", ab->bus);
1513 status = pciehprm_add_resources (&ctrl->p_mem_head, ab->p_mem_head);
1514 if (pciehprm_delete_resources (&ab->p_mem_head, ctrl->p_mem_head))
1515 warn("bapr: cannot sub PMEM Resource on PCI 0x%x\n", ab->bus);
1516 if (status) {
1517 err("bapr: PMEM Resource add on PCI 0x%x: fail=0x%x\n", ab->bus, status);
1518 return status;
1519 }
1520 } else
1521 info("bapr: No PMEM Resource on PCI 0x%x.\n", ab->bus);
1522
1523 return status;
1524}
1525
1526static int no_pci_resources( struct acpi_bridge *ab)
1527{
1528 return !(ab->p_mem_head || ab->mem_head || ab->io_head || ab->bus_head);
1529}
1530
1531static int find_pci_bridge_resources (
1532 struct controller *ctrl,
1533 struct acpi_bridge *ab
1534 )
1535{
1536 int rc = 0;
1537 struct pci_func func;
1538
1539 memset(&func, 0, sizeof(struct pci_func));
1540
1541 func.bus = ab->pbus;
1542 func.device = ab->pdevice;
1543 func.function = ab->pfunction;
1544 func.is_a_board = 1;
1545
1546 /* Get used resources for this PCI bridge */
1547 rc = pciehp_save_used_resources (ctrl, &func, !DISABLE_CARD);
1548
1549 ab->io_head = func.io_head;
1550 ab->mem_head = func.mem_head;
1551 ab->p_mem_head = func.p_mem_head;
1552 ab->bus_head = func.bus_head;
1553 if (ab->bus_head)
1554 pciehprm_delete_resource(&ab->bus_head, ctrl->pci_dev->subordinate->number, 1);
1555
1556 return rc;
1557}
1558
1559static int get_pci_resources_from_bridge(
1560 struct controller *ctrl,
1561 struct acpi_bridge *ab
1562 )
1563{
1564 int rc = 0;
1565
1566 dbg("grfb: Get Resources for PCI 0x%x from actual PCI bridge 0x%x.\n", ctrl->bus, ab->bus);
1567
1568 rc = find_pci_bridge_resources (ctrl, ab);
1569
1570 pciehp_resource_sort_and_combine(&ab->bus_head);
1571 pciehp_resource_sort_and_combine(&ab->io_head);
1572 pciehp_resource_sort_and_combine(&ab->mem_head);
1573 pciehp_resource_sort_and_combine(&ab->p_mem_head);
1574
1575 pciehprm_add_resources (&ab->tbus_head, ab->bus_head);
1576 pciehprm_add_resources (&ab->tio_head, ab->io_head);
1577 pciehprm_add_resources (&ab->tmem_head, ab->mem_head);
1578 pciehprm_add_resources (&ab->tp_mem_head, ab->p_mem_head);
1579
1580 return rc;
1581}
1582
1583static int get_pci_resources(
1584 struct controller *ctrl,
1585 struct acpi_bridge *ab
1586 )
1587{
1588 int rc = 0;
1589
1590 if (no_pci_resources(ab)) {
1591 dbg("spbr:PCI 0x%x has no resources. Get parent resources.\n", ab->bus);
1592 rc = get_pci_resources_from_bridge(ctrl, ab);
1593 }
1594
1595 return rc;
1596}
1597
1598/*
1599 * Get resources for this ctrl.
1600 * 1. get total resources from ACPI _CRS or bridge (this ctrl)
1601 * 2. find used resources of existing adapters
1602 * 3. subtract used resources from total resources
1603 */
1604int pciehprm_find_available_resources( struct controller *ctrl)
1605{
1606 int rc = 0;
1607 struct acpi_bridge *ab;
1608
1609 ab = find_acpi_bridge_by_bus(acpi_bridges_head, ctrl->seg, ctrl->pci_dev->subordinate->number);
1610 if (!ab) {
1611 err("pfar:cannot locate acpi bridge of PCI 0x%x.\n", ctrl->pci_dev->subordinate->number);
1612 return -1;
1613 }
1614 if (no_pci_resources(ab)) {
1615 rc = get_pci_resources(ctrl, ab);
1616 if (rc) {
1617 err("pfar:cannot get pci resources of PCI 0x%x.\n", ctrl->pci_dev->subordinate->number);
1618 return -1;
1619 }
1620 }
1621
1622 rc = bind_pci_resources(ctrl, ab);
1623 dbg("pfar:pre-Bind PCI 0x%x Ctrl Resource Dump\n", ctrl->pci_dev->subordinate->number);
1624 pciehprm_dump_ctrl_res(ctrl);
1625
1626 bind_pci_resources_to_slots (ctrl);
1627
1628 dbg("pfar:post-Bind PCI 0x%x Ctrl Resource Dump\n", ctrl->pci_dev->subordinate->number);
1629 pciehprm_dump_ctrl_res(ctrl);
1630
1631 return rc;
1632}
1633
1634int pciehprm_set_hpp(
1635 struct controller *ctrl,
1636 struct pci_func *func,
1637 u8 card_type
1638 )
1639{
1640 struct acpi_bridge *ab;
1641 struct pci_bus lpci_bus, *pci_bus;
1642 int rc = 0;
1643 unsigned int devfn;
1644 u8 cls= 0x08; /* default cache line size */
1645 u8 lt = 0x40; /* default latency timer */
1646 u8 ep = 0;
1647 u8 es = 0;
1648
1649 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
1650 pci_bus = &lpci_bus;
1651 pci_bus->number = func->bus;
1652 devfn = PCI_DEVFN(func->device, func->function);
1653
1654 ab = find_acpi_bridge_by_bus(acpi_bridges_head, ctrl->seg, ctrl->bus);
1655
1656 if (ab) {
1657 if (ab->_hpp) {
1658 lt = (u8)ab->_hpp->latency_timer;
1659 cls = (u8)ab->_hpp->cache_line_size;
1660 ep = (u8)ab->_hpp->enable_perr;
1661 es = (u8)ab->_hpp->enable_serr;
1662 } else
1663 dbg("_hpp: no _hpp for B/D/F=%#x/%#x/%#x. use default value\n", func->bus, func->device, func->function);
1664 } else
1665 dbg("_hpp: no acpi bridge for B/D/F = %#x/%#x/%#x. use default value\n", func->bus, func->device, func->function);
1666
1667
1668 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
1669 /* set subordinate Latency Timer */
1670 rc |= pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, lt);
1671 } 252 }
1672
1673 /* set base Latency Timer */
1674 rc |= pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, lt);
1675 dbg(" set latency timer =0x%02x: %x\n", lt, rc);
1676
1677 rc |= pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, cls);
1678 dbg(" set cache_line_size=0x%02x: %x\n", cls, rc);
1679
1680 return rc;
1681} 253}
1682 254
1683void pciehprm_enable_card(
1684 struct controller *ctrl,
1685 struct pci_func *func,
1686 u8 card_type)
1687{
1688 u16 command, cmd, bcommand, bcmd;
1689 struct pci_bus lpci_bus, *pci_bus;
1690 struct acpi_bridge *ab;
1691 unsigned int devfn;
1692 int rc;
1693
1694 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
1695 pci_bus = &lpci_bus;
1696 pci_bus->number = func->bus;
1697 devfn = PCI_DEVFN(func->device, func->function);
1698
1699 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &cmd);
1700
1701 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
1702 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcmd);
1703 }
1704
1705 command = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
1706 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
1707 bcommand = bcmd | PCI_BRIDGE_CTL_NO_ISA;
1708
1709 ab = find_acpi_bridge_by_bus(acpi_bridges_head, ctrl->seg, ctrl->bus);
1710 if (ab) {
1711 if (ab->_hpp) {
1712 if (ab->_hpp->enable_perr) {
1713 command |= PCI_COMMAND_PARITY;
1714 bcommand |= PCI_BRIDGE_CTL_PARITY;
1715 } else {
1716 command &= ~PCI_COMMAND_PARITY;
1717 bcommand &= ~PCI_BRIDGE_CTL_PARITY;
1718 }
1719 if (ab->_hpp->enable_serr) {
1720 command |= PCI_COMMAND_SERR;
1721 bcommand |= PCI_BRIDGE_CTL_SERR;
1722 } else {
1723 command &= ~PCI_COMMAND_SERR;
1724 bcommand &= ~PCI_BRIDGE_CTL_SERR;
1725 }
1726 } else
1727 dbg("no _hpp for B/D/F = %#x/%#x/%#x.\n", func->bus, func->device, func->function);
1728 } else
1729 dbg("no acpi bridge for B/D/F = %#x/%#x/%#x.\n", func->bus, func->device, func->function);
1730
1731 if (command != cmd) {
1732 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
1733 }
1734 if ((card_type == PCI_HEADER_TYPE_BRIDGE) && (bcommand != bcmd)) {
1735 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
1736 }
1737}
diff --git a/drivers/pci/hotplug/pciehprm_nonacpi.c b/drivers/pci/hotplug/pciehprm_nonacpi.c
index 76c727c74cc0..29180dfe8493 100644
--- a/drivers/pci/hotplug/pciehprm_nonacpi.c
+++ b/drivers/pci/hotplug/pciehprm_nonacpi.c
@@ -27,479 +27,21 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/config.h>
31#include <linux/module.h> 30#include <linux/module.h>
32#include <linux/kernel.h> 31#include <linux/kernel.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/sched.h> 33#include <linux/sched.h>
35#include <linux/pci.h> 34#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/slab.h> 35#include <linux/slab.h>
38
39#include <asm/uaccess.h>
40#ifdef CONFIG_IA64
41#include <asm/iosapic.h>
42#endif
43
44#include "pciehp.h" 36#include "pciehp.h"
45#include "pciehprm.h"
46#include "pciehprm_nonacpi.h"
47
48 37
49void pciehprm_cleanup(void) 38void pciehp_get_hp_params_from_firmware(struct pci_dev *dev,
39 struct hotplug_params *hpp)
50{ 40{
51 return; 41 return;
52} 42}
53 43
54int pciehprm_print_pirt(void) 44int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev)
55{
56 return 0;
57}
58
59int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
60{
61
62 *sun = (u8) (ctrl->first_slot);
63 return 0;
64}
65
66
67static void print_pci_resource ( struct pci_resource *aprh)
68{
69 struct pci_resource *res;
70
71 for (res = aprh; res; res = res->next)
72 dbg(" base= 0x%x length= 0x%x\n", res->base, res->length);
73}
74
75
76static void phprm_dump_func_res( struct pci_func *fun)
77{
78 struct pci_func *func = fun;
79
80 if (func->bus_head) {
81 dbg(": BUS Resources:\n");
82 print_pci_resource (func->bus_head);
83 }
84 if (func->io_head) {
85 dbg(": IO Resources:\n");
86 print_pci_resource (func->io_head);
87 }
88 if (func->mem_head) {
89 dbg(": MEM Resources:\n");
90 print_pci_resource (func->mem_head);
91 }
92 if (func->p_mem_head) {
93 dbg(": PMEM Resources:\n");
94 print_pci_resource (func->p_mem_head);
95 }
96}
97
98static int phprm_get_used_resources (
99 struct controller *ctrl,
100 struct pci_func *func
101 )
102{
103 return pciehp_save_used_resources (ctrl, func, !DISABLE_CARD);
104}
105
106static int phprm_delete_resource(
107 struct pci_resource **aprh,
108 ulong base,
109 ulong size)
110{
111 struct pci_resource *res;
112 struct pci_resource *prevnode;
113 struct pci_resource *split_node;
114 ulong tbase;
115
116 pciehp_resource_sort_and_combine(aprh);
117
118 for (res = *aprh; res; res = res->next) {
119 if (res->base > base)
120 continue;
121
122 if ((res->base + res->length) < (base + size))
123 continue;
124
125 if (res->base < base) {
126 tbase = base;
127
128 if ((res->length - (tbase - res->base)) < size)
129 continue;
130
131 split_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
132 if (!split_node)
133 return -ENOMEM;
134
135 split_node->base = res->base;
136 split_node->length = tbase - res->base;
137 res->base = tbase;
138 res->length -= split_node->length;
139
140 split_node->next = res->next;
141 res->next = split_node;
142 }
143
144 if (res->length >= size) {
145 split_node = (struct pci_resource*) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
146 if (!split_node)
147 return -ENOMEM;
148
149 split_node->base = res->base + size;
150 split_node->length = res->length - size;
151 res->length = size;
152
153 split_node->next = res->next;
154 res->next = split_node;
155 }
156
157 if (*aprh == res) {
158 *aprh = res->next;
159 } else {
160 prevnode = *aprh;
161 while (prevnode->next != res)
162 prevnode = prevnode->next;
163
164 prevnode->next = res->next;
165 }
166 res->next = NULL;
167 kfree(res);
168 break;
169 }
170
171 return 0;
172}
173
174
175static int phprm_delete_resources(
176 struct pci_resource **aprh,
177 struct pci_resource *this
178 )
179{
180 struct pci_resource *res;
181
182 for (res = this; res; res = res->next)
183 phprm_delete_resource(aprh, res->base, res->length);
184
185 return 0;
186}
187
188
189static int configure_existing_function(
190 struct controller *ctrl,
191 struct pci_func *func
192 )
193{
194 int rc;
195
196 /* see how much resources the func has used. */
197 rc = phprm_get_used_resources (ctrl, func);
198
199 if (!rc) {
200 /* subtract the resources used by the func from ctrl resources */
201 rc = phprm_delete_resources (&ctrl->bus_head, func->bus_head);
202 rc |= phprm_delete_resources (&ctrl->io_head, func->io_head);
203 rc |= phprm_delete_resources (&ctrl->mem_head, func->mem_head);
204 rc |= phprm_delete_resources (&ctrl->p_mem_head, func->p_mem_head);
205 if (rc)
206 warn("aCEF: cannot del used resources\n");
207 } else
208 err("aCEF: cannot get used resources\n");
209
210 return rc;
211}
212
213static int pciehprm_delete_resource(
214 struct pci_resource **aprh,
215 ulong base,
216 ulong size)
217{
218 struct pci_resource *res;
219 struct pci_resource *prevnode;
220 struct pci_resource *split_node;
221 ulong tbase;
222
223 pciehp_resource_sort_and_combine(aprh);
224
225 for (res = *aprh; res; res = res->next) {
226 if (res->base > base)
227 continue;
228
229 if ((res->base + res->length) < (base + size))
230 continue;
231
232 if (res->base < base) {
233 tbase = base;
234
235 if ((res->length - (tbase - res->base)) < size)
236 continue;
237
238 split_node = (struct pci_resource *) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
239 if (!split_node)
240 return -ENOMEM;
241
242 split_node->base = res->base;
243 split_node->length = tbase - res->base;
244 res->base = tbase;
245 res->length -= split_node->length;
246
247 split_node->next = res->next;
248 res->next = split_node;
249 }
250
251 if (res->length >= size) {
252 split_node = (struct pci_resource*) kmalloc(sizeof(struct pci_resource), GFP_KERNEL);
253 if (!split_node)
254 return -ENOMEM;
255
256 split_node->base = res->base + size;
257 split_node->length = res->length - size;
258 res->length = size;
259
260 split_node->next = res->next;
261 res->next = split_node;
262 }
263
264 if (*aprh == res) {
265 *aprh = res->next;
266 } else {
267 prevnode = *aprh;
268 while (prevnode->next != res)
269 prevnode = prevnode->next;
270
271 prevnode->next = res->next;
272 }
273 res->next = NULL;
274 kfree(res);
275 break;
276 }
277
278 return 0;
279}
280
281static int bind_pci_resources_to_slots ( struct controller *ctrl)
282{ 45{
283 struct pci_func *func, new_func;
284 int busn = ctrl->slot_bus;
285 int devn, funn;
286 u32 vid;
287
288 for (devn = 0; devn < 32; devn++) {
289 for (funn = 0; funn < 8; funn++) {
290 /*
291 if (devn == ctrl->device && funn == ctrl->function)
292 continue;
293 */
294 /* find out if this entry is for an occupied slot */
295 vid = 0xFFFFFFFF;
296
297 pci_bus_read_config_dword(ctrl->pci_dev->subordinate, PCI_DEVFN(devn, funn), PCI_VENDOR_ID, &vid);
298
299 if (vid != 0xFFFFFFFF) {
300 dbg("%s: vid = %x bus %x dev %x fun %x\n", __FUNCTION__,
301 vid, busn, devn, funn);
302 func = pciehp_slot_find(busn, devn, funn);
303 dbg("%s: func = %p\n", __FUNCTION__,func);
304 if (!func) {
305 memset(&new_func, 0, sizeof(struct pci_func));
306 new_func.bus = busn;
307 new_func.device = devn;
308 new_func.function = funn;
309 new_func.is_a_board = 1;
310 configure_existing_function(ctrl, &new_func);
311 phprm_dump_func_res(&new_func);
312 } else {
313 configure_existing_function(ctrl, func);
314 phprm_dump_func_res(func);
315 }
316 dbg("aCCF:existing PCI 0x%x Func ResourceDump\n", ctrl->bus);
317 }
318 }
319 }
320
321 return 0; 46 return 0;
322} 47}
323
324static void phprm_dump_ctrl_res( struct controller *ctlr)
325{
326 struct controller *ctrl = ctlr;
327
328 if (ctrl->bus_head) {
329 dbg(": BUS Resources:\n");
330 print_pci_resource (ctrl->bus_head);
331 }
332 if (ctrl->io_head) {
333 dbg(": IO Resources:\n");
334 print_pci_resource (ctrl->io_head);
335 }
336 if (ctrl->mem_head) {
337 dbg(": MEM Resources:\n");
338 print_pci_resource (ctrl->mem_head);
339 }
340 if (ctrl->p_mem_head) {
341 dbg(": PMEM Resources:\n");
342 print_pci_resource (ctrl->p_mem_head);
343 }
344}
345
346/*
347 * phprm_find_available_resources
348 *
349 * Finds available memory, IO, and IRQ resources for programming
350 * devices which may be added to the system
351 * this function is for hot plug ADD!
352 *
353 * returns 0 if success
354 */
355int pciehprm_find_available_resources(struct controller *ctrl)
356{
357 struct pci_func func;
358 u32 rc;
359
360 memset(&func, 0, sizeof(struct pci_func));
361
362 func.bus = ctrl->bus;
363 func.device = ctrl->device;
364 func.function = ctrl->function;
365 func.is_a_board = 1;
366
367 /* Get resources for this PCI bridge */
368 rc = pciehp_save_used_resources (ctrl, &func, !DISABLE_CARD);
369 dbg("%s: pciehp_save_used_resources rc = %d\n", __FUNCTION__, rc);
370
371 if (func.mem_head)
372 func.mem_head->next = ctrl->mem_head;
373 ctrl->mem_head = func.mem_head;
374
375 if (func.p_mem_head)
376 func.p_mem_head->next = ctrl->p_mem_head;
377 ctrl->p_mem_head = func.p_mem_head;
378
379 if (func.io_head)
380 func.io_head->next = ctrl->io_head;
381 ctrl->io_head = func.io_head;
382
383 if(func.bus_head)
384 func.bus_head->next = ctrl->bus_head;
385 ctrl->bus_head = func.bus_head;
386
387 if (ctrl->bus_head)
388 pciehprm_delete_resource(&ctrl->bus_head, ctrl->pci_dev->subordinate->number, 1);
389
390 dbg("%s:pre-Bind PCI 0x%x Ctrl Resource Dump\n", __FUNCTION__, ctrl->bus);
391 phprm_dump_ctrl_res(ctrl);
392
393 dbg("%s: before bind_pci_resources_to slots\n", __FUNCTION__);
394
395 bind_pci_resources_to_slots (ctrl);
396
397 dbg("%s:post-Bind PCI 0x%x Ctrl Resource Dump\n", __FUNCTION__, ctrl->bus);
398 phprm_dump_ctrl_res(ctrl);
399
400 return (rc);
401}
402
403int pciehprm_set_hpp(
404 struct controller *ctrl,
405 struct pci_func *func,
406 u8 card_type)
407{
408 u32 rc;
409 u8 temp_byte;
410 struct pci_bus lpci_bus, *pci_bus;
411 unsigned int devfn;
412 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
413 pci_bus = &lpci_bus;
414 pci_bus->number = func->bus;
415 devfn = PCI_DEVFN(func->device, func->function);
416
417 temp_byte = 0x40; /* hard coded value for LT */
418 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
419 /* set subordinate Latency Timer */
420 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
421
422 if (rc) {
423 dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__,
424 func->bus, func->device, func->function);
425 return rc;
426 }
427 }
428
429 /* set base Latency Timer */
430 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
431
432 if (rc) {
433 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
434 return rc;
435 }
436
437 /* set Cache Line size */
438 temp_byte = 0x08; /* hard coded value for CLS */
439
440 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
441
442 if (rc) {
443 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
444 }
445
446 /* set enable_perr */
447 /* set enable_serr */
448
449 return rc;
450}
451
452void pciehprm_enable_card(
453 struct controller *ctrl,
454 struct pci_func *func,
455 u8 card_type)
456{
457 u16 command, bcommand;
458 struct pci_bus lpci_bus, *pci_bus;
459 unsigned int devfn;
460 int rc;
461
462 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
463 pci_bus = &lpci_bus;
464 pci_bus->number = func->bus;
465 devfn = PCI_DEVFN(func->device, func->function);
466
467 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
468
469 command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
470 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
471 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
472
473 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
474
475 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
476
477 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
478
479 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
480 | PCI_BRIDGE_CTL_NO_ISA;
481
482 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
483 }
484}
485
486static int legacy_pciehprm_init_pci(void)
487{
488 return 0;
489}
490
491int pciehprm_init(enum php_ctlr_type ctrl_type)
492{
493 int retval;
494
495 switch (ctrl_type) {
496 case PCI:
497 retval = legacy_pciehprm_init_pci();
498 break;
499 default:
500 retval = -ENODEV;
501 break;
502 }
503
504 return retval;
505}
diff --git a/drivers/pci/hotplug/pciehprm_nonacpi.h b/drivers/pci/hotplug/pciehprm_nonacpi.h
deleted file mode 100644
index b10603b0e958..000000000000
--- a/drivers/pci/hotplug/pciehprm_nonacpi.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * PCIEHPRM NONACPI: PHP Resource Manager for Non-ACPI/Legacy platform
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29
30#ifndef _PCIEHPRM_NONACPI_H_
31#define _PCIEHPRM_NONACPI_H_
32
33struct irq_info {
34 u8 bus, devfn; /* bus, device and function */
35 struct {
36 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
37 u16 bitmap; /* Available IRQs */
38 } __attribute__ ((packed)) irq[4];
39 u8 slot; /* slot number, 0=onboard */
40 u8 rfu;
41} __attribute__ ((packed));
42
43struct irq_routing_table {
44 u32 signature; /* PIRQ_SIGNATURE should be here */
45 u16 version; /* PIRQ_VERSION */
46 u16 size; /* Table size in bytes */
47 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
48 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
49 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
50 u32 miniport_data; /* Crap */
51 u8 rfu[11];
52 u8 checksum; /* Modulo 256 checksum must give zero */
53 struct irq_info slots[0];
54} __attribute__ ((packed));
55
56#endif /* _PCIEHPRM_NONACPI_H_ */
diff --git a/drivers/pci/hotplug/rpadlpar_core.c b/drivers/pci/hotplug/rpadlpar_core.c
index fcb66b9a0e28..cc03609f45d0 100644
--- a/drivers/pci/hotplug/rpadlpar_core.c
+++ b/drivers/pci/hotplug/rpadlpar_core.c
@@ -134,43 +134,6 @@ static void rpadlpar_claim_one_bus(struct pci_bus *b)
134 rpadlpar_claim_one_bus(child_bus); 134 rpadlpar_claim_one_bus(child_bus);
135} 135}
136 136
137static int pci_add_secondary_bus(struct device_node *dn,
138 struct pci_dev *bridge_dev)
139{
140 struct pci_dn *pdn = dn->data;
141 struct pci_controller *hose = pdn->phb;
142 struct pci_bus *child;
143 u8 sec_busno;
144
145 /* Get busno of downstream bus */
146 pci_read_config_byte(bridge_dev, PCI_SECONDARY_BUS, &sec_busno);
147
148 /* Allocate and add to children of bridge_dev->bus */
149 child = pci_add_new_bus(bridge_dev->bus, bridge_dev, sec_busno);
150 if (!child) {
151 printk(KERN_ERR "%s: could not add secondary bus\n", __FUNCTION__);
152 return -ENOMEM;
153 }
154
155 sprintf(child->name, "PCI Bus #%02x", child->number);
156
157 /* Fixup subordinate bridge bases and resources */
158 pcibios_fixup_bus(child);
159
160 /* Claim new bus resources */
161 rpadlpar_claim_one_bus(bridge_dev->bus);
162
163 if (hose->last_busno < child->number)
164 hose->last_busno = child->number;
165
166 pdn->bussubno = child->number;
167
168 /* ioremap() for child bus, which may or may not succeed */
169 remap_bus_range(child);
170
171 return 0;
172}
173
174static struct pci_dev *dlpar_find_new_dev(struct pci_bus *parent, 137static struct pci_dev *dlpar_find_new_dev(struct pci_bus *parent,
175 struct device_node *dev_dn) 138 struct device_node *dev_dn)
176{ 139{
@@ -188,29 +151,41 @@ static struct pci_dev *dlpar_find_new_dev(struct pci_bus *parent,
188static struct pci_dev *dlpar_pci_add_bus(struct device_node *dn) 151static struct pci_dev *dlpar_pci_add_bus(struct device_node *dn)
189{ 152{
190 struct pci_dn *pdn = dn->data; 153 struct pci_dn *pdn = dn->data;
191 struct pci_controller *hose = pdn->phb; 154 struct pci_controller *phb = pdn->phb;
192 struct pci_dev *dev = NULL; 155 struct pci_dev *dev = NULL;
193 156
194 /* Scan phb bus for EADS device, adding new one to bus->devices */ 157 rpaphp_eeh_init_nodes(dn);
195 if (!pci_scan_single_device(hose->bus, pdn->devfn)) { 158 /* Add EADS device to PHB bus, adding new entry to bus->devices */
196 printk(KERN_ERR "%s: found no device on bus\n", __FUNCTION__); 159 dev = of_create_pci_dev(dn, phb->bus, pdn->devfn);
160 if (!dev) {
161 printk(KERN_ERR "%s: failed to create pci dev for %s\n",
162 __FUNCTION__, dn->full_name);
197 return NULL; 163 return NULL;
198 } 164 }
199 165
166 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
167 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
168 of_scan_pci_bridge(dn, dev);
169
170 rpaphp_init_new_devs(dev->subordinate);
171
172 /* Claim new bus resources */
173 rpadlpar_claim_one_bus(dev->bus);
174
175 /* ioremap() for child bus, which may or may not succeed */
176 (void) remap_bus_range(dev->bus);
177
200 /* Add new devices to global lists. Register in proc, sysfs. */ 178 /* Add new devices to global lists. Register in proc, sysfs. */
201 pci_bus_add_devices(hose->bus); 179 pci_bus_add_devices(phb->bus);
202 180
203 /* Confirm new bridge dev was created */ 181 /* Confirm new bridge dev was created */
204 dev = dlpar_find_new_dev(hose->bus, dn); 182 dev = dlpar_find_new_dev(phb->bus, dn);
205 if (dev) { 183 if (dev) {
206 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { 184 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
207 printk(KERN_ERR "%s: unexpected header type %d\n", 185 printk(KERN_ERR "%s: unexpected header type %d\n",
208 __FUNCTION__, dev->hdr_type); 186 __FUNCTION__, dev->hdr_type);
209 return NULL; 187 return NULL;
210 } 188 }
211
212 if (pci_add_secondary_bus(dn, dev))
213 return NULL;
214 } 189 }
215 190
216 return dev; 191 return dev;
@@ -219,7 +194,6 @@ static struct pci_dev *dlpar_pci_add_bus(struct device_node *dn)
219static int dlpar_add_pci_slot(char *drc_name, struct device_node *dn) 194static int dlpar_add_pci_slot(char *drc_name, struct device_node *dn)
220{ 195{
221 struct pci_dev *dev; 196 struct pci_dev *dev;
222 int rc;
223 197
224 if (rpaphp_find_pci_bus(dn)) 198 if (rpaphp_find_pci_bus(dn))
225 return -EINVAL; 199 return -EINVAL;
@@ -232,15 +206,6 @@ static int dlpar_add_pci_slot(char *drc_name, struct device_node *dn)
232 return -EIO; 206 return -EIO;
233 } 207 }
234 208
235 if (dn->child) {
236 rc = rpaphp_config_pci_adapter(dev->subordinate);
237 if (rc < 0) {
238 printk(KERN_ERR "%s: unable to enable slot %s\n",
239 __FUNCTION__, drc_name);
240 return -EIO;
241 }
242 }
243
244 /* Add hotplug slot */ 209 /* Add hotplug slot */
245 if (rpaphp_add_slot(dn)) { 210 if (rpaphp_add_slot(dn)) {
246 printk(KERN_ERR "%s: unable to add hotplug slot %s\n", 211 printk(KERN_ERR "%s: unable to add hotplug slot %s\n",
@@ -306,7 +271,7 @@ static int dlpar_add_phb(char *drc_name, struct device_node *dn)
306{ 271{
307 struct pci_controller *phb; 272 struct pci_controller *phb;
308 273
309 if (PCI_DN(dn)->phb) { 274 if (PCI_DN(dn) && PCI_DN(dn)->phb) {
310 /* PHB already exists */ 275 /* PHB already exists */
311 return -EINVAL; 276 return -EINVAL;
312 } 277 }
@@ -435,6 +400,8 @@ int dlpar_remove_pci_slot(char *drc_name, struct device_node *dn)
435 __FUNCTION__, drc_name); 400 __FUNCTION__, drc_name);
436 return -EIO; 401 return -EIO;
437 } 402 }
403 } else {
404 rpaphp_unconfig_pci_adapter(bus);
438 } 405 }
439 406
440 if (unmap_bus_range(bus)) { 407 if (unmap_bus_range(bus)) {
diff --git a/drivers/pci/hotplug/rpaphp.h b/drivers/pci/hotplug/rpaphp.h
index 71ea5f9bb284..57ea71a7bda5 100644
--- a/drivers/pci/hotplug/rpaphp.h
+++ b/drivers/pci/hotplug/rpaphp.h
@@ -93,6 +93,8 @@ extern int rpaphp_claim_resource(struct pci_dev *dev, int resource);
93extern int rpaphp_enable_pci_slot(struct slot *slot); 93extern int rpaphp_enable_pci_slot(struct slot *slot);
94extern int register_pci_slot(struct slot *slot); 94extern int register_pci_slot(struct slot *slot);
95extern int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value); 95extern int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value);
96extern void rpaphp_init_new_devs(struct pci_bus *bus);
97extern void rpaphp_eeh_init_nodes(struct device_node *dn);
96 98
97extern int rpaphp_config_pci_adapter(struct pci_bus *bus); 99extern int rpaphp_config_pci_adapter(struct pci_bus *bus);
98extern int rpaphp_unconfig_pci_adapter(struct pci_bus *bus); 100extern int rpaphp_unconfig_pci_adapter(struct pci_bus *bus);
diff --git a/drivers/pci/hotplug/rpaphp_pci.c b/drivers/pci/hotplug/rpaphp_pci.c
index f7c12d7dfcfc..4b35097b3d9f 100644
--- a/drivers/pci/hotplug/rpaphp_pci.c
+++ b/drivers/pci/hotplug/rpaphp_pci.c
@@ -154,8 +154,7 @@ exit:
154} 154}
155 155
156/* Must be called before pci_bus_add_devices */ 156/* Must be called before pci_bus_add_devices */
157static void 157void rpaphp_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus)
158rpaphp_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus)
159{ 158{
160 struct pci_dev *dev; 159 struct pci_dev *dev;
161 160
@@ -184,6 +183,20 @@ rpaphp_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus)
184 } 183 }
185} 184}
186 185
186static void rpaphp_eeh_add_bus_device(struct pci_bus *bus)
187{
188 struct pci_dev *dev;
189
190 list_for_each_entry(dev, &bus->devices, bus_list) {
191 eeh_add_device_late(dev);
192 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
193 struct pci_bus *subbus = dev->subordinate;
194 if (subbus)
195 rpaphp_eeh_add_bus_device (subbus);
196 }
197 }
198}
199
187static int rpaphp_pci_config_bridge(struct pci_dev *dev) 200static int rpaphp_pci_config_bridge(struct pci_dev *dev)
188{ 201{
189 u8 sec_busno; 202 u8 sec_busno;
@@ -217,6 +230,13 @@ static int rpaphp_pci_config_bridge(struct pci_dev *dev)
217 return 0; 230 return 0;
218} 231}
219 232
233void rpaphp_init_new_devs(struct pci_bus *bus)
234{
235 rpaphp_fixup_new_pci_devices(bus, 0);
236 rpaphp_eeh_add_bus_device(bus);
237}
238EXPORT_SYMBOL_GPL(rpaphp_init_new_devs);
239
220/***************************************************************************** 240/*****************************************************************************
221 rpaphp_pci_config_slot() will configure all devices under the 241 rpaphp_pci_config_slot() will configure all devices under the
222 given slot->dn and return the the first pci_dev. 242 given slot->dn and return the the first pci_dev.
@@ -233,36 +253,51 @@ rpaphp_pci_config_slot(struct pci_bus *bus)
233 if (!dn || !dn->child) 253 if (!dn || !dn->child)
234 return NULL; 254 return NULL;
235 255
236 slotno = PCI_SLOT(PCI_DN(dn->child)->devfn); 256 if (_machine == PLATFORM_PSERIES_LPAR) {
257 of_scan_bus(dn, bus);
258 if (list_empty(&bus->devices)) {
259 err("%s: No new device found\n", __FUNCTION__);
260 return NULL;
261 }
237 262
238 /* pci_scan_slot should find all children */ 263 rpaphp_init_new_devs(bus);
239 num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
240 if (num) {
241 rpaphp_fixup_new_pci_devices(bus, 1);
242 pci_bus_add_devices(bus); 264 pci_bus_add_devices(bus);
243 } 265 dev = list_entry(&bus->devices, struct pci_dev, bus_list);
244 if (list_empty(&bus->devices)) { 266 } else {
245 err("%s: No new device found\n", __FUNCTION__); 267 slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
246 return NULL; 268
247 } 269 /* pci_scan_slot should find all children */
248 list_for_each_entry(dev, &bus->devices, bus_list) { 270 num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
249 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 271 if (num) {
250 rpaphp_pci_config_bridge(dev); 272 rpaphp_fixup_new_pci_devices(bus, 1);
273 pci_bus_add_devices(bus);
274 }
275 if (list_empty(&bus->devices)) {
276 err("%s: No new device found\n", __FUNCTION__);
277 return NULL;
278 }
279 list_for_each_entry(dev, &bus->devices, bus_list) {
280 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
281 rpaphp_pci_config_bridge(dev);
282
283 rpaphp_eeh_add_bus_device(bus);
284 }
251 } 285 }
252 286
253 return dev; 287 return dev;
254} 288}
255 289
256static void enable_eeh(struct device_node *dn) 290void rpaphp_eeh_init_nodes(struct device_node *dn)
257{ 291{
258 struct device_node *sib; 292 struct device_node *sib;
259 293
260 for (sib = dn->child; sib; sib = sib->sibling) 294 for (sib = dn->child; sib; sib = sib->sibling)
261 enable_eeh(sib); 295 rpaphp_eeh_init_nodes(sib);
262 eeh_add_device_early(dn); 296 eeh_add_device_early(dn);
263 return; 297 return;
264 298
265} 299}
300EXPORT_SYMBOL_GPL(rpaphp_eeh_init_nodes);
266 301
267static void print_slot_pci_funcs(struct pci_bus *bus) 302static void print_slot_pci_funcs(struct pci_bus *bus)
268{ 303{
@@ -289,7 +324,7 @@ int rpaphp_config_pci_adapter(struct pci_bus *bus)
289 if (!dn) 324 if (!dn)
290 goto exit; 325 goto exit;
291 326
292 enable_eeh(dn); 327 rpaphp_eeh_init_nodes(dn);
293 dev = rpaphp_pci_config_slot(bus); 328 dev = rpaphp_pci_config_slot(bus);
294 if (!dev) { 329 if (!dev) {
295 err("%s: can't find any devices.\n", __FUNCTION__); 330 err("%s: can't find any devices.\n", __FUNCTION__);
@@ -331,6 +366,7 @@ int rpaphp_unconfig_pci_adapter(struct pci_bus *bus)
331 } 366 }
332 return 0; 367 return 0;
333} 368}
369EXPORT_SYMBOL_GPL(rpaphp_unconfig_pci_adapter);
334 370
335static int setup_pci_hotplug_slot_info(struct slot *slot) 371static int setup_pci_hotplug_slot_info(struct slot *slot)
336{ 372{
@@ -444,8 +480,8 @@ int rpaphp_enable_pci_slot(struct slot *slot)
444 retval = rpaphp_config_pci_adapter(slot->bus); 480 retval = rpaphp_config_pci_adapter(slot->bus);
445 if (!retval) { 481 if (!retval) {
446 slot->state = CONFIGURED; 482 slot->state = CONFIGURED;
447 dbg("%s: PCI devices in slot[%s] has been configured\n", 483 info("%s: devices in slot[%s] configured\n",
448 __FUNCTION__, slot->name); 484 __FUNCTION__, slot->name);
449 } else { 485 } else {
450 slot->state = NOT_CONFIGURED; 486 slot->state = NOT_CONFIGURED;
451 dbg("%s: no pci_dev struct for adapter in slot[%s]\n", 487 dbg("%s: no pci_dev struct for adapter in slot[%s]\n",
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 40905a6c8094..9987a6fd65b8 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -31,6 +31,8 @@
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/pci.h> 33#include <linux/pci.h>
34#include <linux/interrupt.h>
35
34#include "shpchp.h" 36#include "shpchp.h"
35 37
36#ifdef DEBUG 38#ifdef DEBUG
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index b8e95acea3b6..38009bc0fd5d 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -34,7 +34,7 @@
34#include "../pci.h" 34#include "../pci.h"
35#include "shpchp.h" 35#include "shpchp.h"
36 36
37void program_fw_provided_values(struct pci_dev *dev) 37static void program_fw_provided_values(struct pci_dev *dev)
38{ 38{
39 u16 pci_cmd, pci_bctl; 39 u16 pci_cmd, pci_bctl;
40 struct pci_dev *cdev; 40 struct pci_dev *cdev;
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index a2033552423c..202b7507a357 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -23,6 +23,8 @@
23#include "pci.h" 23#include "pci.h"
24#include "msi.h" 24#include "msi.h"
25 25
26#define MSI_TARGET_CPU first_cpu(cpu_online_map)
27
26static DEFINE_SPINLOCK(msi_lock); 28static DEFINE_SPINLOCK(msi_lock);
27static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 29static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
28static kmem_cache_t* msi_cachep; 30static kmem_cache_t* msi_cachep;
@@ -92,6 +94,7 @@ static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
92 struct msi_desc *entry; 94 struct msi_desc *entry;
93 struct msg_address address; 95 struct msg_address address;
94 unsigned int irq = vector; 96 unsigned int irq = vector;
97 unsigned int dest_cpu = first_cpu(cpu_mask);
95 98
96 entry = (struct msi_desc *)msi_desc[vector]; 99 entry = (struct msi_desc *)msi_desc[vector];
97 if (!entry || !entry->dev) 100 if (!entry || !entry->dev)
@@ -108,9 +111,9 @@ static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
108 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), 111 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
109 &address.lo_address.value); 112 &address.lo_address.value);
110 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; 113 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
111 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) << 114 address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
112 MSI_TARGET_CPU_SHIFT); 115 MSI_TARGET_CPU_SHIFT);
113 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask); 116 entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
114 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos), 117 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
115 address.lo_address.value); 118 address.lo_address.value);
116 set_native_irq_info(irq, cpu_mask); 119 set_native_irq_info(irq, cpu_mask);
@@ -123,9 +126,9 @@ static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
123 126
124 address.lo_address.value = readl(entry->mask_base + offset); 127 address.lo_address.value = readl(entry->mask_base + offset);
125 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; 128 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
126 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) << 129 address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
127 MSI_TARGET_CPU_SHIFT); 130 MSI_TARGET_CPU_SHIFT);
128 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask); 131 entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
129 writel(address.lo_address.value, entry->mask_base + offset); 132 writel(address.lo_address.value, entry->mask_base + offset);
130 set_native_irq_info(irq, cpu_mask); 133 set_native_irq_info(irq, cpu_mask);
131 break; 134 break;
@@ -259,14 +262,15 @@ static void msi_data_init(struct msg_data *msi_data,
259static void msi_address_init(struct msg_address *msi_address) 262static void msi_address_init(struct msg_address *msi_address)
260{ 263{
261 unsigned int dest_id; 264 unsigned int dest_id;
265 unsigned long dest_phys_id = cpu_physical_id(MSI_TARGET_CPU);
262 266
263 memset(msi_address, 0, sizeof(struct msg_address)); 267 memset(msi_address, 0, sizeof(struct msg_address));
264 msi_address->hi_address = (u32)0; 268 msi_address->hi_address = (u32)0;
265 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT); 269 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
266 msi_address->lo_address.u.dest_mode = MSI_DEST_MODE; 270 msi_address->lo_address.u.dest_mode = MSI_PHYSICAL_MODE;
267 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE; 271 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
268 msi_address->lo_address.u.dest_id = dest_id; 272 msi_address->lo_address.u.dest_id = dest_id;
269 msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT); 273 msi_address->lo_address.value |= (dest_phys_id << MSI_TARGET_CPU_SHIFT);
270} 274}
271 275
272static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); 276static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index e9e37abe1f76..6917c6cb0912 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -91,9 +91,7 @@ acpi_query_osc (
91static acpi_status 91static acpi_status
92acpi_run_osc ( 92acpi_run_osc (
93 acpi_handle handle, 93 acpi_handle handle,
94 u32 level, 94 void *context)
95 void *context,
96 void **retval )
97{ 95{
98 acpi_status status; 96 acpi_status status;
99 struct acpi_object_list input; 97 struct acpi_object_list input;
@@ -180,11 +178,12 @@ EXPORT_SYMBOL(pci_osc_support_set);
180 178
181/** 179/**
182 * pci_osc_control_set - commit requested control to Firmware 180 * pci_osc_control_set - commit requested control to Firmware
181 * @handle: acpi_handle for the target ACPI object
183 * @flags: driver's requested control bits 182 * @flags: driver's requested control bits
184 * 183 *
185 * Attempt to take control from Firmware on requested control bits. 184 * Attempt to take control from Firmware on requested control bits.
186 **/ 185 **/
187acpi_status pci_osc_control_set(u32 flags) 186acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
188{ 187{
189 acpi_status status; 188 acpi_status status;
190 u32 ctrlset; 189 u32 ctrlset;
@@ -198,10 +197,7 @@ acpi_status pci_osc_control_set(u32 flags)
198 return AE_SUPPORT; 197 return AE_SUPPORT;
199 } 198 }
200 ctrlset_buf[OSC_CONTROL_TYPE] |= ctrlset; 199 ctrlset_buf[OSC_CONTROL_TYPE] |= ctrlset;
201 status = acpi_get_devices ( PCI_ROOT_HID_STRING, 200 status = acpi_run_osc(handle, ctrlset_buf);
202 acpi_run_osc,
203 ctrlset_buf,
204 NULL );
205 if (ACPI_FAILURE (status)) { 201 if (ACPI_FAILURE (status)) {
206 ctrlset_buf[OSC_CONTROL_TYPE] &= ~ctrlset; 202 ctrlset_buf[OSC_CONTROL_TYPE] &= ~ctrlset;
207 } 203 }
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 94e68c54d273..a9046d4b8af3 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -37,7 +37,7 @@ struct pci_dynid {
37 * Adds a new dynamic pci device ID to this driver, 37 * Adds a new dynamic pci device ID to this driver,
38 * and causes the driver to probe for all devices again. 38 * and causes the driver to probe for all devices again.
39 */ 39 */
40static inline ssize_t 40static ssize_t
41store_new_id(struct device_driver *driver, const char *buf, size_t count) 41store_new_id(struct device_driver *driver, const char *buf, size_t count)
42{ 42{
43 struct pci_dynid *dynid; 43 struct pci_dynid *dynid;
@@ -364,15 +364,16 @@ static struct kobj_type pci_driver_kobj_type = {
364}; 364};
365 365
366/** 366/**
367 * pci_register_driver - register a new pci driver 367 * __pci_register_driver - register a new pci driver
368 * @drv: the driver structure to register 368 * @drv: the driver structure to register
369 * @owner: owner module of drv
369 * 370 *
370 * Adds the driver structure to the list of registered drivers. 371 * Adds the driver structure to the list of registered drivers.
371 * Returns a negative value on error, otherwise 0. 372 * Returns a negative value on error, otherwise 0.
372 * If no error occurred, the driver remains registered even if 373 * If no error occurred, the driver remains registered even if
373 * no device was claimed during registration. 374 * no device was claimed during registration.
374 */ 375 */
375int pci_register_driver(struct pci_driver *drv) 376int __pci_register_driver(struct pci_driver *drv, struct module *owner)
376{ 377{
377 int error; 378 int error;
378 379
@@ -389,7 +390,7 @@ int pci_register_driver(struct pci_driver *drv)
389 printk(KERN_WARNING "Warning: PCI driver %s has a struct " 390 printk(KERN_WARNING "Warning: PCI driver %s has a struct "
390 "device_driver shutdown method, please update!\n", 391 "device_driver shutdown method, please update!\n",
391 drv->name); 392 drv->name);
392 drv->driver.owner = drv->owner; 393 drv->driver.owner = owner;
393 drv->driver.kobj.ktype = &pci_driver_kobj_type; 394 drv->driver.kobj.ktype = &pci_driver_kobj_type;
394 395
395 spin_lock_init(&drv->dynids.lock); 396 spin_lock_init(&drv->dynids.lock);
@@ -526,7 +527,7 @@ postcore_initcall(pci_driver_init);
526 527
527EXPORT_SYMBOL(pci_match_id); 528EXPORT_SYMBOL(pci_match_id);
528EXPORT_SYMBOL(pci_match_device); 529EXPORT_SYMBOL(pci_match_device);
529EXPORT_SYMBOL(pci_register_driver); 530EXPORT_SYMBOL(__pci_register_driver);
530EXPORT_SYMBOL(pci_unregister_driver); 531EXPORT_SYMBOL(pci_unregister_driver);
531EXPORT_SYMBOL(pci_dev_driver); 532EXPORT_SYMBOL(pci_dev_driver);
532EXPORT_SYMBOL(pci_bus_type); 533EXPORT_SYMBOL(pci_bus_type);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e74d75843047..8e287a828d5d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -63,11 +63,38 @@ pci_max_busnr(void)
63 return max; 63 return max;
64} 64}
65 65
66static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
67{
68 u8 id;
69 int ttl = 48;
70
71 while (ttl--) {
72 pci_bus_read_config_byte(bus, devfn, pos, &pos);
73 if (pos < 0x40)
74 break;
75 pos &= ~3;
76 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
77 &id);
78 if (id == 0xff)
79 break;
80 if (id == cap)
81 return pos;
82 pos += PCI_CAP_LIST_NEXT;
83 }
84 return 0;
85}
86
87int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
88{
89 return __pci_find_next_cap(dev->bus, dev->devfn,
90 pos + PCI_CAP_LIST_NEXT, cap);
91}
92EXPORT_SYMBOL_GPL(pci_find_next_capability);
93
66static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) 94static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
67{ 95{
68 u16 status; 96 u16 status;
69 u8 pos, id; 97 u8 pos;
70 int ttl = 48;
71 98
72 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 99 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
73 if (!(status & PCI_STATUS_CAP_LIST)) 100 if (!(status & PCI_STATUS_CAP_LIST))
@@ -76,24 +103,15 @@ static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_ty
76 switch (hdr_type) { 103 switch (hdr_type) {
77 case PCI_HEADER_TYPE_NORMAL: 104 case PCI_HEADER_TYPE_NORMAL:
78 case PCI_HEADER_TYPE_BRIDGE: 105 case PCI_HEADER_TYPE_BRIDGE:
79 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos); 106 pos = PCI_CAPABILITY_LIST;
80 break; 107 break;
81 case PCI_HEADER_TYPE_CARDBUS: 108 case PCI_HEADER_TYPE_CARDBUS:
82 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos); 109 pos = PCI_CB_CAPABILITY_LIST;
83 break; 110 break;
84 default: 111 default:
85 return 0; 112 return 0;
86 } 113 }
87 while (ttl-- && pos >= 0x40) { 114 return __pci_find_next_cap(bus, devfn, pos, cap);
88 pos &= ~3;
89 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
90 if (id == 0xff)
91 break;
92 if (id == cap)
93 return pos;
94 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
95 }
96 return 0;
97} 115}
98 116
99/** 117/**
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 5627ce1d2b32..3a4f49f4effb 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -462,11 +462,11 @@ static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
462 462
463 pci_read_config_word(dev, 0x70, &hm); 463 pci_read_config_word(dev, 0x70, &hm);
464 hm &= PCI_BASE_ADDRESS_IO_MASK; 464 hm &= PCI_BASE_ADDRESS_IO_MASK;
465 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c868 HW-mon"); 465 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
466 466
467 pci_read_config_dword(dev, 0x90, &smb); 467 pci_read_config_dword(dev, 0x90, &smb);
468 smb &= PCI_BASE_ADDRESS_IO_MASK; 468 smb &= PCI_BASE_ADDRESS_IO_MASK;
469 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c868 SMB"); 469 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
470} 470}
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
472 472
@@ -1243,6 +1243,21 @@ static void __devinit quirk_netmos(struct pci_dev *dev)
1243} 1243}
1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1245 1245
1246
1247static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1248{
1249 /* rev 1 ncr53c810 chips don't set the class at all which means
1250 * they don't get their resources remapped. Fix that here.
1251 */
1252
1253 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1254 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1255 dev->class = PCI_CLASS_STORAGE_SCSI;
1256 }
1257}
1258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1259
1260
1246static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1261static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1247{ 1262{
1248 while (f < end) { 1263 while (f < end) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 14:24:05 -0500