7 files changed, 166 insertions, 42 deletions

diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h
index f9e244da30ae..9bcb6cbd5aa9 100644
--- a/drivers/pci/hotplug/acpiphp.h
+++ b/drivers/pci/hotplug/acpiphp.h
@@ -113,7 +113,7 @@ struct acpiphp_slot {
 
         u8              device;         /* pci device# */
 
-        u32             sun;            /* ACPI _SUN (slot unique number) */
+        unsigned long long sun;         /* ACPI _SUN (slot unique number) */
         u32             flags;          /* see below */
 };
 
diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c
index 95b536a23d25..43c10bd261b4 100644
--- a/drivers/pci/hotplug/acpiphp_core.c
+++ b/drivers/pci/hotplug/acpiphp_core.c
@@ -337,7 +337,7 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot)
         slot->hotplug_slot->info->cur_bus_speed = PCI_SPEED_UNKNOWN;
 
         acpiphp_slot->slot = slot;
-        snprintf(name, SLOT_NAME_SIZE, "%u", slot->acpi_slot->sun);
+        snprintf(name, SLOT_NAME_SIZE, "%llu", slot->acpi_slot->sun);
 
         retval = pci_hp_register(slot->hotplug_slot,
                                         acpiphp_slot->bridge->pci_bus,
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 955aae4071f7..3affc6472e65 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -255,13 +255,13 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
 
                 bridge->nr_slots++;
 
-                dbg("found ACPI PCI Hotplug slot %d at PCI %04x:%02x:%02x\n",
+                dbg("found ACPI PCI Hotplug slot %llu at PCI %04x:%02x:%02x\n",
                                 slot->sun, pci_domain_nr(bridge->pci_bus),
                                 bridge->pci_bus->number, slot->device);
                 retval = acpiphp_register_hotplug_slot(slot);
                 if (retval) {
                         if (retval == -EBUSY)
-                                warn("Slot %d already registered by another "
+                                warn("Slot %llu already registered by another "
                                         "hotplug driver\n", slot->sun);
                         else
                                 warn("acpiphp_register_hotplug_slot failed "
diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c
index c892daae74d6..633e743442ac 100644
--- a/drivers/pci/hotplug/ibmphp_core.c
+++ b/drivers/pci/hotplug/ibmphp_core.c
@@ -1402,10 +1402,6 @@ static int __init ibmphp_init(void)
                 goto error;
         }
 
-        /* lock ourselves into memory with a module 
-         * count of -1 so that no one can unload us. */
-        module_put(THIS_MODULE);
-
 exit:
         return rc;
 
@@ -1423,4 +1419,3 @@ static void __exit ibmphp_exit(void)
 }
 
 module_init(ibmphp_init);
-module_exit(ibmphp_exit);
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 4b23bc39b11e..39cf248d24e3 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -432,18 +432,19 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
                 goto err_out_release_ctlr;
         }
 
+        /* Check if slot is occupied */
         t_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
-
-        t_slot->hpc_ops->get_adapter_status(t_slot, &value); /* Check if slot is occupied */
-        if (value && pciehp_force) {
-                rc = pciehp_enable_slot(t_slot);
-                if (rc) /* -ENODEV: shouldn't happen, but deal with it */
-                        value = 0;
-        }
-        if ((POWER_CTRL(ctrl)) && !value) {
-                rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/
-                if (rc)
-                        goto err_out_free_ctrl_slot;
+        t_slot->hpc_ops->get_adapter_status(t_slot, &value);
+        if (value) {
+                if (pciehp_force)
+                        pciehp_enable_slot(t_slot);
+        } else {
+                /* Power off slot if not occupied */
+                if (POWER_CTRL(ctrl)) {
+                        rc = t_slot->hpc_ops->power_off_slot(t_slot);
+                        if (rc)
+                                goto err_out_free_ctrl_slot;
+                }
         }
 
         return 0;
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index dfc63d01f20a..aac7006949f1 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -252,7 +252,7 @@ static void report_resume(struct pci_dev *dev, void *data)
 
         if (!dev->driver ||
                 !dev->driver->err_handler ||
-                !dev->driver->err_handler->slot_reset)
+                !dev->driver->err_handler->resume)
                 return;
 
         err_handler = dev->driver->err_handler;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 5f4f85f56cb7..ce0985615133 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -606,27 +606,6 @@ static void __init quirk_ioapic_rmw(struct pci_dev *dev)
                 sis_apic_bug = 1;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_ANY_ID,                     quirk_ioapic_rmw);
-
-#define AMD8131_revA0        0x01
-#define AMD8131_revB0        0x11
-#define AMD8131_MISC         0x40
-#define AMD8131_NIOAMODE_BIT 0
-static void quirk_amd_8131_ioapic(struct pci_dev *dev)
-{ 
-        unsigned char tmp;
-        
-        if (nr_ioapics == 0) 
-                return;
-
-        if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
-                dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
-                pci_read_config_byte( dev, AMD8131_MISC, &tmp);
-                tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
-                pci_write_config_byte( dev, AMD8131_MISC, tmp);
-        }
-} 
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
 #endif /* CONFIG_X86_IO_APIC */
 
 /*
@@ -1423,6 +1402,155 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260a, quirk_intel_pcie_pm);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260b, quirk_intel_pcie_pm);
 
+#ifdef CONFIG_X86_IO_APIC
+/*
+ * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
+ * remap the original interrupt in the linux kernel to the boot interrupt, so
+ * that a PCI device's interrupt handler is installed on the boot interrupt
+ * line instead.
+ */
+static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
+{
+        if (noioapicquirk || noioapicreroute)
+                return;
+
+        dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
+
+        printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
+                        dev->vendor, dev->device);
+        return;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
+
+/*
+ * On some chipsets we can disable the generation of legacy INTx boot
+ * interrupts.
+ */
+
+/*
+ * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
+ * 300641-004US, section 5.7.3.
+ */
+#define INTEL_6300_IOAPIC_ABAR          0x40
+#define INTEL_6300_DISABLE_BOOT_IRQ     (1<<14)
+
+static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
+{
+        u16 pci_config_word;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
+        pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
+        pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
+
+        printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
+                dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,      quirk_disable_intel_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,     quirk_disable_intel_boot_interrupt);
+
+/*
+ * disable boot interrupts on HT-1000
+ */
+#define BC_HT1000_FEATURE_REG           0x64
+#define BC_HT1000_PIC_REGS_ENABLE       (1<<0)
+#define BC_HT1000_MAP_IDX               0xC00
+#define BC_HT1000_MAP_DATA              0xC01
+
+static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
+{
+        u32 pci_config_dword;
+        u8 irq;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
+        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
+                        BC_HT1000_PIC_REGS_ENABLE);
+
+        for (irq = 0x10; irq < 0x10 + 32; irq++) {
+                outb(irq, BC_HT1000_MAP_IDX);
+                outb(0x00, BC_HT1000_MAP_DATA);
+        }
+
+        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
+
+        printk(KERN_INFO "disabled boot interrupts on PCI device"
+                        "0x%04x:0x%04x\n", dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,       quirk_disable_broadcom_boot_interrupt);
+
+/*
+ * disable boot interrupts on AMD and ATI chipsets
+ */
+/*
+ * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
+ * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
+ * (due to an erratum).
+ */
+#define AMD_813X_MISC                   0x40
+#define AMD_813X_NOIOAMODE              (1<<0)
+
+static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
+{
+        u32 pci_config_dword;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
+        pci_config_dword &= ~AMD_813X_NOIOAMODE;
+        pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
+
+        printk(KERN_INFO "disabled boot interrupts on PCI device "
+                        "0x%04x:0x%04x\n", dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8131_BRIDGE,     quirk_disable_amd_813x_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8132_BRIDGE,    quirk_disable_amd_813x_boot_interrupt);
+
+#define AMD_8111_PCI_IRQ_ROUTING        0x56
+
+static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
+{
+        u16 pci_config_word;
+
+        if (noioapicquirk)
+                return;
+
+        pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
+        if (!pci_config_word) {
+                printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
+                                "already disabled\n",
+                                dev->vendor, dev->device);
+                return;
+        }
+        pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
+        printk(KERN_INFO "disabled boot interrupts on PCI device "
+                        "0x%04x:0x%04x\n", dev->vendor, dev->device);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,     quirk_disable_amd_8111_boot_interrupt);
+#endif /* CONFIG_X86_IO_APIC */
+
 /*
  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.