diff options
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/intel-iommu.c | 15 | ||||
-rw-r--r-- | drivers/pci/intel-iommu.h | 15 |
2 files changed, 15 insertions, 15 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 218a1f357b4d..fb701d9dd8c0 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c | |||
@@ -49,8 +49,6 @@ | |||
49 | 49 | ||
50 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | 50 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 |
51 | 51 | ||
52 | #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */ | ||
53 | |||
54 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) | 52 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) |
55 | 53 | ||
56 | 54 | ||
@@ -486,19 +484,6 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |||
486 | return 0; | 484 | return 0; |
487 | } | 485 | } |
488 | 486 | ||
489 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ | ||
490 | {\ | ||
491 | cycles_t start_time = get_cycles();\ | ||
492 | while (1) {\ | ||
493 | sts = op (iommu->reg + offset);\ | ||
494 | if (cond)\ | ||
495 | break;\ | ||
496 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ | ||
497 | panic("DMAR hardware is malfunctioning\n");\ | ||
498 | cpu_relax();\ | ||
499 | }\ | ||
500 | } | ||
501 | |||
502 | static void iommu_set_root_entry(struct intel_iommu *iommu) | 487 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
503 | { | 488 | { |
504 | void *addr; | 489 | void *addr; |
diff --git a/drivers/pci/intel-iommu.h b/drivers/pci/intel-iommu.h index eb167e39b464..3a650e8cba33 100644 --- a/drivers/pci/intel-iommu.h +++ b/drivers/pci/intel-iommu.h | |||
@@ -177,6 +177,21 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) | |||
177 | #define dma_frcd_source_id(c) (c & 0xffff) | 177 | #define dma_frcd_source_id(c) (c & 0xffff) |
178 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ | 178 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ |
179 | 179 | ||
180 | #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */ | ||
181 | |||
182 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ | ||
183 | {\ | ||
184 | cycles_t start_time = get_cycles();\ | ||
185 | while (1) {\ | ||
186 | sts = op (iommu->reg + offset);\ | ||
187 | if (cond)\ | ||
188 | break;\ | ||
189 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ | ||
190 | panic("DMAR hardware is malfunctioning\n");\ | ||
191 | cpu_relax();\ | ||
192 | }\ | ||
193 | } | ||
194 | |||
180 | struct intel_iommu { | 195 | struct intel_iommu { |
181 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | 196 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ |
182 | u64 cap; | 197 | u64 cap; |