diff options
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/probe.c | 45 | ||||
-rw-r--r-- | drivers/pci/setup-res.c | 3 |
2 files changed, 18 insertions, 30 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3e7a00a3fc81..ef17cf99830e 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c | |||
@@ -67,21 +67,6 @@ static int __init pcibus_class_init(void) | |||
67 | } | 67 | } |
68 | postcore_initcall(pcibus_class_init); | 68 | postcore_initcall(pcibus_class_init); |
69 | 69 | ||
70 | /* | ||
71 | * Translate the low bits of the PCI base | ||
72 | * to the resource type | ||
73 | */ | ||
74 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | ||
75 | { | ||
76 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | ||
77 | return IORESOURCE_IO; | ||
78 | |||
79 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | ||
80 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | ||
81 | |||
82 | return IORESOURCE_MEM; | ||
83 | } | ||
84 | |||
85 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) | 70 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
86 | { | 71 | { |
87 | u64 size = mask & maxbase; /* Find the significant bits */ | 72 | u64 size = mask & maxbase; /* Find the significant bits */ |
@@ -100,17 +85,21 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask) | |||
100 | return size; | 85 | return size; |
101 | } | 86 | } |
102 | 87 | ||
103 | static inline enum pci_bar_type decode_bar(struct pci_dev *dev, | 88 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
104 | struct resource *res, u32 bar) | ||
105 | { | 89 | { |
106 | u32 mem_type; | 90 | u32 mem_type; |
91 | unsigned long flags; | ||
107 | 92 | ||
108 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | 93 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
109 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | 94 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
110 | return pci_bar_io; | 95 | flags |= IORESOURCE_IO; |
96 | return flags; | ||
111 | } | 97 | } |
112 | 98 | ||
113 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; | 99 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
100 | flags |= IORESOURCE_MEM; | ||
101 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | ||
102 | flags |= IORESOURCE_PREFETCH; | ||
114 | 103 | ||
115 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; | 104 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
116 | switch (mem_type) { | 105 | switch (mem_type) { |
@@ -120,14 +109,15 @@ static inline enum pci_bar_type decode_bar(struct pci_dev *dev, | |||
120 | dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); | 109 | dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); |
121 | break; | 110 | break; |
122 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | 111 | case PCI_BASE_ADDRESS_MEM_TYPE_64: |
123 | return pci_bar_mem64; | 112 | flags |= IORESOURCE_MEM_64; |
113 | break; | ||
124 | default: | 114 | default: |
125 | dev_warn(&dev->dev, | 115 | dev_warn(&dev->dev, |
126 | "mem unknown type %x treated as 32-bit BAR\n", | 116 | "mem unknown type %x treated as 32-bit BAR\n", |
127 | mem_type); | 117 | mem_type); |
128 | break; | 118 | break; |
129 | } | 119 | } |
130 | return pci_bar_mem32; | 120 | return flags; |
131 | } | 121 | } |
132 | 122 | ||
133 | /** | 123 | /** |
@@ -180,9 +170,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |||
180 | l = 0; | 170 | l = 0; |
181 | 171 | ||
182 | if (type == pci_bar_unknown) { | 172 | if (type == pci_bar_unknown) { |
183 | type = decode_bar(dev, res, l); | 173 | res->flags = decode_bar(dev, l); |
184 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | 174 | res->flags |= IORESOURCE_SIZEALIGN; |
185 | if (type == pci_bar_io) { | 175 | if (res->flags & IORESOURCE_IO) { |
186 | l &= PCI_BASE_ADDRESS_IO_MASK; | 176 | l &= PCI_BASE_ADDRESS_IO_MASK; |
187 | mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; | 177 | mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
188 | } else { | 178 | } else { |
@@ -195,7 +185,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |||
195 | mask = (u32)PCI_ROM_ADDRESS_MASK; | 185 | mask = (u32)PCI_ROM_ADDRESS_MASK; |
196 | } | 186 | } |
197 | 187 | ||
198 | if (type == pci_bar_mem64) { | 188 | if (res->flags & IORESOURCE_MEM_64) { |
199 | u64 l64 = l; | 189 | u64 l64 = l; |
200 | u64 sz64 = sz; | 190 | u64 sz64 = sz; |
201 | u64 mask64 = mask | (u64)~0 << 32; | 191 | u64 mask64 = mask | (u64)~0 << 32; |
@@ -219,7 +209,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |||
219 | goto fail; | 209 | goto fail; |
220 | } | 210 | } |
221 | 211 | ||
222 | res->flags |= IORESOURCE_MEM_64; | ||
223 | if ((sizeof(resource_size_t) < 8) && l) { | 212 | if ((sizeof(resource_size_t) < 8) && l) { |
224 | /* Address above 32-bit boundary; disable the BAR */ | 213 | /* Address above 32-bit boundary; disable the BAR */ |
225 | pci_write_config_dword(dev, pos, 0); | 214 | pci_write_config_dword(dev, pos, 0); |
@@ -245,7 +234,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |||
245 | } | 234 | } |
246 | 235 | ||
247 | out: | 236 | out: |
248 | return (type == pci_bar_mem64) ? 1 : 0; | 237 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
249 | fail: | 238 | fail: |
250 | res->flags = 0; | 239 | res->flags = 0; |
251 | goto out; | 240 | goto out; |
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index bc0e6eea0fff..319f359906e8 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c | |||
@@ -74,8 +74,7 @@ void pci_update_resource(struct pci_dev *dev, int resno) | |||
74 | resno, new, check); | 74 | resno, new, check); |
75 | } | 75 | } |
76 | 76 | ||
77 | if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == | 77 | if (res->flags & IORESOURCE_MEM_64) { |
78 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) { | ||
79 | new = region.start >> 16 >> 16; | 78 | new = region.start >> 16 >> 16; |
80 | pci_write_config_dword(dev, reg + 4, new); | 79 | pci_write_config_dword(dev, reg + 4, new); |
81 | pci_read_config_dword(dev, reg + 4, &check); | 80 | pci_read_config_dword(dev, reg + 4, &check); |