1 files changed, 182 insertions, 39 deletions

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 92b9efe9bcaf..9b2f0d96900d 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -24,6 +24,7 @@
 #include <linux/kallsyms.h>
 #include <linux/dmi.h>
 #include <linux/pci-aspm.h>
+#include <linux/ioport.h>
 #include "pci.h"
 
 int isa_dma_bridge_buggy;
@@ -34,6 +35,65 @@ int pcie_mch_quirk;
 EXPORT_SYMBOL(pcie_mch_quirk);
 
 #ifdef CONFIG_PCI_QUIRKS
+/*
+ * This quirk function disables the device and releases resources
+ * which is specified by kernel's boot parameter 'pci=resource_alignment='.
+ * It also rounds up size to specified alignment.
+ * Later on, the kernel will assign page-aligned memory resource back
+ * to that device.
+ */
+static void __devinit quirk_resource_alignment(struct pci_dev *dev)
+{
+        int i;
+        struct resource *r;
+        resource_size_t align, size;
+
+        if (!pci_is_reassigndev(dev))
+                return;
+
+        if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
+            (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
+                dev_warn(&dev->dev,
+                        "Can't reassign resources to host bridge.\n");
+                return;
+        }
+
+        dev_info(&dev->dev, "Disabling device and release resources.\n");
+        pci_disable_device(dev);
+
+        align = pci_specified_resource_alignment(dev);
+        for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
+                r = &dev->resource[i];
+                if (!(r->flags & IORESOURCE_MEM))
+                        continue;
+                size = resource_size(r);
+                if (size < align) {
+                        size = align;
+                        dev_info(&dev->dev,
+                                "Rounding up size of resource #%d to %#llx.\n",
+                                i, (unsigned long long)size);
+                }
+                r->end = size - 1;
+                r->start = 0;
+        }
+        /* Need to disable bridge's resource window,
+         * to enable the kernel to reassign new resource
+         * window later on.
+         */
+        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
+            (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
+                for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
+                        r = &dev->resource[i];
+                        if (!(r->flags & IORESOURCE_MEM))
+                                continue;
+                        r->end = resource_size(r) - 1;
+                        r->start = 0;
+                }
+                pci_disable_bridge_window(dev);
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
+
 /* The Mellanox Tavor device gives false positive parity errors
  * Mark this device with a broken_parity_status, to allow
  * PCI scanning code to "skip" this now blacklisted device.
@@ -1126,10 +1186,15 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
                                  * its on-board VGA controller */
                                 asus_hides_smbus = 1;
                         }
-                else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
+                else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
                         switch(dev->subsystem_device) {
                         case 0x00b8: /* Compaq Evo D510 CMT */
                         case 0x00b9: /* Compaq Evo D510 SFF */
+                                /* Motherboard doesn't have Host bridge
+                                 * subvendor/subdevice IDs and on-board VGA
+                                 * controller is disabled if an AGP card is
+                                 * inserted, therefore checking USB UHCI
+                                 * Controller #1 */
                                 asus_hides_smbus = 1;
                         }
                 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
@@ -1154,7 +1219,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	as
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82810_IG3,  asus_hides_smbus_hostbridge);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845G_IG,  asus_hides_smbus_hostbridge);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_2,  asus_hides_smbus_hostbridge);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82815_CGC,  asus_hides_smbus_hostbridge);
 
 static void asus_hides_smbus_lpc(struct pci_dev *dev)
@@ -1664,9 +1729,13 @@ static void __devinit quirk_netmos(struct pci_dev *dev)
          * of parallel ports and <S> is the number of serial ports.
          */
         switch (dev->device) {
+        case PCI_DEVICE_ID_NETMOS_9835:
+                /* Well, this rule doesn't hold for the following 9835 device */
+                if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
+                                dev->subsystem_device == 0x0299)
+                        return;
         case PCI_DEVICE_ID_NETMOS_9735:
         case PCI_DEVICE_ID_NETMOS_9745:
-        case PCI_DEVICE_ID_NETMOS_9835:
         case PCI_DEVICE_ID_NETMOS_9845:
         case PCI_DEVICE_ID_NETMOS_9855:
                 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
@@ -2078,6 +2147,92 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
                         PCI_DEVICE_ID_NVIDIA_NVENET_15,
                         nvenet_msi_disable);
 
+static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
+{
+        int pos, ttl = 48;
+        int found = 0;
+
+        /* check if there is HT MSI cap or enabled on this device */
+        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
+        while (pos && ttl--) {
+                u8 flags;
+
+                if (found < 1)
+                        found = 1;
+                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
+                                         &flags) == 0) {
+                        if (flags & HT_MSI_FLAGS_ENABLE) {
+                                if (found < 2) {
+                                        found = 2;
+                                        break;
+                                }
+                        }
+                }
+                pos = pci_find_next_ht_capability(dev, pos,
+                                                  HT_CAPTYPE_MSI_MAPPING);
+        }
+
+        return found;
+}
+
+static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
+{
+        struct pci_dev *dev;
+        int pos;
+        int i, dev_no;
+        int found = 0;
+
+        dev_no = host_bridge->devfn >> 3;
+        for (i = dev_no + 1; i < 0x20; i++) {
+                dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
+                if (!dev)
+                        continue;
+
+                /* found next host bridge ?*/
+                pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
+                if (pos != 0) {
+                        pci_dev_put(dev);
+                        break;
+                }
+
+                if (ht_check_msi_mapping(dev)) {
+                        found = 1;
+                        pci_dev_put(dev);
+                        break;
+                }
+                pci_dev_put(dev);
+        }
+
+        return found;
+}
+
+#define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
+#define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */
+
+static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
+{
+        int pos, ctrl_off;
+        int end = 0;
+        u16 flags, ctrl;
+
+        pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
+
+        if (!pos)
+                goto out;
+
+        pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
+
+        ctrl_off = ((flags >> 10) & 1) ?
+                        PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
+        pci_read_config_word(dev, pos + ctrl_off, &ctrl);
+
+        if (ctrl & (1 << 6))
+                end = 1;
+
+out:
+        return end;
+}
+
 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
 {
         struct pci_dev *host_bridge;
@@ -2102,6 +2257,11 @@ static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
         if (!found)
                 return;
 
+        /* don't enable end_device/host_bridge with leaf directly here */
+        if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
+            host_bridge_with_leaf(host_bridge))
+                goto out;
+
         /* root did that ! */
         if (msi_ht_cap_enabled(host_bridge))
                 goto out;
@@ -2132,44 +2292,12 @@ static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
         }
 }
 
-static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
-{
-        int pos, ttl = 48;
-        int found = 0;
-
-        /* check if there is HT MSI cap or enabled on this device */
-        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
-        while (pos && ttl--) {
-                u8 flags;
-
-                if (found < 1)
-                        found = 1;
-                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
-                                         &flags) == 0) {
-                        if (flags & HT_MSI_FLAGS_ENABLE) {
-                                if (found < 2) {
-                                        found = 2;
-                                        break;
-                                }
-                        }
-                }
-                pos = pci_find_next_ht_capability(dev, pos,
-                                                  HT_CAPTYPE_MSI_MAPPING);
-        }
-
-        return found;
-}
-
-static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
+static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
 {
         struct pci_dev *host_bridge;
         int pos;
         int found;
 
-        /* Enabling HT MSI mapping on this device breaks MCP51 */
-        if (dev->device == 0x270)
-                return;
-
         /* check if there is HT MSI cap or enabled on this device */
         found = ht_check_msi_mapping(dev);
 
@@ -2193,7 +2321,10 @@ static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
                 /* Host bridge is to HT */
                 if (found == 1) {
                         /* it is not enabled, try to enable it */
-                        nv_ht_enable_msi_mapping(dev);
+                        if (all)
+                                ht_enable_msi_mapping(dev);
+                        else
+                                nv_ht_enable_msi_mapping(dev);
                 }
                 return;
         }
@@ -2205,8 +2336,20 @@ static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
         /* Host bridge is not to HT, disable HT MSI mapping on this device */
         ht_disable_msi_mapping(dev);
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
+
+static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
+{
+        return __nv_msi_ht_cap_quirk(dev, 1);
+}
+
+static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
+{
+        return __nv_msi_ht_cap_quirk(dev, 0);
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
 
 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
 {