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path: root/drivers/pci/quirks.c
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Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index c913ea4e545c..40c1825c8b93 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1481,6 +1481,24 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1481DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1481DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1482DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1482DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1483 1483
1484/*
1485 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1486 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1487 * Re-allocate the region if needed...
1488 */
1489static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1490{
1491 struct resource *r = &dev->resource[0];
1492
1493 if (r->start & 0x8) {
1494 r->start = 0;
1495 r->end = 0xf;
1496 }
1497}
1498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1499 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1500 quirk_tc86c001_ide);
1501
1484static void __devinit quirk_netmos(struct pci_dev *dev) 1502static void __devinit quirk_netmos(struct pci_dev *dev)
1485{ 1503{
1486 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1504 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;