aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/quirks.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 0d0ba2fad5fc..11217bda4b9e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1460,6 +1460,24 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1462 1462
1463/*
1464 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1465 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1466 * Re-allocate the region if needed...
1467 */
1468static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1469{
1470 struct resource *r = &dev->resource[0];
1471
1472 if (r->start & 0x8) {
1473 r->start = 0;
1474 r->end = 0xf;
1475 }
1476}
1477DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1478 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1479 quirk_tc86c001_ide);
1480
1463static void __devinit quirk_netmos(struct pci_dev *dev) 1481static void __devinit quirk_netmos(struct pci_dev *dev)
1464{ 1482{
1465 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1483 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;