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path: root/drivers/pci/quirks.c
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Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c483
1 files changed, 281 insertions, 202 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 72e0bd5d80ac..0a953d43b9a2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/acpi.h> 23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
24#include "pci.h" 25#include "pci.h"
25 26
26/* The Mellanox Tavor device gives false positive parity errors 27/* The Mellanox Tavor device gives false positive parity errors
@@ -46,14 +47,14 @@ static void quirk_passive_release(struct pci_dev *dev)
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc); 48 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) { 49 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 50 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
50 dlc |= 1<<1; 51 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc); 52 pci_write_config_byte(d, 0x82, dlc);
52 } 53 }
53 } 54 }
54} 55}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
56DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 57DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
57 58
58/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 59/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA 60 but VIA don't answer queries. If you happen to have good contacts at VIA
@@ -68,20 +69,20 @@ static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
68{ 69{
69 if (!isa_dma_bridge_buggy) { 70 if (!isa_dma_bridge_buggy) {
70 isa_dma_bridge_buggy=1; 71 isa_dma_bridge_buggy=1;
71 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 72 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
72 } 73 }
73} 74}
74 /* 75 /*
75 * Its not totally clear which chipsets are the problematic ones 76 * Its not totally clear which chipsets are the problematic ones
76 * We know 82C586 and 82C596 variants are affected. 77 * We know 82C586 and 82C596 variants are affected.
77 */ 78 */
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 85DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
85 86
86int pci_pci_problems; 87int pci_pci_problems;
87EXPORT_SYMBOL(pci_pci_problems); 88EXPORT_SYMBOL(pci_pci_problems);
@@ -92,12 +93,12 @@ EXPORT_SYMBOL(pci_pci_problems);
92static void __devinit quirk_nopcipci(struct pci_dev *dev) 93static void __devinit quirk_nopcipci(struct pci_dev *dev)
93{ 94{
94 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 95 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
95 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 96 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
96 pci_pci_problems |= PCIPCI_FAIL; 97 pci_pci_problems |= PCIPCI_FAIL;
97 } 98 }
98} 99}
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
101 102
102static void __devinit quirk_nopciamd(struct pci_dev *dev) 103static void __devinit quirk_nopciamd(struct pci_dev *dev)
103{ 104{
@@ -105,11 +106,11 @@ static void __devinit quirk_nopciamd(struct pci_dev *dev)
105 pci_read_config_byte(dev, 0x08, &rev); 106 pci_read_config_byte(dev, 0x08, &rev);
106 if (rev == 0x13) { 107 if (rev == 0x13) {
107 /* Erratum 24 */ 108 /* Erratum 24 */
108 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); 109 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
109 pci_pci_problems |= PCIAGP_FAIL; 110 pci_pci_problems |= PCIAGP_FAIL;
110 } 111 }
111} 112}
112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd ); 113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
113 114
114/* 115/*
115 * Triton requires workarounds to be used by the drivers 116 * Triton requires workarounds to be used by the drivers
@@ -117,14 +118,14 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopci
117static void __devinit quirk_triton(struct pci_dev *dev) 118static void __devinit quirk_triton(struct pci_dev *dev)
118{ 119{
119 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 120 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
120 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 121 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
121 pci_pci_problems |= PCIPCI_TRITON; 122 pci_pci_problems |= PCIPCI_TRITON;
122 } 123 }
123} 124}
124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
128 129
129/* 130/*
130 * VIA Apollo KT133 needs PCI latency patch 131 * VIA Apollo KT133 needs PCI latency patch
@@ -139,25 +140,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quir
139static void quirk_vialatency(struct pci_dev *dev) 140static void quirk_vialatency(struct pci_dev *dev)
140{ 141{
141 struct pci_dev *p; 142 struct pci_dev *p;
142 u8 rev;
143 u8 busarb; 143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have 144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */ 145 a buggy southbridge */
146 146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) { 148 if (p!=NULL) {
149 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
150 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
151 /* Check for buggy part revisions */ 150 /* Check for buggy part revisions */
152 if (rev < 0x40 || rev > 0x42) 151 if (p->revision < 0x40 || p->revision > 0x42)
153 goto exit; 152 goto exit;
154 } else { 153 } else {
155 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
156 if (p==NULL) /* No problem parts */ 155 if (p==NULL) /* No problem parts */
157 goto exit; 156 goto exit;
158 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
159 /* Check for buggy part revisions */ 157 /* Check for buggy part revisions */
160 if (rev < 0x10 || rev > 0x12) 158 if (p->revision < 0x10 || p->revision > 0x12)
161 goto exit; 159 goto exit;
162 } 160 }
163 161
@@ -180,17 +178,17 @@ static void quirk_vialatency(struct pci_dev *dev)
180 busarb &= ~(1<<5); 178 busarb &= ~(1<<5);
181 busarb |= (1<<4); 179 busarb |= (1<<4);
182 pci_write_config_byte(dev, 0x76, busarb); 180 pci_write_config_byte(dev, 0x76, busarb);
183 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 181 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
184exit: 182exit:
185 pci_dev_put(p); 183 pci_dev_put(p);
186} 184}
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
190/* Must restore this on a resume from RAM */ 188/* Must restore this on a resume from RAM */
191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 189DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
192DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 190DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
194 192
195/* 193/*
196 * VIA Apollo VP3 needs ETBF on BT848/878 194 * VIA Apollo VP3 needs ETBF on BT848/878
@@ -198,20 +196,20 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_viala
198static void __devinit quirk_viaetbf(struct pci_dev *dev) 196static void __devinit quirk_viaetbf(struct pci_dev *dev)
199{ 197{
200 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 198 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
201 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 199 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
202 pci_pci_problems |= PCIPCI_VIAETBF; 200 pci_pci_problems |= PCIPCI_VIAETBF;
203 } 201 }
204} 202}
205DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
206 204
207static void __devinit quirk_vsfx(struct pci_dev *dev) 205static void __devinit quirk_vsfx(struct pci_dev *dev)
208{ 206{
209 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 207 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
210 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 208 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
211 pci_pci_problems |= PCIPCI_VSFX; 209 pci_pci_problems |= PCIPCI_VSFX;
212 } 210 }
213} 211}
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
215 213
216/* 214/*
217 * Ali Magik requires workarounds to be used by the drivers 215 * Ali Magik requires workarounds to be used by the drivers
@@ -222,12 +220,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx
222static void __init quirk_alimagik(struct pci_dev *dev) 220static void __init quirk_alimagik(struct pci_dev *dev)
223{ 221{
224 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 222 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
225 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 223 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
226 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 224 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
227 } 225 }
228} 226}
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
231 229
232/* 230/*
233 * Natoma has some interesting boundary conditions with Zoran stuff 231 * Natoma has some interesting boundary conditions with Zoran stuff
@@ -236,16 +234,16 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimag
236static void __devinit quirk_natoma(struct pci_dev *dev) 234static void __devinit quirk_natoma(struct pci_dev *dev)
237{ 235{
238 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 236 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
239 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
240 pci_pci_problems |= PCIPCI_NATOMA; 238 pci_pci_problems |= PCIPCI_NATOMA;
241 } 239 }
242} 240}
243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
249 247
250/* 248/*
251 * This chip can cause PCI parity errors if config register 0xA0 is read 249 * This chip can cause PCI parity errors if config register 0xA0 is read
@@ -255,7 +253,7 @@ static void __devinit quirk_citrine(struct pci_dev *dev)
255{ 253{
256 dev->cfg_size = 0xA0; 254 dev->cfg_size = 0xA0;
257} 255}
258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
259 257
260/* 258/*
261 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
@@ -270,8 +268,8 @@ static void __devinit quirk_s3_64M(struct pci_dev *dev)
270 r->end = 0x3ffffff; 268 r->end = 0x3ffffff;
271 } 269 }
272} 270}
273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
275 273
276static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 274static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
277 unsigned size, int nr, const char *name) 275 unsigned size, int nr, const char *name)
@@ -292,7 +290,7 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
292 pcibios_bus_to_resource(dev, res, &bus_region); 290 pcibios_bus_to_resource(dev, res, &bus_region);
293 291
294 pci_claim_resource(dev, nr); 292 pci_claim_resource(dev, nr);
295 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 293 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
296 } 294 }
297} 295}
298 296
@@ -302,12 +300,12 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
302 */ 300 */
303static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 301static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
304{ 302{
305 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 303 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
306 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
307 request_region(0x3b0, 0x0C, "RadeonIGP"); 305 request_region(0x3b0, 0x0C, "RadeonIGP");
308 request_region(0x3d3, 0x01, "RadeonIGP"); 306 request_region(0x3d3, 0x01, "RadeonIGP");
309} 307}
310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
311 309
312/* 310/*
313 * Let's make the southbridge information explicit instead 311 * Let's make the southbridge information explicit instead
@@ -329,7 +327,7 @@ static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
329 pci_read_config_word(dev, 0xE2, &region); 327 pci_read_config_word(dev, 0xE2, &region);
330 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 328 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
331} 329}
332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
333 331
334static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 332static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
335{ 333{
@@ -354,7 +352,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
354 * let's get enough confirmation reports first. 352 * let's get enough confirmation reports first.
355 */ 353 */
356 base &= -size; 354 base &= -size;
357 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 355 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
358} 356}
359 357
360static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 358static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
@@ -379,7 +377,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
379 * reserve it, but let's get enough confirmation reports first. 377 * reserve it, but let's get enough confirmation reports first.
380 */ 378 */
381 base &= -size; 379 base &= -size;
382 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 380 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
383} 381}
384 382
385/* 383/*
@@ -418,8 +416,8 @@ static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
418 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 416 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
419 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 417 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
420} 418}
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); 420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
423 421
424/* 422/*
425 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
@@ -436,16 +434,16 @@ static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
436 pci_read_config_dword(dev, 0x58, &region); 434 pci_read_config_dword(dev, 0x58, &region);
437 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 435 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
438} 436}
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
449 447
450static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 448static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
451{ 449{
@@ -457,20 +455,20 @@ static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
457 pci_read_config_dword(dev, 0x48, &region); 455 pci_read_config_dword(dev, 0x48, &region);
458 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 456 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
459} 457}
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); 458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi ); 460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi ); 461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi ); 462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi ); 463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi ); 464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi ); 465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi ); 466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi ); 467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi ); 468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi ); 469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi ); 470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi ); 471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
474 472
475/* 473/*
476 * VIA ACPI: One IO region pointed to by longword at 474 * VIA ACPI: One IO region pointed to by longword at
@@ -486,7 +484,7 @@ static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
486 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 484 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
487 } 485 }
488} 486}
489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
490 488
491/* 489/*
492 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
@@ -509,7 +507,7 @@ static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
509 smb &= PCI_BASE_ADDRESS_IO_MASK; 507 smb &= PCI_BASE_ADDRESS_IO_MASK;
510 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 508 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
511} 509}
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
513 511
514/* 512/*
515 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
@@ -551,14 +549,14 @@ static void quirk_via_ioapic(struct pci_dev *dev)
551 else 549 else
552 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 550 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
553 551
554 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 552 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
555 tmp == 0 ? "Disa" : "Ena"); 553 tmp == 0 ? "Disa" : "Ena");
556 554
557 /* Offset 0x58: External APIC IRQ output control */ 555 /* Offset 0x58: External APIC IRQ output control */
558 pci_write_config_byte (dev, 0x58, tmp); 556 pci_write_config_byte (dev, 0x58, tmp);
559} 557}
560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
561DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 559DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
562 560
563/* 561/*
564 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
@@ -573,7 +571,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
573 571
574 pci_read_config_byte(dev, 0x5B, &misc_control2); 572 pci_read_config_byte(dev, 0x5B, &misc_control2);
575 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 573 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
576 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 574 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
577 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 575 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
578 } 576 }
579} 577}
@@ -592,18 +590,18 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_v
592static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 590static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
593{ 591{
594 if (dev->revision >= 0x02) { 592 if (dev->revision >= 0x02) {
595 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 593 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
596 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 594 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
597 } 595 }
598} 596}
599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
600 598
601static void __init quirk_ioapic_rmw(struct pci_dev *dev) 599static void __init quirk_ioapic_rmw(struct pci_dev *dev)
602{ 600{
603 if (dev->devfn == 0 && dev->bus->number == 0) 601 if (dev->devfn == 0 && dev->bus->number == 0)
604 sis_apic_bug = 1; 602 sis_apic_bug = 1;
605} 603}
606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
607 605
608#define AMD8131_revA0 0x01 606#define AMD8131_revA0 0x01
609#define AMD8131_revB0 0x11 607#define AMD8131_revB0 0x11
@@ -617,7 +615,7 @@ static void quirk_amd_8131_ioapic(struct pci_dev *dev)
617 return; 615 return;
618 616
619 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) { 617 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
620 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 618 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
621 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 619 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
622 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 620 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
623 pci_write_config_byte( dev, AMD8131_MISC, tmp); 621 pci_write_config_byte( dev, AMD8131_MISC, tmp);
@@ -634,8 +632,8 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk
634static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 632static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
635{ 633{
636 if (dev->subordinate && dev->revision <= 0x12) { 634 if (dev->subordinate && dev->revision <= 0x12) {
637 printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X " 635 dev_info(&dev->dev, "AMD8131 rev %x detected; "
638 "MMRBC\n", dev->revision); 636 "disabling PCI-X MMRBC\n", dev->revision);
639 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 637 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
640 } 638 }
641} 639}
@@ -660,8 +658,8 @@ static void __devinit quirk_via_acpi(struct pci_dev *d)
660 if (irq && (irq != 2)) 658 if (irq && (irq != 2))
661 d->irq = irq; 659 d->irq = irq;
662} 660}
663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 662DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
665 663
666 664
667/* 665/*
@@ -742,8 +740,8 @@ static void quirk_via_vlink(struct pci_dev *dev)
742 740
743 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
744 if (new_irq != irq) { 742 if (new_irq != irq) {
745 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n", 743 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
746 pci_name(dev), irq, new_irq); 744 irq, new_irq);
747 udelay(15); /* unknown if delay really needed */ 745 udelay(15); /* unknown if delay really needed */
748 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 746 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
749 } 747 }
@@ -761,7 +759,7 @@ static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
761 pci_write_config_byte(dev, 0xfc, 0); 759 pci_write_config_byte(dev, 0xfc, 0);
762 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 760 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
763} 761}
764DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
765 763
766/* 764/*
767 * CardBus controllers have a legacy base address that enables them 765 * CardBus controllers have a legacy base address that enables them
@@ -791,15 +789,15 @@ static void quirk_amd_ordering(struct pci_dev *dev)
791 pci_read_config_dword(dev, 0x4C, &pcic); 789 pci_read_config_dword(dev, 0x4C, &pcic);
792 if ((pcic&6)!=6) { 790 if ((pcic&6)!=6) {
793 pcic |= 6; 791 pcic |= 6;
794 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 792 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
795 pci_write_config_dword(dev, 0x4C, pcic); 793 pci_write_config_dword(dev, 0x4C, pcic);
796 pci_read_config_dword(dev, 0x84, &pcic); 794 pci_read_config_dword(dev, 0x84, &pcic);
797 pcic |= (1<<23); /* Required in this mode */ 795 pcic |= (1<<23); /* Required in this mode */
798 pci_write_config_dword(dev, 0x84, pcic); 796 pci_write_config_dword(dev, 0x84, pcic);
799 } 797 }
800} 798}
801DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
802DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 800DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
803 801
804/* 802/*
805 * DreamWorks provided workaround for Dunord I-3000 problem 803 * DreamWorks provided workaround for Dunord I-3000 problem
@@ -814,7 +812,7 @@ static void __devinit quirk_dunord ( struct pci_dev * dev )
814 r->start = 0; 812 r->start = 0;
815 r->end = 0xffffff; 813 r->end = 0xffffff;
816} 814}
817DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
818 816
819/* 817/*
820 * i82380FB mobile docking controller: its PCI-to-PCI bridge 818 * i82380FB mobile docking controller: its PCI-to-PCI bridge
@@ -826,8 +824,8 @@ static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
826{ 824{
827 dev->transparent = 1; 825 dev->transparent = 1;
828} 826}
829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
831 829
832/* 830/*
833 * Common misconfiguration of the MediaGX/Geode PCI master that will 831 * Common misconfiguration of the MediaGX/Geode PCI master that will
@@ -841,12 +839,12 @@ static void quirk_mediagx_master(struct pci_dev *dev)
841 pci_read_config_byte(dev, 0x41, &reg); 839 pci_read_config_byte(dev, 0x41, &reg);
842 if (reg & 2) { 840 if (reg & 2) {
843 reg &= ~2; 841 reg &= ~2;
844 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 842 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
845 pci_write_config_byte(dev, 0x41, reg); 843 pci_write_config_byte(dev, 0x41, reg);
846 } 844 }
847} 845}
848DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
849DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 847DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
850 848
851/* 849/*
852 * Ensure C0 rev restreaming is off. This is normally done by 850 * Ensure C0 rev restreaming is off. This is normally done by
@@ -863,11 +861,11 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
863 if (config & (1<<6)) { 861 if (config & (1<<6)) {
864 config &= ~(1<<6); 862 config &= ~(1<<6);
865 pci_write_config_word(pdev, 0x40, config); 863 pci_write_config_word(pdev, 0x40, config);
866 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 864 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
867 } 865 }
868} 866}
869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
870DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 868DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
871 869
872 870
873static void __devinit quirk_sb600_sata(struct pci_dev *pdev) 871static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
@@ -902,7 +900,7 @@ static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
902 /* PCI layer will sort out resources */ 900 /* PCI layer will sort out resources */
903 } 901 }
904} 902}
905DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 903DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
906 904
907/* 905/*
908 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 906 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
@@ -914,7 +912,7 @@ static void __init quirk_ide_samemode(struct pci_dev *pdev)
914 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 912 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
915 913
916 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 914 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
917 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 915 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
918 prog &= ~5; 916 prog &= ~5;
919 pdev->class &= ~5; 917 pdev->class &= ~5;
920 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 918 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
@@ -929,7 +927,7 @@ static void __init quirk_eisa_bridge(struct pci_dev *dev)
929{ 927{
930 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 928 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
931} 929}
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 930DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
933 931
934 932
935/* 933/*
@@ -1022,6 +1020,11 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1022 case 0x12bd: /* HP D530 */ 1020 case 0x12bd: /* HP D530 */
1023 asus_hides_smbus = 1; 1021 asus_hides_smbus = 1;
1024 } 1022 }
1023 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1024 switch (dev->subsystem_device) {
1025 case 0x12bf: /* HP xw4100 */
1026 asus_hides_smbus = 1;
1027 }
1025 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1028 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1026 switch (dev->subsystem_device) { 1029 switch (dev->subsystem_device) {
1027 case 0x099c: /* HP Compaq nx6110 */ 1030 case 0x099c: /* HP Compaq nx6110 */
@@ -1049,17 +1052,18 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1049 } 1052 }
1050 } 1053 }
1051} 1054}
1052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); 1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1061 1065
1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge ); 1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1063 1067
1064static void asus_hides_smbus_lpc(struct pci_dev *dev) 1068static void asus_hides_smbus_lpc(struct pci_dev *dev)
1065{ 1069{
@@ -1073,25 +1077,25 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev)
1073 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1077 pci_write_config_word(dev, 0xF2, val & (~0x8));
1074 pci_read_config_word(dev, 0xF2, &val); 1078 pci_read_config_word(dev, 0xF2, &val);
1075 if (val & 0x8) 1079 if (val & 0x8)
1076 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1080 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1077 else 1081 else
1078 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 1082 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1079 } 1083 }
1080} 1084}
1081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc ); 1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1084DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1088DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc ); 1092DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1089DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1093DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1090DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1094DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1091DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1095DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1092DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1096DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1093DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1097DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1094DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1098DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1095 1099
1096static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1100static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1097{ 1101{
@@ -1106,10 +1110,10 @@ static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1106 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1110 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1107 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1111 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1108 iounmap(base); 1112 iounmap(base);
1109 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1113 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1110} 1114}
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1112DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1116DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1113 1117
1114/* 1118/*
1115 * SiS 96x south bridge: BIOS typically hides SMBus device... 1119 * SiS 96x south bridge: BIOS typically hides SMBus device...
@@ -1119,18 +1123,18 @@ static void quirk_sis_96x_smbus(struct pci_dev *dev)
1119 u8 val = 0; 1123 u8 val = 0;
1120 pci_read_config_byte(dev, 0x77, &val); 1124 pci_read_config_byte(dev, 0x77, &val);
1121 if (val & 0x10) { 1125 if (val & 0x10) {
1122 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1126 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1123 pci_write_config_byte(dev, 0x77, val & ~0x10); 1127 pci_write_config_byte(dev, 0x77, val & ~0x10);
1124 } 1128 }
1125} 1129}
1126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1129DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1133DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1130DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1134DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1131DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1135DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1132DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1136DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1133DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1134 1138
1135/* 1139/*
1136 * ... This is further complicated by the fact that some SiS96x south 1140 * ... This is further complicated by the fact that some SiS96x south
@@ -1163,8 +1167,8 @@ static void quirk_sis_503(struct pci_dev *dev)
1163 dev->device = devid; 1167 dev->device = devid;
1164 quirk_sis_96x_smbus(dev); 1168 quirk_sis_96x_smbus(dev);
1165} 1169}
1166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1167DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1171DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1168 1172
1169 1173
1170/* 1174/*
@@ -1191,13 +1195,13 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev)
1191 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1195 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1192 pci_read_config_byte(dev, 0x50, &val); 1196 pci_read_config_byte(dev, 0x50, &val);
1193 if (val & 0xc0) 1197 if (val & 0xc0)
1194 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1198 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1195 else 1199 else
1196 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); 1200 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1197 } 1201 }
1198} 1202}
1199DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1203DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1200DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1204DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1201 1205
1202#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1206#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1203 1207
@@ -1292,7 +1296,7 @@ static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1292 } 1296 }
1293 1297
1294} 1298}
1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1296#endif 1300#endif
1297 1301
1298int pcie_mch_quirk; 1302int pcie_mch_quirk;
@@ -1302,9 +1306,9 @@ static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1302{ 1306{
1303 pcie_mch_quirk = 1; 1307 pcie_mch_quirk = 1;
1304} 1308}
1305DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1308 1312
1309 1313
1310/* 1314/*
@@ -1314,11 +1318,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
1314static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1318static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1315{ 1319{
1316 pci_msi_off(dev); 1320 pci_msi_off(dev);
1317
1318 dev->no_msi = 1; 1321 dev->no_msi = 1;
1319 1322 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1320 printk(KERN_WARNING "PCI: PXH quirk detected, "
1321 "disabling MSI for SHPC device\n");
1322} 1323}
1323DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1325DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
@@ -1399,7 +1400,7 @@ static void __devinit quirk_netmos(struct pci_dev *dev)
1399 case PCI_DEVICE_ID_NETMOS_9855: 1400 case PCI_DEVICE_ID_NETMOS_9855:
1400 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1401 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1401 num_parallel) { 1402 num_parallel) {
1402 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1403 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1403 "%u serial); changing class SERIAL to OTHER " 1404 "%u serial); changing class SERIAL to OTHER "
1404 "(use parport_serial)\n", 1405 "(use parport_serial)\n",
1405 dev->device, num_parallel, num_serial); 1406 dev->device, num_parallel, num_serial);
@@ -1412,9 +1413,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1412 1413
1413static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1414static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1414{ 1415{
1415 u16 command; 1416 u16 command, pmcsr;
1416 u8 __iomem *csr; 1417 u8 __iomem *csr;
1417 u8 cmd_hi; 1418 u8 cmd_hi;
1419 int pm;
1418 1420
1419 switch (dev->device) { 1421 switch (dev->device) {
1420 /* PCI IDs taken from drivers/net/e100.c */ 1422 /* PCI IDs taken from drivers/net/e100.c */
@@ -1448,18 +1450,28 @@ static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1448 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1450 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1449 return; 1451 return;
1450 1452
1453 /*
1454 * Check that the device is in the D0 power state. If it's not,
1455 * there is no point to look any further.
1456 */
1457 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1458 if (pm) {
1459 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1460 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1461 return;
1462 }
1463
1451 /* Convert from PCI bus to resource space. */ 1464 /* Convert from PCI bus to resource space. */
1452 csr = ioremap(pci_resource_start(dev, 0), 8); 1465 csr = ioremap(pci_resource_start(dev, 0), 8);
1453 if (!csr) { 1466 if (!csr) {
1454 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", 1467 dev_warn(&dev->dev, "Can't map e100 registers\n");
1455 pci_name(dev));
1456 return; 1468 return;
1457 } 1469 }
1458 1470
1459 cmd_hi = readb(csr + 3); 1471 cmd_hi = readb(csr + 3);
1460 if (cmd_hi == 0) { 1472 if (cmd_hi == 0) {
1461 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " 1473 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1462 "enabled, disabling\n", pci_name(dev)); 1474 "disabling\n");
1463 writeb(1, csr + 3); 1475 writeb(1, csr + 3);
1464 } 1476 }
1465 1477
@@ -1474,7 +1486,7 @@ static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1474 */ 1486 */
1475 1487
1476 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1488 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1477 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1489 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1478 dev->class = PCI_CLASS_STORAGE_SCSI; 1490 dev->class = PCI_CLASS_STORAGE_SCSI;
1479 } 1491 }
1480} 1492}
@@ -1485,7 +1497,11 @@ static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_f
1485 while (f < end) { 1497 while (f < end) {
1486 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1498 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1487 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1499 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1488 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1500#ifdef DEBUG
1501 dev_dbg(&dev->dev, "calling quirk 0x%p", f->hook);
1502 print_fn_descriptor_symbol(": %s()\n",
1503 (unsigned long) f->hook);
1504#endif
1489 f->hook(dev); 1505 f->hook(dev);
1490 } 1506 }
1491 f++; 1507 f++;
@@ -1553,7 +1569,7 @@ static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1553 pci_read_config_word(dev, 0x40, &en1k); 1569 pci_read_config_word(dev, 0x40, &en1k);
1554 1570
1555 if (en1k & 0x200) { 1571 if (en1k & 0x200) {
1556 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1572 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1557 1573
1558 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1574 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1559 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1575 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
@@ -1585,7 +1601,7 @@ static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1585 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1601 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1586 1602
1587 if (iobl_adr != iobl_adr_1k) { 1603 if (iobl_adr != iobl_adr_1k) {
1588 printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n", 1604 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1589 iobl_adr,iobl_adr_1k); 1605 iobl_adr,iobl_adr_1k);
1590 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1606 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1591 } 1607 }
@@ -1603,9 +1619,8 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1603 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1619 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1604 if (!(b & 0x20)) { 1620 if (!(b & 0x20)) {
1605 pci_write_config_byte(dev, 0xf41, b | 0x20); 1621 pci_write_config_byte(dev, 0xf41, b | 0x20);
1606 printk(KERN_INFO 1622 dev_info(&dev->dev,
1607 "PCI: Linking AER extended capability on %s\n", 1623 "Linking AER extended capability\n");
1608 pci_name(dev));
1609 } 1624 }
1610 } 1625 }
1611} 1626}
@@ -1614,6 +1629,34 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1614DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1629DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1615 quirk_nvidia_ck804_pcie_aer_ext_cap); 1630 quirk_nvidia_ck804_pcie_aer_ext_cap);
1616 1631
1632static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1633{
1634 /*
1635 * Disable PCI Bus Parking and PCI Master read caching on CX700
1636 * which causes unspecified timing errors with a VT6212L on the PCI
1637 * bus leading to USB2.0 packet loss. The defaults are that these
1638 * features are turned off but some BIOSes turn them on.
1639 */
1640
1641 uint8_t b;
1642 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1643 if (b & 0x40) {
1644 /* Turn off PCI Bus Parking */
1645 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1646
1647 /* Turn off PCI Master read caching */
1648 pci_write_config_byte(dev, 0x72, 0x0);
1649 pci_write_config_byte(dev, 0x75, 0x1);
1650 pci_write_config_byte(dev, 0x77, 0x0);
1651
1652 printk(KERN_INFO
1653 "PCI: VIA CX700 PCI parking/caching fixup on %s\n",
1654 pci_name(dev));
1655 }
1656 }
1657}
1658DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1659
1617#ifdef CONFIG_PCI_MSI 1660#ifdef CONFIG_PCI_MSI
1618/* Some chipsets do not support MSI. We cannot easily rely on setting 1661/* Some chipsets do not support MSI. We cannot easily rely on setting
1619 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 1662 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
@@ -1624,7 +1667,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1624static void __init quirk_disable_all_msi(struct pci_dev *dev) 1667static void __init quirk_disable_all_msi(struct pci_dev *dev)
1625{ 1668{
1626 pci_no_msi(); 1669 pci_no_msi();
1627 printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n"); 1670 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1628} 1671}
1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
@@ -1635,9 +1678,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disab
1635static void __devinit quirk_disable_msi(struct pci_dev *dev) 1678static void __devinit quirk_disable_msi(struct pci_dev *dev)
1636{ 1679{
1637 if (dev->subordinate) { 1680 if (dev->subordinate) {
1638 printk(KERN_WARNING "PCI: MSI quirk detected. " 1681 dev_warn(&dev->dev, "MSI quirk detected; "
1639 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", 1682 "subordinate MSI disabled\n");
1640 pci_name(dev));
1641 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1683 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1642 } 1684 }
1643} 1685}
@@ -1656,9 +1698,9 @@ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1656 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 1698 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1657 &flags) == 0) 1699 &flags) == 0)
1658 { 1700 {
1659 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n", 1701 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1660 flags & HT_MSI_FLAGS_ENABLE ? 1702 flags & HT_MSI_FLAGS_ENABLE ?
1661 "enabled" : "disabled", pci_name(dev)); 1703 "enabled" : "disabled");
1662 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 1704 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1663 } 1705 }
1664 1706
@@ -1672,17 +1714,40 @@ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1672static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 1714static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1673{ 1715{
1674 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 1716 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1675 printk(KERN_WARNING "PCI: MSI quirk detected. " 1717 dev_warn(&dev->dev, "MSI quirk detected; "
1676 "MSI disabled on chipset %s.\n", 1718 "subordinate MSI disabled\n");
1677 pci_name(dev));
1678 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1719 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1679 } 1720 }
1680} 1721}
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 1722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1682 quirk_msi_ht_cap); 1723 quirk_msi_ht_cap);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, 1724
1684 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 1725
1685 quirk_msi_ht_cap); 1726/*
1727 * Force enable MSI mapping capability on HT bridges
1728 */
1729static void __devinit quirk_msi_ht_cap_enable(struct pci_dev *dev)
1730{
1731 int pos, ttl = 48;
1732
1733 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1734 while (pos && ttl--) {
1735 u8 flags;
1736
1737 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) {
1738 printk(KERN_INFO "PCI: Enabling HT MSI Mapping on %s\n",
1739 pci_name(dev));
1740
1741 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1742 flags | HT_MSI_FLAGS_ENABLE);
1743 }
1744 pos = pci_find_next_ht_capability(dev, pos,
1745 HT_CAPTYPE_MSI_MAPPING);
1746 }
1747}
1748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1749 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1750 quirk_msi_ht_cap_enable);
1686 1751
1687/* The nVidia CK804 chipset may have 2 HT MSI mappings. 1752/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1688 * MSI are supported if the MSI capability set in any of these mappings. 1753 * MSI are supported if the MSI capability set in any of these mappings.
@@ -1701,9 +1766,8 @@ static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1701 if (!pdev) 1766 if (!pdev)
1702 return; 1767 return;
1703 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 1768 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1704 printk(KERN_WARNING "PCI: MSI quirk detected. " 1769 dev_warn(&dev->dev, "MSI quirk detected; "
1705 "MSI disabled on chipset %s.\n", 1770 "subordinate MSI disabled\n");
1706 pci_name(dev));
1707 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1771 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1708 } 1772 }
1709 pci_dev_put(pdev); 1773 pci_dev_put(pdev);
@@ -1715,6 +1779,23 @@ static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1715{ 1779{
1716 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 1780 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1717} 1781}
1782static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1783{
1784 struct pci_dev *p;
1785
1786 /* SB700 MSI issue will be fixed at HW level from revision A21,
1787 * we need check PCI REVISION ID of SMBus controller to get SB700
1788 * revision.
1789 */
1790 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1791 NULL);
1792 if (!p)
1793 return;
1794
1795 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1796 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1797 pci_dev_put(p);
1798}
1718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1719 PCI_DEVICE_ID_TIGON3_5780, 1800 PCI_DEVICE_ID_TIGON3_5780,
1720 quirk_msi_intx_disable_bug); 1801 quirk_msi_intx_disable_bug);
@@ -1735,17 +1816,15 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1735 quirk_msi_intx_disable_bug); 1816 quirk_msi_intx_disable_bug);
1736 1817
1737DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 1818DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
1738 quirk_msi_intx_disable_bug); 1819 quirk_msi_intx_disable_ati_bug);
1739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 1820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
1740 quirk_msi_intx_disable_bug); 1821 quirk_msi_intx_disable_ati_bug);
1741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
1742 quirk_msi_intx_disable_bug); 1823 quirk_msi_intx_disable_ati_bug);
1743DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
1744 quirk_msi_intx_disable_bug); 1825 quirk_msi_intx_disable_ati_bug);
1745DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 1826DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
1746 quirk_msi_intx_disable_bug); 1827 quirk_msi_intx_disable_ati_bug);
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4395,
1748 quirk_msi_intx_disable_bug);
1749 1828
1750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 1829DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1751 quirk_msi_intx_disable_bug); 1830 quirk_msi_intx_disable_bug);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 13:28:53 -0500