1 files changed, 74 insertions, 27 deletions

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ef09f5f2fe6c..2bbf5221afb3 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -171,9 +171,10 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         struct resource *res, unsigned int pos)
 {
         u32 l, sz, mask;
+        u64 l64, sz64, mask64;
         u16 orig_cmd;
         struct pci_bus_region region, inverted_region;
-        bool bar_too_big = false, bar_disabled = false;
+        bool bar_too_big = false, bar_too_high = false, bar_invalid = false;
 
         mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
 
@@ -226,9 +227,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
         }
 
         if (res->flags & IORESOURCE_MEM_64) {
-                u64 l64 = l;
-                u64 sz64 = sz;
-                u64 mask64 = mask | (u64)~0 << 32;
+                l64 = l;
+                sz64 = sz;
+                mask64 = mask | (u64)~0 << 32;
 
                 pci_read_config_dword(dev, pos + 4, &l);
                 pci_write_config_dword(dev, pos + 4, ~0);
@@ -243,19 +244,22 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                 if (!sz64)
                         goto fail;
 
-                if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
+                if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
+                    sz64 > 0x100000000ULL) {
+                        res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
+                        res->start = 0;
+                        res->end = 0;
                         bar_too_big = true;
-                        goto fail;
+                        goto out;
                 }
 
-                if ((sizeof(resource_size_t) < 8) && l) {
-                        /* Address above 32-bit boundary; disable the BAR */
-                        pci_write_config_dword(dev, pos, 0);
-                        pci_write_config_dword(dev, pos + 4, 0);
+                if ((sizeof(dma_addr_t) < 8) && l) {
+                        /* Above 32-bit boundary; try to reallocate */
                         res->flags |= IORESOURCE_UNSET;
-                        region.start = 0;
-                        region.end = sz64;
-                        bar_disabled = true;
+                        res->start = 0;
+                        res->end = sz64;
+                        bar_too_high = true;
+                        goto out;
                 } else {
                         region.start = l64;
                         region.end = l64 + sz64;
@@ -285,11 +289,10 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
          * be claimed by the device.
          */
         if (inverted_region.start != region.start) {
-                dev_info(&dev->dev, "reg 0x%x: initial BAR value %pa invalid; forcing reassignment\n",
-                         pos, &region.start);
                 res->flags |= IORESOURCE_UNSET;
-                res->end -= res->start;
                 res->start = 0;
+                res->end = region.end - region.start;
+                bar_invalid = true;
         }
 
         goto out;
@@ -303,8 +306,15 @@ out:
                 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 
         if (bar_too_big)
-                dev_err(&dev->dev, "reg 0x%x: can't handle 64-bit BAR\n", pos);
-        if (res->flags && !bar_disabled)
+                dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
+                        pos, (unsigned long long) sz64);
+        if (bar_too_high)
+                dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n",
+                         pos, (unsigned long long) l64);
+        if (bar_invalid)
+                dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
+                         pos, (unsigned long long) region.start);
+        if (res->flags)
                 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
 
         return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
@@ -465,7 +475,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
 
         if (dev->transparent) {
                 pci_bus_for_each_resource(child->parent, res, i) {
-                        if (res) {
+                        if (res && res->flags) {
                                 pci_bus_add_resource(child, res,
                                                      PCI_SUBTRACTIVE_DECODE);
                                 dev_printk(KERN_DEBUG, &dev->dev,
@@ -719,7 +729,7 @@ add_dev:
         return child;
 }
 
-struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
+struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
 {
         struct pci_bus *child;
 
@@ -984,6 +994,43 @@ void set_pcie_hotplug_bridge(struct pci_dev *pdev)
 
 
 /**
+ * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
+ * @dev: PCI device
+ *
+ * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
+ * when forwarding a type1 configuration request the bridge must check that
+ * the extended register address field is zero.  The bridge is not permitted
+ * to forward the transactions and must handle it as an Unsupported Request.
+ * Some bridges do not follow this rule and simply drop the extended register
+ * bits, resulting in the standard config space being aliased, every 256
+ * bytes across the entire configuration space.  Test for this condition by
+ * comparing the first dword of each potential alias to the vendor/device ID.
+ * Known offenders:
+ *   ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
+ *   AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
+ */
+static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
+{
+#ifdef CONFIG_PCI_QUIRKS
+        int pos;
+        u32 header, tmp;
+
+        pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
+
+        for (pos = PCI_CFG_SPACE_SIZE;
+             pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
+                if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
+                    || header != tmp)
+                        return false;
+        }
+
+        return true;
+#else
+        return false;
+#endif
+}
+
+/**
  * pci_cfg_space_size - get the configuration space size of the PCI device.
  * @dev: PCI device
  *
@@ -1001,7 +1048,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
 
         if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
                 goto fail;
-        if (status == 0xffffffff)
+        if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
                 goto fail;
 
         return PCI_CFG_SPACE_EXP_SIZE;
@@ -1215,6 +1262,7 @@ static void pci_release_dev(struct device *dev)
         pci_release_of_node(pci_dev);
         pcibios_release_device(pci_dev);
         pci_bus_put(pci_dev->bus);
+        kfree(pci_dev->driver_override);
         kfree(pci_dev);
 }
 
@@ -1369,7 +1417,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         WARN_ON(ret < 0);
 }
 
-struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
+struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
 {
         struct pci_dev *dev;
 
@@ -1617,7 +1665,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
  */
 void pcie_bus_configure_settings(struct pci_bus *bus)
 {
-        u8 smpss;
+        u8 smpss = 0;
 
         if (!bus->self)
                 return;
@@ -1670,8 +1718,7 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
 
         for (pass=0; pass < 2; pass++)
                 list_for_each_entry(dev, &bus->devices, bus_list) {
-                        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
-                            dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
+                        if (pci_is_bridge(dev))
                                 max = pci_scan_bridge(bus, dev, max, pass);
                 }
 
@@ -1958,7 +2005,7 @@ EXPORT_SYMBOL(pci_scan_bus);
  *
  * Returns the max number of subordinate bus discovered.
  */
-unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
+unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
 {
         unsigned int max;
         struct pci_bus *bus = bridge->subordinate;
@@ -1981,7 +2028,7 @@ unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
  *
  * Returns the max number of subordinate bus discovered.
  */
-unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
+unsigned int pci_rescan_bus(struct pci_bus *bus)
 {
         unsigned int max;