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path: root/drivers/pci/probe.c
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Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c83
1 files changed, 48 insertions, 35 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 8105e32117f6..98ffb2de22e9 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -10,6 +10,7 @@
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/cpumask.h> 11#include <linux/cpumask.h>
12#include <linux/pci-aspm.h> 12#include <linux/pci-aspm.h>
13#include <acpi/acpi_hest.h>
13#include "pci.h" 14#include "pci.h"
14 15
15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
@@ -163,12 +164,12 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
163{ 164{
164 u32 l, sz, mask; 165 u32 l, sz, mask;
165 166
166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; 167 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
167 168
168 res->name = pci_name(dev); 169 res->name = pci_name(dev);
169 170
170 pci_read_config_dword(dev, pos, &l); 171 pci_read_config_dword(dev, pos, &l);
171 pci_write_config_dword(dev, pos, mask); 172 pci_write_config_dword(dev, pos, l | mask);
172 pci_read_config_dword(dev, pos, &sz); 173 pci_read_config_dword(dev, pos, &sz);
173 pci_write_config_dword(dev, pos, l); 174 pci_write_config_dword(dev, pos, l);
174 175
@@ -223,9 +224,13 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
223 goto fail; 224 goto fail;
224 225
225 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 226 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
226 dev_err(&dev->dev, "can't handle 64-bit BAR\n"); 227 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
228 pos);
227 goto fail; 229 goto fail;
228 } else if ((sizeof(resource_size_t) < 8) && l) { 230 }
231
232 res->flags |= IORESOURCE_MEM_64;
233 if ((sizeof(resource_size_t) < 8) && l) {
229 /* Address above 32-bit boundary; disable the BAR */ 234 /* Address above 32-bit boundary; disable the BAR */
230 pci_write_config_dword(dev, pos, 0); 235 pci_write_config_dword(dev, pos, 0);
231 pci_write_config_dword(dev, pos + 4, 0); 236 pci_write_config_dword(dev, pos + 4, 0);
@@ -234,14 +239,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
234 } else { 239 } else {
235 res->start = l64; 240 res->start = l64;
236 res->end = l64 + sz64; 241 res->end = l64 + sz64;
237 dev_printk(KERN_DEBUG, &dev->dev, 242 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
238 "reg %x %s: %pR\n", pos, 243 pos, res);
239 (res->flags & IORESOURCE_PREFETCH) ?
240 "64bit mmio pref" : "64bit mmio",
241 res);
242 } 244 }
243
244 res->flags |= IORESOURCE_MEM_64;
245 } else { 245 } else {
246 sz = pci_size(l, sz, mask); 246 sz = pci_size(l, sz, mask);
247 247
@@ -251,11 +251,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
251 res->start = l; 251 res->start = l;
252 res->end = l + sz; 252 res->end = l + sz;
253 253
254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos, 254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
255 (res->flags & IORESOURCE_IO) ? "io port" :
256 ((res->flags & IORESOURCE_PREFETCH) ?
257 "32bit mmio pref" : "32bit mmio"),
258 res);
259 } 255 }
260 256
261 out: 257 out:
@@ -297,8 +293,11 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
297 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 293 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
298 return; 294 return;
299 295
296 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
297 child->secondary, child->subordinate,
298 dev->transparent ? " (subtractive decode)": "");
299
300 if (dev->transparent) { 300 if (dev->transparent) {
301 dev_info(&dev->dev, "transparent bridge\n");
302 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) 301 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
303 child->resource[i] = child->parent->resource[i - 3]; 302 child->resource[i] = child->parent->resource[i - 3];
304 } 303 }
@@ -323,7 +322,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
323 res->start = base; 322 res->start = base;
324 if (!res->end) 323 if (!res->end)
325 res->end = limit + 0xfff; 324 res->end = limit + 0xfff;
326 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res); 325 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
327 } 326 }
328 327
329 res = child->resource[1]; 328 res = child->resource[1];
@@ -335,8 +334,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
335 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 334 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
336 res->start = base; 335 res->start = base;
337 res->end = limit + 0xfffff; 336 res->end = limit + 0xfffff;
338 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n", 337 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
339 res);
340 } 338 }
341 339
342 res = child->resource[2]; 340 res = child->resource[2];
@@ -375,9 +373,7 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
375 res->flags |= IORESOURCE_MEM_64; 373 res->flags |= IORESOURCE_MEM_64;
376 res->start = base; 374 res->start = base;
377 res->end = limit + 0xfffff; 375 res->end = limit + 0xfffff;
378 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n", 376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
379 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
380 res);
381 } 377 }
382} 378}
383 379
@@ -651,13 +647,14 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
651 (child->number > bus->subordinate) || 647 (child->number > bus->subordinate) ||
652 (child->number < bus->number) || 648 (child->number < bus->number) ||
653 (child->subordinate < bus->number)) { 649 (child->subordinate < bus->number)) {
654 pr_debug("PCI: Bus #%02x (-#%02x) is %s " 650 dev_info(&child->dev, "[bus %02x-%02x] %s "
655 "hidden behind%s bridge #%02x (-#%02x)\n", 651 "hidden behind%s bridge %s [bus %02x-%02x]\n",
656 child->number, child->subordinate, 652 child->number, child->subordinate,
657 (bus->number > child->subordinate && 653 (bus->number > child->subordinate &&
658 bus->subordinate < child->number) ? 654 bus->subordinate < child->number) ?
659 "wholly" : "partially", 655 "wholly" : "partially",
660 bus->self->transparent ? " transparent" : "", 656 bus->self->transparent ? " transparent" : "",
657 dev_name(&bus->dev),
661 bus->number, bus->subordinate); 658 bus->number, bus->subordinate);
662 } 659 }
663 bus = bus->parent; 660 bus = bus->parent;
@@ -693,6 +690,7 @@ static void set_pcie_port_type(struct pci_dev *pdev)
693 if (!pos) 690 if (!pos)
694 return; 691 return;
695 pdev->is_pcie = 1; 692 pdev->is_pcie = 1;
693 pdev->pcie_cap = pos;
696 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 694 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
697 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 695 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
698} 696}
@@ -703,7 +701,7 @@ static void set_pcie_hotplug_bridge(struct pci_dev *pdev)
703 u16 reg16; 701 u16 reg16;
704 u32 reg32; 702 u32 reg32;
705 703
706 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 704 pos = pci_pcie_cap(pdev);
707 if (!pos) 705 if (!pos)
708 return; 706 return;
709 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 707 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
@@ -714,6 +712,12 @@ static void set_pcie_hotplug_bridge(struct pci_dev *pdev)
714 pdev->is_hotplug_bridge = 1; 712 pdev->is_hotplug_bridge = 1;
715} 713}
716 714
715static void set_pci_aer_firmware_first(struct pci_dev *pdev)
716{
717 if (acpi_hest_firmware_first_pci(pdev))
718 pdev->aer_firmware_first = 1;
719}
720
717#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 721#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
718 722
719/** 723/**
@@ -731,6 +735,7 @@ int pci_setup_device(struct pci_dev *dev)
731 u32 class; 735 u32 class;
732 u8 hdr_type; 736 u8 hdr_type;
733 struct pci_slot *slot; 737 struct pci_slot *slot;
738 int pos = 0;
734 739
735 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 740 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
736 return -EIO; 741 return -EIO;
@@ -742,6 +747,7 @@ int pci_setup_device(struct pci_dev *dev)
742 dev->multifunction = !!(hdr_type & 0x80); 747 dev->multifunction = !!(hdr_type & 0x80);
743 dev->error_state = pci_channel_io_normal; 748 dev->error_state = pci_channel_io_normal;
744 set_pcie_port_type(dev); 749 set_pcie_port_type(dev);
750 set_pci_aer_firmware_first(dev);
745 751
746 list_for_each_entry(slot, &dev->bus->slots, list) 752 list_for_each_entry(slot, &dev->bus->slots, list)
747 if (PCI_SLOT(dev->devfn) == slot->number) 753 if (PCI_SLOT(dev->devfn) == slot->number)
@@ -822,6 +828,11 @@ int pci_setup_device(struct pci_dev *dev)
822 dev->transparent = ((dev->class & 0xff) == 1); 828 dev->transparent = ((dev->class & 0xff) == 1);
823 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 829 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
824 set_pcie_hotplug_bridge(dev); 830 set_pcie_hotplug_bridge(dev);
831 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
832 if (pos) {
833 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
834 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
835 }
825 break; 836 break;
826 837
827 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 838 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
@@ -907,7 +918,7 @@ int pci_cfg_space_size(struct pci_dev *dev)
907 if (class == PCI_CLASS_BRIDGE_HOST) 918 if (class == PCI_CLASS_BRIDGE_HOST)
908 return pci_cfg_space_size_ext(dev); 919 return pci_cfg_space_size_ext(dev);
909 920
910 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 921 pos = pci_pcie_cap(dev);
911 if (!pos) { 922 if (!pos) {
912 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 923 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
913 if (!pos) 924 if (!pos)
@@ -1014,6 +1025,9 @@ static void pci_init_capabilities(struct pci_dev *dev)
1014 1025
1015 /* Single Root I/O Virtualization */ 1026 /* Single Root I/O Virtualization */
1016 pci_iov_init(dev); 1027 pci_iov_init(dev);
1028
1029 /* Enable ACS P2P upstream forwarding */
1030 pci_enable_acs(dev);
1017} 1031}
1018 1032
1019void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 1033void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
@@ -1110,7 +1124,7 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1110 unsigned int devfn, pass, max = bus->secondary; 1124 unsigned int devfn, pass, max = bus->secondary;
1111 struct pci_dev *dev; 1125 struct pci_dev *dev;
1112 1126
1113 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); 1127 dev_dbg(&bus->dev, "scanning bus\n");
1114 1128
1115 /* Go find them, Rover! */ 1129 /* Go find them, Rover! */
1116 for (devfn = 0; devfn < 0x100; devfn += 8) 1130 for (devfn = 0; devfn < 0x100; devfn += 8)
@@ -1124,8 +1138,7 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1124 * all PCI-to-PCI bridges on this bus. 1138 * all PCI-to-PCI bridges on this bus.
1125 */ 1139 */
1126 if (!bus->is_added) { 1140 if (!bus->is_added) {
1127 pr_debug("PCI: Fixups for bus %04x:%02x\n", 1141 dev_dbg(&bus->dev, "fixups for bus\n");
1128 pci_domain_nr(bus), bus->number);
1129 pcibios_fixup_bus(bus); 1142 pcibios_fixup_bus(bus);
1130 if (pci_is_root_bus(bus)) 1143 if (pci_is_root_bus(bus))
1131 bus->is_added = 1; 1144 bus->is_added = 1;
@@ -1145,8 +1158,7 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1145 * 1158 *
1146 * Return how far we've got finding sub-buses. 1159 * Return how far we've got finding sub-buses.
1147 */ 1160 */
1148 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", 1161 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1149 pci_domain_nr(bus), bus->number, max);
1150 return max; 1162 return max;
1151} 1163}
1152 1164
@@ -1154,7 +1166,7 @@ struct pci_bus * pci_create_bus(struct device *parent,
1154 int bus, struct pci_ops *ops, void *sysdata) 1166 int bus, struct pci_ops *ops, void *sysdata)
1155{ 1167{
1156 int error; 1168 int error;
1157 struct pci_bus *b; 1169 struct pci_bus *b, *b2;
1158 struct device *dev; 1170 struct device *dev;
1159 1171
1160 b = pci_alloc_bus(); 1172 b = pci_alloc_bus();
@@ -1170,9 +1182,10 @@ struct pci_bus * pci_create_bus(struct device *parent,
1170 b->sysdata = sysdata; 1182 b->sysdata = sysdata;
1171 b->ops = ops; 1183 b->ops = ops;
1172 1184
1173 if (pci_find_bus(pci_domain_nr(b), bus)) { 1185 b2 = pci_find_bus(pci_domain_nr(b), bus);
1186 if (b2) {
1174 /* If we already got to this bus through a different bridge, ignore it */ 1187 /* If we already got to this bus through a different bridge, ignore it */
1175 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); 1188 dev_dbg(&b2->dev, "bus already known\n");
1176 goto err_out; 1189 goto err_out;
1177 } 1190 }
1178 1191