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path: root/drivers/pci/probe.c
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Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c48
1 files changed, 27 insertions, 21 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 5b3f5937ecf5..55ec44a27e89 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -51,12 +51,12 @@ static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
51 char *buf) 51 char *buf)
52{ 52{
53 int ret; 53 int ret;
54 cpumask_t cpumask; 54 const struct cpumask *cpumask;
55 55
56 cpumask = pcibus_to_cpumask(to_pci_bus(dev)); 56 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
57 ret = type? 57 ret = type?
58 cpulist_scnprintf(buf, PAGE_SIZE-2, &cpumask) : 58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, &cpumask); 59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
60 buf[ret++] = '\n'; 60 buf[ret++] = '\n';
61 buf[ret] = '\0'; 61 buf[ret] = '\0';
62 return ret; 62 return ret;
@@ -135,13 +135,6 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
135 return size; 135 return size;
136} 136}
137 137
138enum pci_bar_type {
139 pci_bar_unknown, /* Standard PCI BAR probe */
140 pci_bar_io, /* An io port BAR */
141 pci_bar_mem32, /* A 32-bit memory BAR */
142 pci_bar_mem64, /* A 64-bit memory BAR */
143};
144
145static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) 138static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
146{ 139{
147 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
@@ -156,11 +149,16 @@ static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
156 return pci_bar_mem32; 149 return pci_bar_mem32;
157} 150}
158 151
159/* 152/**
160 * If the type is not unknown, we assume that the lowest bit is 'enable'. 153 * pci_read_base - read a PCI BAR
161 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. 154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
158 *
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
162 */ 160 */
163static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 161int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
164 struct resource *res, unsigned int pos) 162 struct resource *res, unsigned int pos)
165{ 163{
166 u32 l, sz, mask; 164 u32 l, sz, mask;
@@ -400,19 +398,17 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
400 if (!child) 398 if (!child)
401 return NULL; 399 return NULL;
402 400
403 child->self = bridge;
404 child->parent = parent; 401 child->parent = parent;
405 child->ops = parent->ops; 402 child->ops = parent->ops;
406 child->sysdata = parent->sysdata; 403 child->sysdata = parent->sysdata;
407 child->bus_flags = parent->bus_flags; 404 child->bus_flags = parent->bus_flags;
408 child->bridge = get_device(&bridge->dev);
409 405
410 /* initialize some portions of the bus device, but don't register it 406 /* initialize some portions of the bus device, but don't register it
411 * now as the parent is not properly set up yet. This device will get 407 * now as the parent is not properly set up yet. This device will get
412 * registered later in pci_bus_add_devices() 408 * registered later in pci_bus_add_devices()
413 */ 409 */
414 child->dev.class = &pcibus_class; 410 child->dev.class = &pcibus_class;
415 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr); 411 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
416 412
417 /* 413 /*
418 * Set up the primary, secondary and subordinate 414 * Set up the primary, secondary and subordinate
@@ -422,8 +418,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
422 child->primary = parent->secondary; 418 child->primary = parent->secondary;
423 child->subordinate = 0xff; 419 child->subordinate = 0xff;
424 420
421 if (!bridge)
422 return child;
423
424 child->self = bridge;
425 child->bridge = get_device(&bridge->dev);
426
425 /* Set up default resource pointers and names.. */ 427 /* Set up default resource pointers and names.. */
426 for (i = 0; i < 4; i++) { 428 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
427 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 429 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
428 child->resource[i]->name = child->name; 430 child->resource[i]->name = child->name;
429 } 431 }
@@ -958,8 +960,12 @@ static void pci_init_capabilities(struct pci_dev *dev)
958 /* MSI/MSI-X list */ 960 /* MSI/MSI-X list */
959 pci_msi_init_pci_dev(dev); 961 pci_msi_init_pci_dev(dev);
960 962
963 /* Buffers for saving PCIe and PCI-X capabilities */
964 pci_allocate_cap_save_buffers(dev);
965
961 /* Power Management */ 966 /* Power Management */
962 pci_pm_init(dev); 967 pci_pm_init(dev);
968 platform_pci_wakeup_init(dev);
963 969
964 /* Vital Product Data */ 970 /* Vital Product Data */
965 pci_vpd_pci22_init(dev); 971 pci_vpd_pci22_init(dev);
@@ -1130,7 +1136,7 @@ struct pci_bus * pci_create_bus(struct device *parent,
1130 memset(dev, 0, sizeof(*dev)); 1136 memset(dev, 0, sizeof(*dev));
1131 dev->parent = parent; 1137 dev->parent = parent;
1132 dev->release = pci_release_bus_bridge_dev; 1138 dev->release = pci_release_bus_bridge_dev;
1133 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus); 1139 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1134 error = device_register(dev); 1140 error = device_register(dev);
1135 if (error) 1141 if (error)
1136 goto dev_reg_err; 1142 goto dev_reg_err;
@@ -1141,7 +1147,7 @@ struct pci_bus * pci_create_bus(struct device *parent,
1141 1147
1142 b->dev.class = &pcibus_class; 1148 b->dev.class = &pcibus_class;
1143 b->dev.parent = b->bridge; 1149 b->dev.parent = b->bridge;
1144 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); 1150 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1145 error = device_register(&b->dev); 1151 error = device_register(&b->dev);
1146 if (error) 1152 if (error)
1147 goto class_dev_reg_err; 1153 goto class_dev_reg_err;