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path: root/drivers/pci/pcie/aer/aerdrv.c
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Diffstat (limited to 'drivers/pci/pcie/aer/aerdrv.c')
-rw-r--r--drivers/pci/pcie/aer/aerdrv.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index aa495ad9bbd4..7a711ee314b7 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -244,11 +244,17 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
244 244
245 /* Assert Secondary Bus Reset */ 245 /* Assert Secondary Bus Reset */
246 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl); 246 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);
247 p2p_ctrl |= PCI_CB_BRIDGE_CTL_CB_RESET; 247 p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
248 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); 248 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);
249 249
250 /*
251 * we should send hot reset message for 2ms to allow it time to
252 * propogate to all downstream ports
253 */
254 msleep(2);
255
250 /* De-assert Secondary Bus Reset */ 256 /* De-assert Secondary Bus Reset */
251 p2p_ctrl &= ~PCI_CB_BRIDGE_CTL_CB_RESET; 257 p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
252 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); 258 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);
253 259
254 /* 260 /*