diff options
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r-- | drivers/pci/pci.c | 395 |
1 files changed, 262 insertions, 133 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c87d518acace..e091b0afdc8a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c | |||
@@ -110,7 +110,7 @@ unsigned char pci_bus_max_busnr(struct pci_bus* bus) | |||
110 | struct list_head *tmp; | 110 | struct list_head *tmp; |
111 | unsigned char max, n; | 111 | unsigned char max, n; |
112 | 112 | ||
113 | max = bus->subordinate; | 113 | max = bus->busn_res.end; |
114 | list_for_each(tmp, &bus->children) { | 114 | list_for_each(tmp, &bus->children) { |
115 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | 115 | n = pci_bus_max_busnr(pci_bus_b(tmp)); |
116 | if(n > max) | 116 | if(n > max) |
@@ -136,30 +136,6 @@ void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |||
136 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | 136 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); |
137 | #endif | 137 | #endif |
138 | 138 | ||
139 | #if 0 | ||
140 | /** | ||
141 | * pci_max_busnr - returns maximum PCI bus number | ||
142 | * | ||
143 | * Returns the highest PCI bus number present in the system global list of | ||
144 | * PCI buses. | ||
145 | */ | ||
146 | unsigned char __devinit | ||
147 | pci_max_busnr(void) | ||
148 | { | ||
149 | struct pci_bus *bus = NULL; | ||
150 | unsigned char max, n; | ||
151 | |||
152 | max = 0; | ||
153 | while ((bus = pci_find_next_bus(bus)) != NULL) { | ||
154 | n = pci_bus_max_busnr(bus); | ||
155 | if(n > max) | ||
156 | max = n; | ||
157 | } | ||
158 | return max; | ||
159 | } | ||
160 | |||
161 | #endif /* 0 */ | ||
162 | |||
163 | #define PCI_FIND_CAP_TTL 48 | 139 | #define PCI_FIND_CAP_TTL 48 |
164 | 140 | ||
165 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | 141 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, |
@@ -278,6 +254,38 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |||
278 | } | 254 | } |
279 | 255 | ||
280 | /** | 256 | /** |
257 | * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure | ||
258 | * @dev: PCI device to check | ||
259 | * | ||
260 | * Like pci_pcie_cap() but also checks that the PCIe capability version is | ||
261 | * >= 2. Note that v1 capability structures could be sparse in that not | ||
262 | * all register fields were required. v2 requires the entire structure to | ||
263 | * be present size wise, while still allowing for non-implemented registers | ||
264 | * to exist but they must be hardwired to 0. | ||
265 | * | ||
266 | * Due to the differences in the versions of capability structures, one | ||
267 | * must be careful not to try and access non-existant registers that may | ||
268 | * exist in early versions - v1 - of Express devices. | ||
269 | * | ||
270 | * Returns the offset of the PCIe capability structure as long as the | ||
271 | * capability version is >= 2; otherwise 0 is returned. | ||
272 | */ | ||
273 | static int pci_pcie_cap2(struct pci_dev *dev) | ||
274 | { | ||
275 | u16 flags; | ||
276 | int pos; | ||
277 | |||
278 | pos = pci_pcie_cap(dev); | ||
279 | if (pos) { | ||
280 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); | ||
281 | if ((flags & PCI_EXP_FLAGS_VERS) < 2) | ||
282 | pos = 0; | ||
283 | } | ||
284 | |||
285 | return pos; | ||
286 | } | ||
287 | |||
288 | /** | ||
281 | * pci_find_ext_capability - Find an extended capability | 289 | * pci_find_ext_capability - Find an extended capability |
282 | * @dev: PCI device to query | 290 | * @dev: PCI device to query |
283 | * @cap: capability code | 291 | * @cap: capability code |
@@ -329,49 +337,6 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap) | |||
329 | } | 337 | } |
330 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); | 338 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
331 | 339 | ||
332 | /** | ||
333 | * pci_bus_find_ext_capability - find an extended capability | ||
334 | * @bus: the PCI bus to query | ||
335 | * @devfn: PCI device to query | ||
336 | * @cap: capability code | ||
337 | * | ||
338 | * Like pci_find_ext_capability() but works for pci devices that do not have a | ||
339 | * pci_dev structure set up yet. | ||
340 | * | ||
341 | * Returns the address of the requested capability structure within the | ||
342 | * device's PCI configuration space or 0 in case the device does not | ||
343 | * support it. | ||
344 | */ | ||
345 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, | ||
346 | int cap) | ||
347 | { | ||
348 | u32 header; | ||
349 | int ttl; | ||
350 | int pos = PCI_CFG_SPACE_SIZE; | ||
351 | |||
352 | /* minimum 8 bytes per capability */ | ||
353 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | ||
354 | |||
355 | if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) | ||
356 | return 0; | ||
357 | if (header == 0xffffffff || header == 0) | ||
358 | return 0; | ||
359 | |||
360 | while (ttl-- > 0) { | ||
361 | if (PCI_EXT_CAP_ID(header) == cap) | ||
362 | return pos; | ||
363 | |||
364 | pos = PCI_EXT_CAP_NEXT(header); | ||
365 | if (pos < PCI_CFG_SPACE_SIZE) | ||
366 | break; | ||
367 | |||
368 | if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) | ||
369 | break; | ||
370 | } | ||
371 | |||
372 | return 0; | ||
373 | } | ||
374 | |||
375 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) | 340 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
376 | { | 341 | { |
377 | int rc, ttl = PCI_FIND_CAP_TTL; | 342 | int rc, ttl = PCI_FIND_CAP_TTL; |
@@ -622,7 +587,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) | |||
622 | dev_info(&dev->dev, "Refused to change power state, " | 587 | dev_info(&dev->dev, "Refused to change power state, " |
623 | "currently in D%d\n", dev->current_state); | 588 | "currently in D%d\n", dev->current_state); |
624 | 589 | ||
625 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | 590 | /* |
591 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | ||
626 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | 592 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
627 | * from D3hot to D0 _may_ perform an internal reset, thereby | 593 | * from D3hot to D0 _may_ perform an internal reset, thereby |
628 | * going to "D0 Uninitialized" rather than "D0 Initialized". | 594 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
@@ -654,6 +620,16 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state) | |||
654 | if (dev->pm_cap) { | 620 | if (dev->pm_cap) { |
655 | u16 pmcsr; | 621 | u16 pmcsr; |
656 | 622 | ||
623 | /* | ||
624 | * Configuration space is not accessible for device in | ||
625 | * D3cold, so just keep or set D3cold for safety | ||
626 | */ | ||
627 | if (dev->current_state == PCI_D3cold) | ||
628 | return; | ||
629 | if (state == PCI_D3cold) { | ||
630 | dev->current_state = PCI_D3cold; | ||
631 | return; | ||
632 | } | ||
657 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | 633 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
658 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | 634 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
659 | } else { | 635 | } else { |
@@ -694,8 +670,50 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |||
694 | */ | 670 | */ |
695 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | 671 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) |
696 | { | 672 | { |
697 | if (state == PCI_D0) | 673 | if (state == PCI_D0) { |
698 | pci_platform_power_transition(dev, PCI_D0); | 674 | pci_platform_power_transition(dev, PCI_D0); |
675 | /* | ||
676 | * Mandatory power management transition delays, see | ||
677 | * PCI Express Base Specification Revision 2.0 Section | ||
678 | * 6.6.1: Conventional Reset. Do not delay for | ||
679 | * devices powered on/off by corresponding bridge, | ||
680 | * because have already delayed for the bridge. | ||
681 | */ | ||
682 | if (dev->runtime_d3cold) { | ||
683 | msleep(dev->d3cold_delay); | ||
684 | /* | ||
685 | * When powering on a bridge from D3cold, the | ||
686 | * whole hierarchy may be powered on into | ||
687 | * D0uninitialized state, resume them to give | ||
688 | * them a chance to suspend again | ||
689 | */ | ||
690 | pci_wakeup_bus(dev->subordinate); | ||
691 | } | ||
692 | } | ||
693 | } | ||
694 | |||
695 | /** | ||
696 | * __pci_dev_set_current_state - Set current state of a PCI device | ||
697 | * @dev: Device to handle | ||
698 | * @data: pointer to state to be set | ||
699 | */ | ||
700 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | ||
701 | { | ||
702 | pci_power_t state = *(pci_power_t *)data; | ||
703 | |||
704 | dev->current_state = state; | ||
705 | return 0; | ||
706 | } | ||
707 | |||
708 | /** | ||
709 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | ||
710 | * @bus: Top bus of the subtree to walk. | ||
711 | * @state: state to be set | ||
712 | */ | ||
713 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | ||
714 | { | ||
715 | if (bus) | ||
716 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | ||
699 | } | 717 | } |
700 | 718 | ||
701 | /** | 719 | /** |
@@ -707,8 +725,15 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |||
707 | */ | 725 | */ |
708 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | 726 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) |
709 | { | 727 | { |
710 | return state >= PCI_D0 ? | 728 | int ret; |
711 | pci_platform_power_transition(dev, state) : -EINVAL; | 729 | |
730 | if (state < PCI_D0) | ||
731 | return -EINVAL; | ||
732 | ret = pci_platform_power_transition(dev, state); | ||
733 | /* Power off the bridge may power off the whole hierarchy */ | ||
734 | if (!ret && state == PCI_D3cold) | ||
735 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | ||
736 | return ret; | ||
712 | } | 737 | } |
713 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | 738 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); |
714 | 739 | ||
@@ -732,8 +757,8 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |||
732 | int error; | 757 | int error; |
733 | 758 | ||
734 | /* bound the state we're entering */ | 759 | /* bound the state we're entering */ |
735 | if (state > PCI_D3hot) | 760 | if (state > PCI_D3cold) |
736 | state = PCI_D3hot; | 761 | state = PCI_D3cold; |
737 | else if (state < PCI_D0) | 762 | else if (state < PCI_D0) |
738 | state = PCI_D0; | 763 | state = PCI_D0; |
739 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | 764 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
@@ -748,10 +773,15 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |||
748 | 773 | ||
749 | /* This device is quirked not to be put into D3, so | 774 | /* This device is quirked not to be put into D3, so |
750 | don't put it in D3 */ | 775 | don't put it in D3 */ |
751 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | 776 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
752 | return 0; | 777 | return 0; |
753 | 778 | ||
754 | error = pci_raw_set_power_state(dev, state); | 779 | /* |
780 | * To put device in D3cold, we put device into D3hot in native | ||
781 | * way, then put device into D3cold with platform ops | ||
782 | */ | ||
783 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | ||
784 | PCI_D3hot : state); | ||
755 | 785 | ||
756 | if (!__pci_complete_power_transition(dev, state)) | 786 | if (!__pci_complete_power_transition(dev, state)) |
757 | error = 0; | 787 | error = 0; |
@@ -822,12 +852,6 @@ EXPORT_SYMBOL(pci_choose_state); | |||
822 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | 852 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ |
823 | (type == PCI_EXP_TYPE_ROOT_PORT || \ | 853 | (type == PCI_EXP_TYPE_ROOT_PORT || \ |
824 | type == PCI_EXP_TYPE_RC_EC)) | 854 | type == PCI_EXP_TYPE_RC_EC)) |
825 | #define pcie_cap_has_devctl2(type, flags) \ | ||
826 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | ||
827 | #define pcie_cap_has_lnkctl2(type, flags) \ | ||
828 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | ||
829 | #define pcie_cap_has_sltctl2(type, flags) \ | ||
830 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | ||
831 | 855 | ||
832 | static struct pci_cap_saved_state *pci_find_saved_cap( | 856 | static struct pci_cap_saved_state *pci_find_saved_cap( |
833 | struct pci_dev *pci_dev, char cap) | 857 | struct pci_dev *pci_dev, char cap) |
@@ -870,13 +894,14 @@ static int pci_save_pcie_state(struct pci_dev *dev) | |||
870 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | 894 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); |
871 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) | 895 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) |
872 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | 896 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); |
873 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) | ||
874 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); | ||
875 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) | ||
876 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); | ||
877 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) | ||
878 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); | ||
879 | 897 | ||
898 | pos = pci_pcie_cap2(dev); | ||
899 | if (!pos) | ||
900 | return 0; | ||
901 | |||
902 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); | ||
903 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); | ||
904 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); | ||
880 | return 0; | 905 | return 0; |
881 | } | 906 | } |
882 | 907 | ||
@@ -903,12 +928,14 @@ static void pci_restore_pcie_state(struct pci_dev *dev) | |||
903 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | 928 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); |
904 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) | 929 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) |
905 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | 930 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); |
906 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) | 931 | |
907 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); | 932 | pos = pci_pcie_cap2(dev); |
908 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) | 933 | if (!pos) |
909 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); | 934 | return; |
910 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) | 935 | |
911 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); | 936 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); |
937 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); | ||
938 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); | ||
912 | } | 939 | } |
913 | 940 | ||
914 | 941 | ||
@@ -1349,7 +1376,7 @@ void pcim_pin_device(struct pci_dev *pdev) | |||
1349 | * is the default implementation. Architecture implementations can | 1376 | * is the default implementation. Architecture implementations can |
1350 | * override this. | 1377 | * override this. |
1351 | */ | 1378 | */ |
1352 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | 1379 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1353 | 1380 | ||
1354 | static void do_pci_disable_device(struct pci_dev *dev) | 1381 | static void do_pci_disable_device(struct pci_dev *dev) |
1355 | { | 1382 | { |
@@ -1413,8 +1440,8 @@ pci_disable_device(struct pci_dev *dev) | |||
1413 | * Sets the PCIe reset state for the device. This is the default | 1440 | * Sets the PCIe reset state for the device. This is the default |
1414 | * implementation. Architecture implementations can override this. | 1441 | * implementation. Architecture implementations can override this. |
1415 | */ | 1442 | */ |
1416 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | 1443 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1417 | enum pcie_reset_state state) | 1444 | enum pcie_reset_state state) |
1418 | { | 1445 | { |
1419 | return -EINVAL; | 1446 | return -EINVAL; |
1420 | } | 1447 | } |
@@ -1498,6 +1525,28 @@ void pci_pme_wakeup_bus(struct pci_bus *bus) | |||
1498 | } | 1525 | } |
1499 | 1526 | ||
1500 | /** | 1527 | /** |
1528 | * pci_wakeup - Wake up a PCI device | ||
1529 | * @dev: Device to handle. | ||
1530 | * @ign: ignored parameter | ||
1531 | */ | ||
1532 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | ||
1533 | { | ||
1534 | pci_wakeup_event(pci_dev); | ||
1535 | pm_request_resume(&pci_dev->dev); | ||
1536 | return 0; | ||
1537 | } | ||
1538 | |||
1539 | /** | ||
1540 | * pci_wakeup_bus - Walk given bus and wake up devices on it | ||
1541 | * @bus: Top bus of the subtree to walk. | ||
1542 | */ | ||
1543 | void pci_wakeup_bus(struct pci_bus *bus) | ||
1544 | { | ||
1545 | if (bus) | ||
1546 | pci_walk_bus(bus, pci_wakeup, NULL); | ||
1547 | } | ||
1548 | |||
1549 | /** | ||
1501 | * pci_pme_capable - check the capability of PCI device to generate PME# | 1550 | * pci_pme_capable - check the capability of PCI device to generate PME# |
1502 | * @dev: PCI device to handle. | 1551 | * @dev: PCI device to handle. |
1503 | * @state: PCI state from which device will issue PME#. | 1552 | * @state: PCI state from which device will issue PME#. |
@@ -1518,6 +1567,16 @@ static void pci_pme_list_scan(struct work_struct *work) | |||
1518 | if (!list_empty(&pci_pme_list)) { | 1567 | if (!list_empty(&pci_pme_list)) { |
1519 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { | 1568 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1520 | if (pme_dev->dev->pme_poll) { | 1569 | if (pme_dev->dev->pme_poll) { |
1570 | struct pci_dev *bridge; | ||
1571 | |||
1572 | bridge = pme_dev->dev->bus->self; | ||
1573 | /* | ||
1574 | * If bridge is in low power state, the | ||
1575 | * configuration space of subordinate devices | ||
1576 | * may be not accessible | ||
1577 | */ | ||
1578 | if (bridge && bridge->current_state != PCI_D0) | ||
1579 | continue; | ||
1521 | pci_pme_wakeup(pme_dev->dev, NULL); | 1580 | pci_pme_wakeup(pme_dev->dev, NULL); |
1522 | } else { | 1581 | } else { |
1523 | list_del(&pme_dev->list); | 1582 | list_del(&pme_dev->list); |
@@ -1744,6 +1803,10 @@ int pci_prepare_to_sleep(struct pci_dev *dev) | |||
1744 | if (target_state == PCI_POWER_ERROR) | 1803 | if (target_state == PCI_POWER_ERROR) |
1745 | return -EIO; | 1804 | return -EIO; |
1746 | 1805 | ||
1806 | /* D3cold during system suspend/hibernate is not supported */ | ||
1807 | if (target_state > PCI_D3hot) | ||
1808 | target_state = PCI_D3hot; | ||
1809 | |||
1747 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); | 1810 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
1748 | 1811 | ||
1749 | error = pci_set_power_state(dev, target_state); | 1812 | error = pci_set_power_state(dev, target_state); |
@@ -1781,12 +1844,16 @@ int pci_finish_runtime_suspend(struct pci_dev *dev) | |||
1781 | if (target_state == PCI_POWER_ERROR) | 1844 | if (target_state == PCI_POWER_ERROR) |
1782 | return -EIO; | 1845 | return -EIO; |
1783 | 1846 | ||
1847 | dev->runtime_d3cold = target_state == PCI_D3cold; | ||
1848 | |||
1784 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); | 1849 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1785 | 1850 | ||
1786 | error = pci_set_power_state(dev, target_state); | 1851 | error = pci_set_power_state(dev, target_state); |
1787 | 1852 | ||
1788 | if (error) | 1853 | if (error) { |
1789 | __pci_enable_wake(dev, target_state, true, false); | 1854 | __pci_enable_wake(dev, target_state, true, false); |
1855 | dev->runtime_d3cold = false; | ||
1856 | } | ||
1790 | 1857 | ||
1791 | return error; | 1858 | return error; |
1792 | } | 1859 | } |
@@ -1856,6 +1923,7 @@ void pci_pm_init(struct pci_dev *dev) | |||
1856 | 1923 | ||
1857 | dev->pm_cap = pm; | 1924 | dev->pm_cap = pm; |
1858 | dev->d3_delay = PCI_PM_D3_WAIT; | 1925 | dev->d3_delay = PCI_PM_D3_WAIT; |
1926 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; | ||
1859 | 1927 | ||
1860 | dev->d1_support = false; | 1928 | dev->d1_support = false; |
1861 | dev->d2_support = false; | 1929 | dev->d2_support = false; |
@@ -1983,7 +2051,7 @@ void pci_enable_ari(struct pci_dev *dev) | |||
1983 | { | 2051 | { |
1984 | int pos; | 2052 | int pos; |
1985 | u32 cap; | 2053 | u32 cap; |
1986 | u16 flags, ctrl; | 2054 | u16 ctrl; |
1987 | struct pci_dev *bridge; | 2055 | struct pci_dev *bridge; |
1988 | 2056 | ||
1989 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) | 2057 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
@@ -1994,18 +2062,14 @@ void pci_enable_ari(struct pci_dev *dev) | |||
1994 | return; | 2062 | return; |
1995 | 2063 | ||
1996 | bridge = dev->bus->self; | 2064 | bridge = dev->bus->self; |
1997 | if (!bridge || !pci_is_pcie(bridge)) | 2065 | if (!bridge) |
1998 | return; | 2066 | return; |
1999 | 2067 | ||
2000 | pos = pci_pcie_cap(bridge); | 2068 | /* ARI is a PCIe cap v2 feature */ |
2069 | pos = pci_pcie_cap2(bridge); | ||
2001 | if (!pos) | 2070 | if (!pos) |
2002 | return; | 2071 | return; |
2003 | 2072 | ||
2004 | /* ARI is a PCIe v2 feature */ | ||
2005 | pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags); | ||
2006 | if ((flags & PCI_EXP_FLAGS_VERS) < 2) | ||
2007 | return; | ||
2008 | |||
2009 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); | 2073 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
2010 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) | 2074 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2011 | return; | 2075 | return; |
@@ -2018,7 +2082,7 @@ void pci_enable_ari(struct pci_dev *dev) | |||
2018 | } | 2082 | } |
2019 | 2083 | ||
2020 | /** | 2084 | /** |
2021 | * pci_enable_ido - enable ID-based ordering on a device | 2085 | * pci_enable_ido - enable ID-based Ordering on a device |
2022 | * @dev: the PCI device | 2086 | * @dev: the PCI device |
2023 | * @type: which types of IDO to enable | 2087 | * @type: which types of IDO to enable |
2024 | * | 2088 | * |
@@ -2031,7 +2095,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type) | |||
2031 | int pos; | 2095 | int pos; |
2032 | u16 ctrl; | 2096 | u16 ctrl; |
2033 | 2097 | ||
2034 | pos = pci_pcie_cap(dev); | 2098 | /* ID-based Ordering is a PCIe cap v2 feature */ |
2099 | pos = pci_pcie_cap2(dev); | ||
2035 | if (!pos) | 2100 | if (!pos) |
2036 | return; | 2101 | return; |
2037 | 2102 | ||
@@ -2054,10 +2119,8 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type) | |||
2054 | int pos; | 2119 | int pos; |
2055 | u16 ctrl; | 2120 | u16 ctrl; |
2056 | 2121 | ||
2057 | if (!pci_is_pcie(dev)) | 2122 | /* ID-based Ordering is a PCIe cap v2 feature */ |
2058 | return; | 2123 | pos = pci_pcie_cap2(dev); |
2059 | |||
2060 | pos = pci_pcie_cap(dev); | ||
2061 | if (!pos) | 2124 | if (!pos) |
2062 | return; | 2125 | return; |
2063 | 2126 | ||
@@ -2096,10 +2159,8 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) | |||
2096 | u16 ctrl; | 2159 | u16 ctrl; |
2097 | int ret; | 2160 | int ret; |
2098 | 2161 | ||
2099 | if (!pci_is_pcie(dev)) | 2162 | /* OBFF is a PCIe cap v2 feature */ |
2100 | return -ENOTSUPP; | 2163 | pos = pci_pcie_cap2(dev); |
2101 | |||
2102 | pos = pci_pcie_cap(dev); | ||
2103 | if (!pos) | 2164 | if (!pos) |
2104 | return -ENOTSUPP; | 2165 | return -ENOTSUPP; |
2105 | 2166 | ||
@@ -2108,7 +2169,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) | |||
2108 | return -ENOTSUPP; /* no OBFF support at all */ | 2169 | return -ENOTSUPP; /* no OBFF support at all */ |
2109 | 2170 | ||
2110 | /* Make sure the topology supports OBFF as well */ | 2171 | /* Make sure the topology supports OBFF as well */ |
2111 | if (dev->bus) { | 2172 | if (dev->bus->self) { |
2112 | ret = pci_enable_obff(dev->bus->self, type); | 2173 | ret = pci_enable_obff(dev->bus->self, type); |
2113 | if (ret) | 2174 | if (ret) |
2114 | return ret; | 2175 | return ret; |
@@ -2149,10 +2210,8 @@ void pci_disable_obff(struct pci_dev *dev) | |||
2149 | int pos; | 2210 | int pos; |
2150 | u16 ctrl; | 2211 | u16 ctrl; |
2151 | 2212 | ||
2152 | if (!pci_is_pcie(dev)) | 2213 | /* OBFF is a PCIe cap v2 feature */ |
2153 | return; | 2214 | pos = pci_pcie_cap2(dev); |
2154 | |||
2155 | pos = pci_pcie_cap(dev); | ||
2156 | if (!pos) | 2215 | if (!pos) |
2157 | return; | 2216 | return; |
2158 | 2217 | ||
@@ -2169,15 +2228,13 @@ EXPORT_SYMBOL(pci_disable_obff); | |||
2169 | * RETURNS: | 2228 | * RETURNS: |
2170 | * True if @dev supports latency tolerance reporting, false otherwise. | 2229 | * True if @dev supports latency tolerance reporting, false otherwise. |
2171 | */ | 2230 | */ |
2172 | bool pci_ltr_supported(struct pci_dev *dev) | 2231 | static bool pci_ltr_supported(struct pci_dev *dev) |
2173 | { | 2232 | { |
2174 | int pos; | 2233 | int pos; |
2175 | u32 cap; | 2234 | u32 cap; |
2176 | 2235 | ||
2177 | if (!pci_is_pcie(dev)) | 2236 | /* LTR is a PCIe cap v2 feature */ |
2178 | return false; | 2237 | pos = pci_pcie_cap2(dev); |
2179 | |||
2180 | pos = pci_pcie_cap(dev); | ||
2181 | if (!pos) | 2238 | if (!pos) |
2182 | return false; | 2239 | return false; |
2183 | 2240 | ||
@@ -2185,7 +2242,6 @@ bool pci_ltr_supported(struct pci_dev *dev) | |||
2185 | 2242 | ||
2186 | return cap & PCI_EXP_DEVCAP2_LTR; | 2243 | return cap & PCI_EXP_DEVCAP2_LTR; |
2187 | } | 2244 | } |
2188 | EXPORT_SYMBOL(pci_ltr_supported); | ||
2189 | 2245 | ||
2190 | /** | 2246 | /** |
2191 | * pci_enable_ltr - enable latency tolerance reporting | 2247 | * pci_enable_ltr - enable latency tolerance reporting |
@@ -2206,7 +2262,8 @@ int pci_enable_ltr(struct pci_dev *dev) | |||
2206 | if (!pci_ltr_supported(dev)) | 2262 | if (!pci_ltr_supported(dev)) |
2207 | return -ENOTSUPP; | 2263 | return -ENOTSUPP; |
2208 | 2264 | ||
2209 | pos = pci_pcie_cap(dev); | 2265 | /* LTR is a PCIe cap v2 feature */ |
2266 | pos = pci_pcie_cap2(dev); | ||
2210 | if (!pos) | 2267 | if (!pos) |
2211 | return -ENOTSUPP; | 2268 | return -ENOTSUPP; |
2212 | 2269 | ||
@@ -2215,7 +2272,7 @@ int pci_enable_ltr(struct pci_dev *dev) | |||
2215 | return -EINVAL; | 2272 | return -EINVAL; |
2216 | 2273 | ||
2217 | /* Enable upstream ports first */ | 2274 | /* Enable upstream ports first */ |
2218 | if (dev->bus) { | 2275 | if (dev->bus->self) { |
2219 | ret = pci_enable_ltr(dev->bus->self); | 2276 | ret = pci_enable_ltr(dev->bus->self); |
2220 | if (ret) | 2277 | if (ret) |
2221 | return ret; | 2278 | return ret; |
@@ -2241,7 +2298,8 @@ void pci_disable_ltr(struct pci_dev *dev) | |||
2241 | if (!pci_ltr_supported(dev)) | 2298 | if (!pci_ltr_supported(dev)) |
2242 | return; | 2299 | return; |
2243 | 2300 | ||
2244 | pos = pci_pcie_cap(dev); | 2301 | /* LTR is a PCIe cap v2 feature */ |
2302 | pos = pci_pcie_cap2(dev); | ||
2245 | if (!pos) | 2303 | if (!pos) |
2246 | return; | 2304 | return; |
2247 | 2305 | ||
@@ -2360,6 +2418,75 @@ void pci_enable_acs(struct pci_dev *dev) | |||
2360 | } | 2418 | } |
2361 | 2419 | ||
2362 | /** | 2420 | /** |
2421 | * pci_acs_enabled - test ACS against required flags for a given device | ||
2422 | * @pdev: device to test | ||
2423 | * @acs_flags: required PCI ACS flags | ||
2424 | * | ||
2425 | * Return true if the device supports the provided flags. Automatically | ||
2426 | * filters out flags that are not implemented on multifunction devices. | ||
2427 | */ | ||
2428 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | ||
2429 | { | ||
2430 | int pos, ret; | ||
2431 | u16 ctrl; | ||
2432 | |||
2433 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | ||
2434 | if (ret >= 0) | ||
2435 | return ret > 0; | ||
2436 | |||
2437 | if (!pci_is_pcie(pdev)) | ||
2438 | return false; | ||
2439 | |||
2440 | /* Filter out flags not applicable to multifunction */ | ||
2441 | if (pdev->multifunction) | ||
2442 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | | ||
2443 | PCI_ACS_EC | PCI_ACS_DT); | ||
2444 | |||
2445 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM || | ||
2446 | pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | ||
2447 | pdev->multifunction) { | ||
2448 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | ||
2449 | if (!pos) | ||
2450 | return false; | ||
2451 | |||
2452 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); | ||
2453 | if ((ctrl & acs_flags) != acs_flags) | ||
2454 | return false; | ||
2455 | } | ||
2456 | |||
2457 | return true; | ||
2458 | } | ||
2459 | |||
2460 | /** | ||
2461 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | ||
2462 | * @start: starting downstream device | ||
2463 | * @end: ending upstream device or NULL to search to the root bus | ||
2464 | * @acs_flags: required flags | ||
2465 | * | ||
2466 | * Walk up a device tree from start to end testing PCI ACS support. If | ||
2467 | * any step along the way does not support the required flags, return false. | ||
2468 | */ | ||
2469 | bool pci_acs_path_enabled(struct pci_dev *start, | ||
2470 | struct pci_dev *end, u16 acs_flags) | ||
2471 | { | ||
2472 | struct pci_dev *pdev, *parent = start; | ||
2473 | |||
2474 | do { | ||
2475 | pdev = parent; | ||
2476 | |||
2477 | if (!pci_acs_enabled(pdev, acs_flags)) | ||
2478 | return false; | ||
2479 | |||
2480 | if (pci_is_root_bus(pdev->bus)) | ||
2481 | return (end == NULL); | ||
2482 | |||
2483 | parent = pdev->bus->self; | ||
2484 | } while (pdev != end); | ||
2485 | |||
2486 | return true; | ||
2487 | } | ||
2488 | |||
2489 | /** | ||
2363 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | 2490 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge |
2364 | * @dev: the PCI device | 2491 | * @dev: the PCI device |
2365 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) | 2492 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) |
@@ -2888,6 +3015,9 @@ bool pci_intx_mask_supported(struct pci_dev *dev) | |||
2888 | bool mask_supported = false; | 3015 | bool mask_supported = false; |
2889 | u16 orig, new; | 3016 | u16 orig, new; |
2890 | 3017 | ||
3018 | if (dev->broken_intx_masking) | ||
3019 | return false; | ||
3020 | |||
2891 | pci_cfg_access_lock(dev); | 3021 | pci_cfg_access_lock(dev); |
2892 | 3022 | ||
2893 | pci_read_config_word(dev, PCI_COMMAND, &orig); | 3023 | pci_read_config_word(dev, PCI_COMMAND, &orig); |
@@ -3407,8 +3537,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |||
3407 | 3537 | ||
3408 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | 3538 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; |
3409 | if (o != v) { | 3539 | if (o != v) { |
3410 | if (v > o && dev->bus && | 3540 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
3411 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | ||
3412 | return -EIO; | 3541 | return -EIO; |
3413 | 3542 | ||
3414 | cmd &= ~PCI_X_CMD_MAX_READ; | 3543 | cmd &= ~PCI_X_CMD_MAX_READ; |
@@ -3863,7 +3992,7 @@ static void __devinit pci_no_domains(void) | |||
3863 | * greater than 0xff). This is the default implementation. Architecture | 3992 | * greater than 0xff). This is the default implementation. Architecture |
3864 | * implementations can override this. | 3993 | * implementations can override this. |
3865 | */ | 3994 | */ |
3866 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) | 3995 | int __weak pci_ext_cfg_avail(struct pci_dev *dev) |
3867 | { | 3996 | { |
3868 | return 1; | 3997 | return 1; |
3869 | } | 3998 | } |