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path: root/drivers/pci/pci.c
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-rw-r--r--drivers/pci/pci.c358
1 files changed, 94 insertions, 264 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index ab4bf5a4c2f1..54858838f098 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -254,52 +254,17 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
254} 254}
255 255
256/** 256/**
257 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure 257 * pci_find_next_ext_capability - Find an extended capability
258 * @dev: PCI device to check
259 *
260 * Like pci_pcie_cap() but also checks that the PCIe capability version is
261 * >= 2. Note that v1 capability structures could be sparse in that not
262 * all register fields were required. v2 requires the entire structure to
263 * be present size wise, while still allowing for non-implemented registers
264 * to exist but they must be hardwired to 0.
265 *
266 * Due to the differences in the versions of capability structures, one
267 * must be careful not to try and access non-existant registers that may
268 * exist in early versions - v1 - of Express devices.
269 *
270 * Returns the offset of the PCIe capability structure as long as the
271 * capability version is >= 2; otherwise 0 is returned.
272 */
273static int pci_pcie_cap2(struct pci_dev *dev)
274{
275 u16 flags;
276 int pos;
277
278 pos = pci_pcie_cap(dev);
279 if (pos) {
280 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
281 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
282 pos = 0;
283 }
284
285 return pos;
286}
287
288/**
289 * pci_find_ext_capability - Find an extended capability
290 * @dev: PCI device to query 258 * @dev: PCI device to query
259 * @start: address at which to start looking (0 to start at beginning of list)
291 * @cap: capability code 260 * @cap: capability code
292 * 261 *
293 * Returns the address of the requested extended capability structure 262 * Returns the address of the next matching extended capability structure
294 * within the device's PCI configuration space or 0 if the device does 263 * within the device's PCI configuration space or 0 if the device does
295 * not support it. Possible values for @cap: 264 * not support it. Some capabilities can occur several times, e.g., the
296 * 265 * vendor-specific capability, and this provides a way to find them all.
297 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
298 * %PCI_EXT_CAP_ID_VC Virtual Channel
299 * %PCI_EXT_CAP_ID_DSN Device Serial Number
300 * %PCI_EXT_CAP_ID_PWR Power Budgeting
301 */ 266 */
302int pci_find_ext_capability(struct pci_dev *dev, int cap) 267int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
303{ 268{
304 u32 header; 269 u32 header;
305 int ttl; 270 int ttl;
@@ -311,6 +276,9 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
311 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
312 return 0; 277 return 0;
313 278
279 if (start)
280 pos = start;
281
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
315 return 0; 283 return 0;
316 284
@@ -322,7 +290,7 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
322 return 0; 290 return 0;
323 291
324 while (ttl-- > 0) { 292 while (ttl-- > 0) {
325 if (PCI_EXT_CAP_ID(header) == cap) 293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
326 return pos; 294 return pos;
327 295
328 pos = PCI_EXT_CAP_NEXT(header); 296 pos = PCI_EXT_CAP_NEXT(header);
@@ -335,6 +303,26 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
335 303
336 return 0; 304 return 0;
337} 305}
306EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
307
308/**
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
312 *
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
316 *
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
321 */
322int pci_find_ext_capability(struct pci_dev *dev, int cap)
323{
324 return pci_find_next_ext_capability(dev, 0, cap);
325}
338EXPORT_SYMBOL_GPL(pci_find_ext_capability); 326EXPORT_SYMBOL_GPL(pci_find_ext_capability);
339 327
340static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 328static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
@@ -854,21 +842,6 @@ EXPORT_SYMBOL(pci_choose_state);
854 842
855#define PCI_EXP_SAVE_REGS 7 843#define PCI_EXP_SAVE_REGS 7
856 844
857#define pcie_cap_has_devctl(type, flags) 1
858#define pcie_cap_has_lnkctl(type, flags) \
859 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
860 (type == PCI_EXP_TYPE_ROOT_PORT || \
861 type == PCI_EXP_TYPE_ENDPOINT || \
862 type == PCI_EXP_TYPE_LEG_END))
863#define pcie_cap_has_sltctl(type, flags) \
864 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
865 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
866 (type == PCI_EXP_TYPE_DOWNSTREAM && \
867 (flags & PCI_EXP_FLAGS_SLOT))))
868#define pcie_cap_has_rtctl(type, flags) \
869 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
870 (type == PCI_EXP_TYPE_ROOT_PORT || \
871 type == PCI_EXP_TYPE_RC_EC))
872 845
873static struct pci_cap_saved_state *pci_find_saved_cap( 846static struct pci_cap_saved_state *pci_find_saved_cap(
874 struct pci_dev *pci_dev, char cap) 847 struct pci_dev *pci_dev, char cap)
@@ -885,13 +858,11 @@ static struct pci_cap_saved_state *pci_find_saved_cap(
885 858
886static int pci_save_pcie_state(struct pci_dev *dev) 859static int pci_save_pcie_state(struct pci_dev *dev)
887{ 860{
888 int pos, i = 0; 861 int i = 0;
889 struct pci_cap_saved_state *save_state; 862 struct pci_cap_saved_state *save_state;
890 u16 *cap; 863 u16 *cap;
891 u16 flags;
892 864
893 pos = pci_pcie_cap(dev); 865 if (!pci_is_pcie(dev))
894 if (!pos)
895 return 0; 866 return 0;
896 867
897 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 868 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
@@ -899,60 +870,37 @@ static int pci_save_pcie_state(struct pci_dev *dev)
899 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 870 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
900 return -ENOMEM; 871 return -ENOMEM;
901 } 872 }
902 cap = (u16 *)&save_state->cap.data[0];
903
904 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
905 873
906 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 874 cap = (u16 *)&save_state->cap.data[0];
907 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 875 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
908 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 876 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
909 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 877 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
910 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 878 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
911 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 879 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
912 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 880 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
913 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 881 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
914
915 pos = pci_pcie_cap2(dev);
916 if (!pos)
917 return 0;
918 882
919 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
920 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
921 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
922 return 0; 883 return 0;
923} 884}
924 885
925static void pci_restore_pcie_state(struct pci_dev *dev) 886static void pci_restore_pcie_state(struct pci_dev *dev)
926{ 887{
927 int i = 0, pos; 888 int i = 0;
928 struct pci_cap_saved_state *save_state; 889 struct pci_cap_saved_state *save_state;
929 u16 *cap; 890 u16 *cap;
930 u16 flags;
931 891
932 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 892 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
933 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 893 if (!save_state)
934 if (!save_state || pos <= 0)
935 return;
936 cap = (u16 *)&save_state->cap.data[0];
937
938 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
939
940 if (pcie_cap_has_devctl(dev->pcie_type, flags))
941 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
942 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
943 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
944 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
945 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
946 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
947 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
948
949 pos = pci_pcie_cap2(dev);
950 if (!pos)
951 return; 894 return;
952 895
953 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 896 cap = (u16 *)&save_state->cap.data[0];
954 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 897 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
955 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 898 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
899 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
900 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
901 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
902 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
903 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
956} 904}
957 905
958 906
@@ -1543,7 +1491,7 @@ void pci_pme_wakeup_bus(struct pci_bus *bus)
1543 1491
1544/** 1492/**
1545 * pci_wakeup - Wake up a PCI device 1493 * pci_wakeup - Wake up a PCI device
1546 * @dev: Device to handle. 1494 * @pci_dev: Device to handle.
1547 * @ign: ignored parameter 1495 * @ign: ignored parameter
1548 */ 1496 */
1549static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 1497static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
@@ -2067,35 +2015,24 @@ void pci_free_cap_save_buffers(struct pci_dev *dev)
2067 */ 2015 */
2068void pci_enable_ari(struct pci_dev *dev) 2016void pci_enable_ari(struct pci_dev *dev)
2069{ 2017{
2070 int pos;
2071 u32 cap; 2018 u32 cap;
2072 u16 ctrl;
2073 struct pci_dev *bridge; 2019 struct pci_dev *bridge;
2074 2020
2075 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2021 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2076 return; 2022 return;
2077 2023
2078 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2024 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
2079 if (!pos)
2080 return; 2025 return;
2081 2026
2082 bridge = dev->bus->self; 2027 bridge = dev->bus->self;
2083 if (!bridge) 2028 if (!bridge)
2084 return; 2029 return;
2085 2030
2086 /* ARI is a PCIe cap v2 feature */ 2031 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2087 pos = pci_pcie_cap2(bridge);
2088 if (!pos)
2089 return;
2090
2091 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2092 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2032 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2093 return; 2033 return;
2094 2034
2095 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); 2035 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
2096 ctrl |= PCI_EXP_DEVCTL2_ARI;
2097 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
2098
2099 bridge->ari_enabled = 1; 2036 bridge->ari_enabled = 1;
2100} 2037}
2101 2038
@@ -2110,20 +2047,14 @@ void pci_enable_ari(struct pci_dev *dev)
2110 */ 2047 */
2111void pci_enable_ido(struct pci_dev *dev, unsigned long type) 2048void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2112{ 2049{
2113 int pos; 2050 u16 ctrl = 0;
2114 u16 ctrl;
2115 2051
2116 /* ID-based Ordering is a PCIe cap v2 feature */
2117 pos = pci_pcie_cap2(dev);
2118 if (!pos)
2119 return;
2120
2121 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2122 if (type & PCI_EXP_IDO_REQUEST) 2052 if (type & PCI_EXP_IDO_REQUEST)
2123 ctrl |= PCI_EXP_IDO_REQ_EN; 2053 ctrl |= PCI_EXP_IDO_REQ_EN;
2124 if (type & PCI_EXP_IDO_COMPLETION) 2054 if (type & PCI_EXP_IDO_COMPLETION)
2125 ctrl |= PCI_EXP_IDO_CMP_EN; 2055 ctrl |= PCI_EXP_IDO_CMP_EN;
2126 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2056 if (ctrl)
2057 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2127} 2058}
2128EXPORT_SYMBOL(pci_enable_ido); 2059EXPORT_SYMBOL(pci_enable_ido);
2129 2060
@@ -2134,20 +2065,14 @@ EXPORT_SYMBOL(pci_enable_ido);
2134 */ 2065 */
2135void pci_disable_ido(struct pci_dev *dev, unsigned long type) 2066void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2136{ 2067{
2137 int pos; 2068 u16 ctrl = 0;
2138 u16 ctrl;
2139 2069
2140 /* ID-based Ordering is a PCIe cap v2 feature */
2141 pos = pci_pcie_cap2(dev);
2142 if (!pos)
2143 return;
2144
2145 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2146 if (type & PCI_EXP_IDO_REQUEST) 2070 if (type & PCI_EXP_IDO_REQUEST)
2147 ctrl &= ~PCI_EXP_IDO_REQ_EN; 2071 ctrl |= PCI_EXP_IDO_REQ_EN;
2148 if (type & PCI_EXP_IDO_COMPLETION) 2072 if (type & PCI_EXP_IDO_COMPLETION)
2149 ctrl &= ~PCI_EXP_IDO_CMP_EN; 2073 ctrl |= PCI_EXP_IDO_CMP_EN;
2150 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2074 if (ctrl)
2075 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2151} 2076}
2152EXPORT_SYMBOL(pci_disable_ido); 2077EXPORT_SYMBOL(pci_disable_ido);
2153 2078
@@ -2172,17 +2097,11 @@ EXPORT_SYMBOL(pci_disable_ido);
2172 */ 2097 */
2173int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) 2098int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2174{ 2099{
2175 int pos;
2176 u32 cap; 2100 u32 cap;
2177 u16 ctrl; 2101 u16 ctrl;
2178 int ret; 2102 int ret;
2179 2103
2180 /* OBFF is a PCIe cap v2 feature */ 2104 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2181 pos = pci_pcie_cap2(dev);
2182 if (!pos)
2183 return -ENOTSUPP;
2184
2185 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2186 if (!(cap & PCI_EXP_OBFF_MASK)) 2105 if (!(cap & PCI_EXP_OBFF_MASK))
2187 return -ENOTSUPP; /* no OBFF support at all */ 2106 return -ENOTSUPP; /* no OBFF support at all */
2188 2107
@@ -2193,7 +2112,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2193 return ret; 2112 return ret;
2194 } 2113 }
2195 2114
2196 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2115 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2197 if (cap & PCI_EXP_OBFF_WAKE) 2116 if (cap & PCI_EXP_OBFF_WAKE)
2198 ctrl |= PCI_EXP_OBFF_WAKE_EN; 2117 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2199 else { 2118 else {
@@ -2211,7 +2130,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2211 return -ENOTSUPP; 2130 return -ENOTSUPP;
2212 } 2131 }
2213 } 2132 }
2214 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2133 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2215 2134
2216 return 0; 2135 return 0;
2217} 2136}
@@ -2225,17 +2144,7 @@ EXPORT_SYMBOL(pci_enable_obff);
2225 */ 2144 */
2226void pci_disable_obff(struct pci_dev *dev) 2145void pci_disable_obff(struct pci_dev *dev)
2227{ 2146{
2228 int pos; 2147 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
2229 u16 ctrl;
2230
2231 /* OBFF is a PCIe cap v2 feature */
2232 pos = pci_pcie_cap2(dev);
2233 if (!pos)
2234 return;
2235
2236 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2237 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2238 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2239} 2148}
2240EXPORT_SYMBOL(pci_disable_obff); 2149EXPORT_SYMBOL(pci_disable_obff);
2241 2150
@@ -2248,15 +2157,9 @@ EXPORT_SYMBOL(pci_disable_obff);
2248 */ 2157 */
2249static bool pci_ltr_supported(struct pci_dev *dev) 2158static bool pci_ltr_supported(struct pci_dev *dev)
2250{ 2159{
2251 int pos;
2252 u32 cap; 2160 u32 cap;
2253 2161
2254 /* LTR is a PCIe cap v2 feature */ 2162 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2255 pos = pci_pcie_cap2(dev);
2256 if (!pos)
2257 return false;
2258
2259 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2260 2163
2261 return cap & PCI_EXP_DEVCAP2_LTR; 2164 return cap & PCI_EXP_DEVCAP2_LTR;
2262} 2165}
@@ -2273,22 +2176,15 @@ static bool pci_ltr_supported(struct pci_dev *dev)
2273 */ 2176 */
2274int pci_enable_ltr(struct pci_dev *dev) 2177int pci_enable_ltr(struct pci_dev *dev)
2275{ 2178{
2276 int pos;
2277 u16 ctrl;
2278 int ret; 2179 int ret;
2279 2180
2280 if (!pci_ltr_supported(dev))
2281 return -ENOTSUPP;
2282
2283 /* LTR is a PCIe cap v2 feature */
2284 pos = pci_pcie_cap2(dev);
2285 if (!pos)
2286 return -ENOTSUPP;
2287
2288 /* Only primary function can enable/disable LTR */ 2181 /* Only primary function can enable/disable LTR */
2289 if (PCI_FUNC(dev->devfn) != 0) 2182 if (PCI_FUNC(dev->devfn) != 0)
2290 return -EINVAL; 2183 return -EINVAL;
2291 2184
2185 if (!pci_ltr_supported(dev))
2186 return -ENOTSUPP;
2187
2292 /* Enable upstream ports first */ 2188 /* Enable upstream ports first */
2293 if (dev->bus->self) { 2189 if (dev->bus->self) {
2294 ret = pci_enable_ltr(dev->bus->self); 2190 ret = pci_enable_ltr(dev->bus->self);
@@ -2296,11 +2192,7 @@ int pci_enable_ltr(struct pci_dev *dev)
2296 return ret; 2192 return ret;
2297 } 2193 }
2298 2194
2299 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2195 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2300 ctrl |= PCI_EXP_LTR_EN;
2301 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2302
2303 return 0;
2304} 2196}
2305EXPORT_SYMBOL(pci_enable_ltr); 2197EXPORT_SYMBOL(pci_enable_ltr);
2306 2198
@@ -2310,24 +2202,14 @@ EXPORT_SYMBOL(pci_enable_ltr);
2310 */ 2202 */
2311void pci_disable_ltr(struct pci_dev *dev) 2203void pci_disable_ltr(struct pci_dev *dev)
2312{ 2204{
2313 int pos;
2314 u16 ctrl;
2315
2316 if (!pci_ltr_supported(dev))
2317 return;
2318
2319 /* LTR is a PCIe cap v2 feature */
2320 pos = pci_pcie_cap2(dev);
2321 if (!pos)
2322 return;
2323
2324 /* Only primary function can enable/disable LTR */ 2205 /* Only primary function can enable/disable LTR */
2325 if (PCI_FUNC(dev->devfn) != 0) 2206 if (PCI_FUNC(dev->devfn) != 0)
2326 return; 2207 return;
2327 2208
2328 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2209 if (!pci_ltr_supported(dev))
2329 ctrl &= ~PCI_EXP_LTR_EN; 2210 return;
2330 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2211
2212 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2331} 2213}
2332EXPORT_SYMBOL(pci_disable_ltr); 2214EXPORT_SYMBOL(pci_disable_ltr);
2333 2215
@@ -2410,9 +2292,6 @@ void pci_enable_acs(struct pci_dev *dev)
2410 if (!pci_acs_enable) 2292 if (!pci_acs_enable)
2411 return; 2293 return;
2412 2294
2413 if (!pci_is_pcie(dev))
2414 return;
2415
2416 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2295 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2417 if (!pos) 2296 if (!pos)
2418 return; 2297 return;
@@ -2460,8 +2339,8 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2460 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | 2339 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2461 PCI_ACS_EC | PCI_ACS_DT); 2340 PCI_ACS_EC | PCI_ACS_DT);
2462 2341
2463 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM || 2342 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2464 pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2343 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
2465 pdev->multifunction) { 2344 pdev->multifunction) {
2466 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2345 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2467 if (!pos) 2346 if (!pos)
@@ -3177,15 +3056,10 @@ EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3177static int pcie_flr(struct pci_dev *dev, int probe) 3056static int pcie_flr(struct pci_dev *dev, int probe)
3178{ 3057{
3179 int i; 3058 int i;
3180 int pos;
3181 u32 cap; 3059 u32 cap;
3182 u16 status, control; 3060 u16 status;
3183
3184 pos = pci_pcie_cap(dev);
3185 if (!pos)
3186 return -ENOTTY;
3187 3061
3188 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 3062 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3189 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3063 if (!(cap & PCI_EXP_DEVCAP_FLR))
3190 return -ENOTTY; 3064 return -ENOTTY;
3191 3065
@@ -3197,7 +3071,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
3197 if (i) 3071 if (i)
3198 msleep((1 << (i - 1)) * 100); 3072 msleep((1 << (i - 1)) * 100);
3199 3073
3200 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 3074 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3201 if (!(status & PCI_EXP_DEVSTA_TRPND)) 3075 if (!(status & PCI_EXP_DEVSTA_TRPND))
3202 goto clear; 3076 goto clear;
3203 } 3077 }
@@ -3206,9 +3080,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
3206 "proceeding with reset anyway\n"); 3080 "proceeding with reset anyway\n");
3207 3081
3208clear: 3082clear:
3209 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); 3083 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3210 control |= PCI_EXP_DEVCTL_BCR_FLR;
3211 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
3212 3084
3213 msleep(100); 3085 msleep(100);
3214 3086
@@ -3576,18 +3448,11 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
3576 */ 3448 */
3577int pcie_get_readrq(struct pci_dev *dev) 3449int pcie_get_readrq(struct pci_dev *dev)
3578{ 3450{
3579 int ret, cap;
3580 u16 ctl; 3451 u16 ctl;
3581 3452
3582 cap = pci_pcie_cap(dev); 3453 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3583 if (!cap)
3584 return -EINVAL;
3585
3586 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3587 if (!ret)
3588 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3589 3454
3590 return ret; 3455 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3591} 3456}
3592EXPORT_SYMBOL(pcie_get_readrq); 3457EXPORT_SYMBOL(pcie_get_readrq);
3593 3458
@@ -3601,19 +3466,11 @@ EXPORT_SYMBOL(pcie_get_readrq);
3601 */ 3466 */
3602int pcie_set_readrq(struct pci_dev *dev, int rq) 3467int pcie_set_readrq(struct pci_dev *dev, int rq)
3603{ 3468{
3604 int cap, err = -EINVAL; 3469 u16 v;
3605 u16 ctl, v;
3606 3470
3607 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 3471 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3608 goto out; 3472 return -EINVAL;
3609
3610 cap = pci_pcie_cap(dev);
3611 if (!cap)
3612 goto out;
3613 3473
3614 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3615 if (err)
3616 goto out;
3617 /* 3474 /*
3618 * If using the "performance" PCIe config, we clamp the 3475 * If using the "performance" PCIe config, we clamp the
3619 * read rq size to the max packet size to prevent the 3476 * read rq size to the max packet size to prevent the
@@ -3631,14 +3488,8 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
3631 3488
3632 v = (ffs(rq) - 8) << 12; 3489 v = (ffs(rq) - 8) << 12;
3633 3490
3634 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 3491 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3635 ctl &= ~PCI_EXP_DEVCTL_READRQ; 3492 PCI_EXP_DEVCTL_READRQ, v);
3636 ctl |= v;
3637 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3638 }
3639
3640out:
3641 return err;
3642} 3493}
3643EXPORT_SYMBOL(pcie_set_readrq); 3494EXPORT_SYMBOL(pcie_set_readrq);
3644 3495
@@ -3651,18 +3502,11 @@ EXPORT_SYMBOL(pcie_set_readrq);
3651 */ 3502 */
3652int pcie_get_mps(struct pci_dev *dev) 3503int pcie_get_mps(struct pci_dev *dev)
3653{ 3504{
3654 int ret, cap;
3655 u16 ctl; 3505 u16 ctl;
3656 3506
3657 cap = pci_pcie_cap(dev); 3507 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3658 if (!cap)
3659 return -EINVAL;
3660
3661 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3662 if (!ret)
3663 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3664 3508
3665 return ret; 3509 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3666} 3510}
3667 3511
3668/** 3512/**
@@ -3675,32 +3519,18 @@ int pcie_get_mps(struct pci_dev *dev)
3675 */ 3519 */
3676int pcie_set_mps(struct pci_dev *dev, int mps) 3520int pcie_set_mps(struct pci_dev *dev, int mps)
3677{ 3521{
3678 int cap, err = -EINVAL; 3522 u16 v;
3679 u16 ctl, v;
3680 3523
3681 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3524 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3682 goto out; 3525 return -EINVAL;
3683 3526
3684 v = ffs(mps) - 8; 3527 v = ffs(mps) - 8;
3685 if (v > dev->pcie_mpss) 3528 if (v > dev->pcie_mpss)
3686 goto out; 3529 return -EINVAL;
3687 v <<= 5; 3530 v <<= 5;
3688 3531
3689 cap = pci_pcie_cap(dev); 3532 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3690 if (!cap) 3533 PCI_EXP_DEVCTL_PAYLOAD, v);
3691 goto out;
3692
3693 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3694 if (err)
3695 goto out;
3696
3697 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3698 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3699 ctl |= v;
3700 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3701 }
3702out:
3703 return err;
3704} 3534}
3705 3535
3706/** 3536/**
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 16:44:34 -0500