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path: root/drivers/pci/pci.c
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-rw-r--r--drivers/pci/pci.c104
1 files changed, 91 insertions, 13 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index c62d2f043397..ccff633a3948 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -222,6 +222,37 @@ pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
222} 222}
223 223
224/** 224/**
225 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
226 * @dev: PCI device to have its BARs restored
227 *
228 * Restore the BAR values for a given device, so as to make it
229 * accessible by its driver.
230 */
231void
232pci_restore_bars(struct pci_dev *dev)
233{
234 int i, numres;
235
236 switch (dev->hdr_type) {
237 case PCI_HEADER_TYPE_NORMAL:
238 numres = 6;
239 break;
240 case PCI_HEADER_TYPE_BRIDGE:
241 numres = 2;
242 break;
243 case PCI_HEADER_TYPE_CARDBUS:
244 numres = 1;
245 break;
246 default:
247 /* Should never get here, but just in case... */
248 return;
249 }
250
251 for (i = 0; i < numres; i ++)
252 pci_update_resource(dev, &dev->resource[i], i);
253}
254
255/**
225 * pci_set_power_state - Set the power state of a PCI device 256 * pci_set_power_state - Set the power state of a PCI device
226 * @dev: PCI device to be suspended 257 * @dev: PCI device to be suspended
227 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 258 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
@@ -239,7 +270,7 @@ int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
239int 270int
240pci_set_power_state(struct pci_dev *dev, pci_power_t state) 271pci_set_power_state(struct pci_dev *dev, pci_power_t state)
241{ 272{
242 int pm; 273 int pm, need_restore = 0;
243 u16 pmcsr, pmc; 274 u16 pmcsr, pmc;
244 275
245 /* bound the state we're entering */ 276 /* bound the state we're entering */
@@ -263,7 +294,7 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
263 return -EIO; 294 return -EIO;
264 295
265 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 296 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
266 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) { 297 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
267 printk(KERN_DEBUG 298 printk(KERN_DEBUG
268 "PCI: %s has unsupported PM cap regs version (%u)\n", 299 "PCI: %s has unsupported PM cap regs version (%u)\n",
269 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 300 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
@@ -271,21 +302,22 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
271 } 302 }
272 303
273 /* check if this device supports the desired state */ 304 /* check if this device supports the desired state */
274 if (state == PCI_D1 || state == PCI_D2) { 305 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
275 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 306 return -EIO;
276 return -EIO; 307 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
277 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 308 return -EIO;
278 return -EIO; 309
279 } 310 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
280 311
281 /* If we're in D3, force entire word to 0. 312 /* If we're in D3, force entire word to 0.
282 * This doesn't affect PME_Status, disables PME_En, and 313 * This doesn't affect PME_Status, disables PME_En, and
283 * sets PowerState to 0. 314 * sets PowerState to 0.
284 */ 315 */
285 if (dev->current_state >= PCI_D3hot) 316 if (dev->current_state >= PCI_D3hot) {
317 if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
318 need_restore = 1;
286 pmcsr = 0; 319 pmcsr = 0;
287 else { 320 } else {
288 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
289 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 321 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
290 pmcsr |= state; 322 pmcsr |= state;
291 } 323 }
@@ -308,6 +340,22 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
308 platform_pci_set_power_state(dev, state); 340 platform_pci_set_power_state(dev, state);
309 341
310 dev->current_state = state; 342 dev->current_state = state;
343
344 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
345 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
346 * from D3hot to D0 _may_ perform an internal reset, thereby
347 * going to "D0 Uninitialized" rather than "D0 Initialized".
348 * For example, at least some versions of the 3c905B and the
349 * 3c556B exhibit this behaviour.
350 *
351 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
352 * devices in a D3hot state at boot. Consequently, we need to
353 * restore at least the BARs so that the device will be
354 * accessible to its driver.
355 */
356 if (need_restore)
357 pci_restore_bars(dev);
358
311 return 0; 359 return 0;
312} 360}
313 361
@@ -394,8 +442,11 @@ pci_enable_device_bars(struct pci_dev *dev, int bars)
394{ 442{
395 int err; 443 int err;
396 444
397 pci_set_power_state(dev, PCI_D0); 445 err = pci_set_power_state(dev, PCI_D0);
398 if ((err = pcibios_enable_device(dev, bars)) < 0) 446 if (err < 0 && err != -EIO)
447 return err;
448 err = pcibios_enable_device(dev, bars);
449 if (err < 0)
399 return err; 450 return err;
400 return 0; 451 return 0;
401} 452}
@@ -747,6 +798,31 @@ pci_clear_mwi(struct pci_dev *dev)
747 } 798 }
748} 799}
749 800
801/**
802 * pci_intx - enables/disables PCI INTx for device dev
803 * @dev: the PCI device to operate on
804 * @enable: boolean
805 *
806 * Enables/disables PCI INTx for device dev
807 */
808void
809pci_intx(struct pci_dev *pdev, int enable)
810{
811 u16 pci_command, new;
812
813 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
814
815 if (enable) {
816 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
817 } else {
818 new = pci_command | PCI_COMMAND_INTX_DISABLE;
819 }
820
821 if (new != pci_command) {
822 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
823 }
824}
825
750#ifndef HAVE_ARCH_PCI_SET_DMA_MASK 826#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
751/* 827/*
752 * These can be overridden by arch-specific implementations 828 * These can be overridden by arch-specific implementations
@@ -809,6 +885,7 @@ struct pci_dev *isa_bridge;
809EXPORT_SYMBOL(isa_bridge); 885EXPORT_SYMBOL(isa_bridge);
810#endif 886#endif
811 887
888EXPORT_SYMBOL_GPL(pci_restore_bars);
812EXPORT_SYMBOL(pci_enable_device_bars); 889EXPORT_SYMBOL(pci_enable_device_bars);
813EXPORT_SYMBOL(pci_enable_device); 890EXPORT_SYMBOL(pci_enable_device);
814EXPORT_SYMBOL(pci_disable_device); 891EXPORT_SYMBOL(pci_disable_device);
@@ -823,6 +900,7 @@ EXPORT_SYMBOL(pci_request_region);
823EXPORT_SYMBOL(pci_set_master); 900EXPORT_SYMBOL(pci_set_master);
824EXPORT_SYMBOL(pci_set_mwi); 901EXPORT_SYMBOL(pci_set_mwi);
825EXPORT_SYMBOL(pci_clear_mwi); 902EXPORT_SYMBOL(pci_clear_mwi);
903EXPORT_SYMBOL_GPL(pci_intx);
826EXPORT_SYMBOL(pci_set_dma_mask); 904EXPORT_SYMBOL(pci_set_dma_mask);
827EXPORT_SYMBOL(pci_set_consistent_dma_mask); 905EXPORT_SYMBOL(pci_set_consistent_dma_mask);
828EXPORT_SYMBOL(pci_assign_resource); 906EXPORT_SYMBOL(pci_assign_resource);