diff options
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r-- | drivers/pci/pci.c | 246 |
1 files changed, 158 insertions, 88 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 07bbb9b3b93f..6c93af5ced18 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c | |||
@@ -485,6 +485,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) | |||
485 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | 485 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
486 | pmcsr |= state; | 486 | pmcsr |= state; |
487 | break; | 487 | break; |
488 | case PCI_D3hot: | ||
489 | case PCI_D3cold: | ||
488 | case PCI_UNKNOWN: /* Boot-up */ | 490 | case PCI_UNKNOWN: /* Boot-up */ |
489 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | 491 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
490 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | 492 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
@@ -1208,7 +1210,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable) | |||
1208 | * Error code depending on the platform is returned if both the platform and | 1210 | * Error code depending on the platform is returned if both the platform and |
1209 | * the native mechanism fail to enable the generation of wake-up events | 1211 | * the native mechanism fail to enable the generation of wake-up events |
1210 | */ | 1212 | */ |
1211 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | 1213 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1212 | { | 1214 | { |
1213 | int error = 0; | 1215 | int error = 0; |
1214 | bool pme_done = false; | 1216 | bool pme_done = false; |
@@ -1287,15 +1289,14 @@ pci_power_t pci_target_state(struct pci_dev *dev) | |||
1287 | default: | 1289 | default: |
1288 | target_state = state; | 1290 | target_state = state; |
1289 | } | 1291 | } |
1292 | } else if (!dev->pm_cap) { | ||
1293 | target_state = PCI_D0; | ||
1290 | } else if (device_may_wakeup(&dev->dev)) { | 1294 | } else if (device_may_wakeup(&dev->dev)) { |
1291 | /* | 1295 | /* |
1292 | * Find the deepest state from which the device can generate | 1296 | * Find the deepest state from which the device can generate |
1293 | * wake-up events, make it the target state and enable device | 1297 | * wake-up events, make it the target state and enable device |
1294 | * to generate PME#. | 1298 | * to generate PME#. |
1295 | */ | 1299 | */ |
1296 | if (!dev->pm_cap) | ||
1297 | return PCI_POWER_ERROR; | ||
1298 | |||
1299 | if (dev->pme_support) { | 1300 | if (dev->pme_support) { |
1300 | while (target_state | 1301 | while (target_state |
1301 | && !(dev->pme_support & (1 << target_state))) | 1302 | && !(dev->pme_support & (1 << target_state))) |
@@ -1532,7 +1533,7 @@ pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |||
1532 | if (!pin) | 1533 | if (!pin) |
1533 | return -1; | 1534 | return -1; |
1534 | 1535 | ||
1535 | while (dev->bus->parent) { | 1536 | while (!pci_is_root_bus(dev->bus)) { |
1536 | pin = pci_swizzle_interrupt_pin(dev, pin); | 1537 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1537 | dev = dev->bus->self; | 1538 | dev = dev->bus->self; |
1538 | } | 1539 | } |
@@ -1552,7 +1553,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |||
1552 | { | 1553 | { |
1553 | u8 pin = *pinp; | 1554 | u8 pin = *pinp; |
1554 | 1555 | ||
1555 | while (dev->bus->parent) { | 1556 | while (!pci_is_root_bus(dev->bus)) { |
1556 | pin = pci_swizzle_interrupt_pin(dev, pin); | 1557 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1557 | dev = dev->bus->self; | 1558 | dev = dev->bus->self; |
1558 | } | 1559 | } |
@@ -2058,111 +2059,177 @@ int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |||
2058 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | 2059 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); |
2059 | #endif | 2060 | #endif |
2060 | 2061 | ||
2061 | static int __pcie_flr(struct pci_dev *dev, int probe) | 2062 | static int pcie_flr(struct pci_dev *dev, int probe) |
2062 | { | 2063 | { |
2063 | u16 status; | 2064 | int i; |
2065 | int pos; | ||
2064 | u32 cap; | 2066 | u32 cap; |
2065 | int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP); | 2067 | u16 status; |
2066 | 2068 | ||
2067 | if (!exppos) | 2069 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
2070 | if (!pos) | ||
2068 | return -ENOTTY; | 2071 | return -ENOTTY; |
2069 | pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap); | 2072 | |
2073 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | ||
2070 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | 2074 | if (!(cap & PCI_EXP_DEVCAP_FLR)) |
2071 | return -ENOTTY; | 2075 | return -ENOTTY; |
2072 | 2076 | ||
2073 | if (probe) | 2077 | if (probe) |
2074 | return 0; | 2078 | return 0; |
2075 | 2079 | ||
2076 | pci_block_user_cfg_access(dev); | ||
2077 | |||
2078 | /* Wait for Transaction Pending bit clean */ | 2080 | /* Wait for Transaction Pending bit clean */ |
2079 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | 2081 | for (i = 0; i < 4; i++) { |
2080 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | 2082 | if (i) |
2081 | goto transaction_done; | 2083 | msleep((1 << (i - 1)) * 100); |
2082 | 2084 | ||
2083 | msleep(100); | 2085 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); |
2084 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | 2086 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
2085 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | 2087 | goto clear; |
2086 | goto transaction_done; | 2088 | } |
2087 | 2089 | ||
2088 | dev_info(&dev->dev, "Busy after 100ms while trying to reset; " | 2090 | dev_err(&dev->dev, "transaction is not cleared; " |
2089 | "sleeping for 1 second\n"); | 2091 | "proceeding with reset anyway\n"); |
2090 | ssleep(1); | 2092 | |
2091 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | 2093 | clear: |
2092 | if (status & PCI_EXP_DEVSTA_TRPND) | 2094 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, |
2093 | dev_info(&dev->dev, "Still busy after 1s; " | ||
2094 | "proceeding with reset anyway\n"); | ||
2095 | |||
2096 | transaction_done: | ||
2097 | pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL, | ||
2098 | PCI_EXP_DEVCTL_BCR_FLR); | 2095 | PCI_EXP_DEVCTL_BCR_FLR); |
2099 | mdelay(100); | 2096 | msleep(100); |
2100 | 2097 | ||
2101 | pci_unblock_user_cfg_access(dev); | ||
2102 | return 0; | 2098 | return 0; |
2103 | } | 2099 | } |
2104 | 2100 | ||
2105 | static int __pci_af_flr(struct pci_dev *dev, int probe) | 2101 | static int pci_af_flr(struct pci_dev *dev, int probe) |
2106 | { | 2102 | { |
2107 | int cappos = pci_find_capability(dev, PCI_CAP_ID_AF); | 2103 | int i; |
2108 | u8 status; | 2104 | int pos; |
2109 | u8 cap; | 2105 | u8 cap; |
2106 | u8 status; | ||
2110 | 2107 | ||
2111 | if (!cappos) | 2108 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
2109 | if (!pos) | ||
2112 | return -ENOTTY; | 2110 | return -ENOTTY; |
2113 | pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap); | 2111 | |
2112 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | ||
2114 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) | 2113 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
2115 | return -ENOTTY; | 2114 | return -ENOTTY; |
2116 | 2115 | ||
2117 | if (probe) | 2116 | if (probe) |
2118 | return 0; | 2117 | return 0; |
2119 | 2118 | ||
2120 | pci_block_user_cfg_access(dev); | ||
2121 | |||
2122 | /* Wait for Transaction Pending bit clean */ | 2119 | /* Wait for Transaction Pending bit clean */ |
2123 | pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status); | 2120 | for (i = 0; i < 4; i++) { |
2124 | if (!(status & PCI_AF_STATUS_TP)) | 2121 | if (i) |
2125 | goto transaction_done; | 2122 | msleep((1 << (i - 1)) * 100); |
2123 | |||
2124 | pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); | ||
2125 | if (!(status & PCI_AF_STATUS_TP)) | ||
2126 | goto clear; | ||
2127 | } | ||
2126 | 2128 | ||
2129 | dev_err(&dev->dev, "transaction is not cleared; " | ||
2130 | "proceeding with reset anyway\n"); | ||
2131 | |||
2132 | clear: | ||
2133 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | ||
2127 | msleep(100); | 2134 | msleep(100); |
2128 | pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status); | 2135 | |
2129 | if (!(status & PCI_AF_STATUS_TP)) | ||
2130 | goto transaction_done; | ||
2131 | |||
2132 | dev_info(&dev->dev, "Busy after 100ms while trying to" | ||
2133 | " reset; sleeping for 1 second\n"); | ||
2134 | ssleep(1); | ||
2135 | pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status); | ||
2136 | if (status & PCI_AF_STATUS_TP) | ||
2137 | dev_info(&dev->dev, "Still busy after 1s; " | ||
2138 | "proceeding with reset anyway\n"); | ||
2139 | |||
2140 | transaction_done: | ||
2141 | pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | ||
2142 | mdelay(100); | ||
2143 | |||
2144 | pci_unblock_user_cfg_access(dev); | ||
2145 | return 0; | 2136 | return 0; |
2146 | } | 2137 | } |
2147 | 2138 | ||
2148 | static int __pci_reset_function(struct pci_dev *pdev, int probe) | 2139 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
2149 | { | 2140 | { |
2150 | int res; | 2141 | u16 csr; |
2142 | |||
2143 | if (!dev->pm_cap) | ||
2144 | return -ENOTTY; | ||
2151 | 2145 | ||
2152 | res = __pcie_flr(pdev, probe); | 2146 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
2153 | if (res != -ENOTTY) | 2147 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) |
2154 | return res; | 2148 | return -ENOTTY; |
2155 | 2149 | ||
2156 | res = __pci_af_flr(pdev, probe); | 2150 | if (probe) |
2157 | if (res != -ENOTTY) | 2151 | return 0; |
2158 | return res; | ||
2159 | 2152 | ||
2160 | return res; | 2153 | if (dev->current_state != PCI_D0) |
2154 | return -EINVAL; | ||
2155 | |||
2156 | csr &= ~PCI_PM_CTRL_STATE_MASK; | ||
2157 | csr |= PCI_D3hot; | ||
2158 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | ||
2159 | msleep(pci_pm_d3_delay); | ||
2160 | |||
2161 | csr &= ~PCI_PM_CTRL_STATE_MASK; | ||
2162 | csr |= PCI_D0; | ||
2163 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | ||
2164 | msleep(pci_pm_d3_delay); | ||
2165 | |||
2166 | return 0; | ||
2167 | } | ||
2168 | |||
2169 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | ||
2170 | { | ||
2171 | u16 ctrl; | ||
2172 | struct pci_dev *pdev; | ||
2173 | |||
2174 | if (dev->subordinate) | ||
2175 | return -ENOTTY; | ||
2176 | |||
2177 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | ||
2178 | if (pdev != dev) | ||
2179 | return -ENOTTY; | ||
2180 | |||
2181 | if (probe) | ||
2182 | return 0; | ||
2183 | |||
2184 | pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); | ||
2185 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | ||
2186 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | ||
2187 | msleep(100); | ||
2188 | |||
2189 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | ||
2190 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | ||
2191 | msleep(100); | ||
2192 | |||
2193 | return 0; | ||
2194 | } | ||
2195 | |||
2196 | static int pci_dev_reset(struct pci_dev *dev, int probe) | ||
2197 | { | ||
2198 | int rc; | ||
2199 | |||
2200 | might_sleep(); | ||
2201 | |||
2202 | if (!probe) { | ||
2203 | pci_block_user_cfg_access(dev); | ||
2204 | /* block PM suspend, driver probe, etc. */ | ||
2205 | down(&dev->dev.sem); | ||
2206 | } | ||
2207 | |||
2208 | rc = pcie_flr(dev, probe); | ||
2209 | if (rc != -ENOTTY) | ||
2210 | goto done; | ||
2211 | |||
2212 | rc = pci_af_flr(dev, probe); | ||
2213 | if (rc != -ENOTTY) | ||
2214 | goto done; | ||
2215 | |||
2216 | rc = pci_pm_reset(dev, probe); | ||
2217 | if (rc != -ENOTTY) | ||
2218 | goto done; | ||
2219 | |||
2220 | rc = pci_parent_bus_reset(dev, probe); | ||
2221 | done: | ||
2222 | if (!probe) { | ||
2223 | up(&dev->dev.sem); | ||
2224 | pci_unblock_user_cfg_access(dev); | ||
2225 | } | ||
2226 | |||
2227 | return rc; | ||
2161 | } | 2228 | } |
2162 | 2229 | ||
2163 | /** | 2230 | /** |
2164 | * pci_execute_reset_function() - Reset a PCI device function | 2231 | * __pci_reset_function - reset a PCI device function |
2165 | * @dev: Device function to reset | 2232 | * @dev: PCI device to reset |
2166 | * | 2233 | * |
2167 | * Some devices allow an individual function to be reset without affecting | 2234 | * Some devices allow an individual function to be reset without affecting |
2168 | * other functions in the same device. The PCI device must be responsive | 2235 | * other functions in the same device. The PCI device must be responsive |
@@ -2174,18 +2241,18 @@ static int __pci_reset_function(struct pci_dev *pdev, int probe) | |||
2174 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | 2241 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, |
2175 | * etc. | 2242 | * etc. |
2176 | * | 2243 | * |
2177 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | 2244 | * Returns 0 if the device function was successfully reset or negative if the |
2178 | * device doesn't support resetting a single function. | 2245 | * device doesn't support resetting a single function. |
2179 | */ | 2246 | */ |
2180 | int pci_execute_reset_function(struct pci_dev *dev) | 2247 | int __pci_reset_function(struct pci_dev *dev) |
2181 | { | 2248 | { |
2182 | return __pci_reset_function(dev, 0); | 2249 | return pci_dev_reset(dev, 0); |
2183 | } | 2250 | } |
2184 | EXPORT_SYMBOL_GPL(pci_execute_reset_function); | 2251 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
2185 | 2252 | ||
2186 | /** | 2253 | /** |
2187 | * pci_reset_function() - quiesce and reset a PCI device function | 2254 | * pci_reset_function - quiesce and reset a PCI device function |
2188 | * @dev: Device function to reset | 2255 | * @dev: PCI device to reset |
2189 | * | 2256 | * |
2190 | * Some devices allow an individual function to be reset without affecting | 2257 | * Some devices allow an individual function to be reset without affecting |
2191 | * other functions in the same device. The PCI device must be responsive | 2258 | * other functions in the same device. The PCI device must be responsive |
@@ -2193,32 +2260,33 @@ EXPORT_SYMBOL_GPL(pci_execute_reset_function); | |||
2193 | * | 2260 | * |
2194 | * This function does not just reset the PCI portion of a device, but | 2261 | * This function does not just reset the PCI portion of a device, but |
2195 | * clears all the state associated with the device. This function differs | 2262 | * clears all the state associated with the device. This function differs |
2196 | * from pci_execute_reset_function in that it saves and restores device state | 2263 | * from __pci_reset_function in that it saves and restores device state |
2197 | * over the reset. | 2264 | * over the reset. |
2198 | * | 2265 | * |
2199 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | 2266 | * Returns 0 if the device function was successfully reset or negative if the |
2200 | * device doesn't support resetting a single function. | 2267 | * device doesn't support resetting a single function. |
2201 | */ | 2268 | */ |
2202 | int pci_reset_function(struct pci_dev *dev) | 2269 | int pci_reset_function(struct pci_dev *dev) |
2203 | { | 2270 | { |
2204 | int r = __pci_reset_function(dev, 1); | 2271 | int rc; |
2205 | 2272 | ||
2206 | if (r < 0) | 2273 | rc = pci_dev_reset(dev, 1); |
2207 | return r; | 2274 | if (rc) |
2275 | return rc; | ||
2208 | 2276 | ||
2209 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) | ||
2210 | disable_irq(dev->irq); | ||
2211 | pci_save_state(dev); | 2277 | pci_save_state(dev); |
2212 | 2278 | ||
2279 | /* | ||
2280 | * both INTx and MSI are disabled after the Interrupt Disable bit | ||
2281 | * is set and the Bus Master bit is cleared. | ||
2282 | */ | ||
2213 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | 2283 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); |
2214 | 2284 | ||
2215 | r = pci_execute_reset_function(dev); | 2285 | rc = pci_dev_reset(dev, 0); |
2216 | 2286 | ||
2217 | pci_restore_state(dev); | 2287 | pci_restore_state(dev); |
2218 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) | ||
2219 | enable_irq(dev->irq); | ||
2220 | 2288 | ||
2221 | return r; | 2289 | return rc; |
2222 | } | 2290 | } |
2223 | EXPORT_SYMBOL_GPL(pci_reset_function); | 2291 | EXPORT_SYMBOL_GPL(pci_reset_function); |
2224 | 2292 | ||
@@ -2591,6 +2659,8 @@ static int __init pci_setup(char *str) | |||
2591 | } else if (!strncmp(str, "resource_alignment=", 19)) { | 2659 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
2592 | pci_set_resource_alignment_param(str + 19, | 2660 | pci_set_resource_alignment_param(str + 19, |
2593 | strlen(str + 19)); | 2661 | strlen(str + 19)); |
2662 | } else if (!strncmp(str, "ecrc=", 5)) { | ||
2663 | pcie_ecrc_get_policy(str + 5); | ||
2594 | } else { | 2664 | } else { |
2595 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | 2665 | printk(KERN_ERR "PCI: Unknown option `%s'\n", |
2596 | str); | 2666 | str); |