1 files changed, 189 insertions, 11 deletions

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index fd47ac0c4730..03fd59e80fef 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -406,6 +406,13 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
         if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
                 return 0;
 
+        /* find PCI PM capability in list */
+        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
+
+        /* abort if the device doesn't support PM capabilities */
+        if (!pm)
+                return -EIO;
+
         /* Validate current state:
          * Can enter D0 from any state, but if we can only go deeper 
          * to sleep if we're already in a low power state
@@ -418,13 +425,6 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
                 return 0;        /* we're already there */
 
 
-        /* find PCI PM capability in list */
-        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
-        
-        /* abort if the device doesn't support PM capabilities */
-        if (!pm)
-                return -EIO; 
-
         pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
         if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
                 printk(KERN_DEBUG
@@ -1186,6 +1186,11 @@ int pci_set_mwi(struct pci_dev *dev)
         return 0;
 }
 
+int pci_try_set_mwi(struct pci_dev *dev)
+{
+        return 0;
+}
+
 void pci_clear_mwi(struct pci_dev *dev)
 {
 }
@@ -1242,9 +1247,7 @@ pci_set_cacheline_size(struct pci_dev *dev)
  * pci_set_mwi - enables memory-write-invalidate PCI transaction
  * @dev: the PCI device for which MWI is enabled
  *
- * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
- * and then calls @pcibios_set_mwi to do the needed arch specific
- * operations or a generic mwi-prep function.
+ * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
  *
  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  */
@@ -1260,7 +1263,8 @@ pci_set_mwi(struct pci_dev *dev)
 
         pci_read_config_word(dev, PCI_COMMAND, &cmd);
         if (! (cmd & PCI_COMMAND_INVALIDATE)) {
-                pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
+                pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
+                        pci_name(dev));
                 cmd |= PCI_COMMAND_INVALIDATE;
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
@@ -1269,6 +1273,21 @@ pci_set_mwi(struct pci_dev *dev)
 }
 
 /**
+ * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
+ * @dev: the PCI device for which MWI is enabled
+ *
+ * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
+ * Callers are not required to check the return value.
+ *
+ * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
+ */
+int pci_try_set_mwi(struct pci_dev *dev)
+{
+        int rc = pci_set_mwi(dev);
+        return rc;
+}
+
+/**
  * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
  * @dev: the PCI device to disable
  *
@@ -1375,6 +1394,164 @@ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
 #endif
 
 /**
+ * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
+ * @dev: PCI device to query
+ *
+ * Returns mmrbc: maximum designed memory read count in bytes
+ *    or appropriate error value.
+ */
+int pcix_get_max_mmrbc(struct pci_dev *dev)
+{
+        int err, cap;
+        u32 stat;
+
+        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+        if (!cap)
+                return -EINVAL;
+
+        err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
+        if (err)
+                return -EINVAL;
+
+        return (stat & PCI_X_STATUS_MAX_READ) >> 12;
+}
+EXPORT_SYMBOL(pcix_get_max_mmrbc);
+
+/**
+ * pcix_get_mmrbc - get PCI-X maximum memory read byte count
+ * @dev: PCI device to query
+ *
+ * Returns mmrbc: maximum memory read count in bytes
+ *    or appropriate error value.
+ */
+int pcix_get_mmrbc(struct pci_dev *dev)
+{
+        int ret, cap;
+        u32 cmd;
+
+        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+        if (!cap)
+                return -EINVAL;
+
+        ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
+        if (!ret)
+                ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
+
+        return ret;
+}
+EXPORT_SYMBOL(pcix_get_mmrbc);
+
+/**
+ * pcix_set_mmrbc - set PCI-X maximum memory read byte count
+ * @dev: PCI device to query
+ * @mmrbc: maximum memory read count in bytes
+ *    valid values are 512, 1024, 2048, 4096
+ *
+ * If possible sets maximum memory read byte count, some bridges have erratas
+ * that prevent this.
+ */
+int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
+{
+        int cap, err = -EINVAL;
+        u32 stat, cmd, v, o;
+
+        if (mmrbc < 512 || mmrbc > 4096 || (mmrbc & (mmrbc-1)))
+                goto out;
+
+        v = ffs(mmrbc) - 10;
+
+        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+        if (!cap)
+                goto out;
+
+        err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
+        if (err)
+                goto out;
+
+        if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
+                return -E2BIG;
+
+        err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
+        if (err)
+                goto out;
+
+        o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
+        if (o != v) {
+                if (v > o && dev->bus &&
+                   (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
+                        return -EIO;
+
+                cmd &= ~PCI_X_CMD_MAX_READ;
+                cmd |= v << 2;
+                err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
+        }
+out:
+        return err;
+}
+EXPORT_SYMBOL(pcix_set_mmrbc);
+
+/**
+ * pcie_get_readrq - get PCI Express read request size
+ * @dev: PCI device to query
+ *
+ * Returns maximum memory read request in bytes
+ *    or appropriate error value.
+ */
+int pcie_get_readrq(struct pci_dev *dev)
+{
+        int ret, cap;
+        u16 ctl;
+
+        cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        if (!cap)
+                return -EINVAL;
+
+        ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
+        if (!ret)
+        ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+
+        return ret;
+}
+EXPORT_SYMBOL(pcie_get_readrq);
+
+/**
+ * pcie_set_readrq - set PCI Express maximum memory read request
+ * @dev: PCI device to query
+ * @count: maximum memory read count in bytes
+ *    valid values are 128, 256, 512, 1024, 2048, 4096
+ *
+ * If possible sets maximum read byte count
+ */
+int pcie_set_readrq(struct pci_dev *dev, int rq)
+{
+        int cap, err = -EINVAL;
+        u16 ctl, v;
+
+        if (rq < 128 || rq > 4096 || (rq & (rq-1)))
+                goto out;
+
+        v = (ffs(rq) - 8) << 12;
+
+        cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        if (!cap)
+                goto out;
+
+        err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
+        if (err)
+                goto out;
+
+        if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
+                ctl &= ~PCI_EXP_DEVCTL_READRQ;
+                ctl |= v;
+                err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
+        }
+
+out:
+        return err;
+}
+EXPORT_SYMBOL(pcie_set_readrq);
+
+/**
  * pci_select_bars - Make BAR mask from the type of resource
  * @dev: the PCI device for which BAR mask is made
  * @flags: resource type mask to be selected
@@ -1442,6 +1619,7 @@ EXPORT_SYMBOL(pci_release_selected_regions);
 EXPORT_SYMBOL(pci_request_selected_regions);
 EXPORT_SYMBOL(pci_set_master);
 EXPORT_SYMBOL(pci_set_mwi);
+EXPORT_SYMBOL(pci_try_set_mwi);
 EXPORT_SYMBOL(pci_clear_mwi);
 EXPORT_SYMBOL_GPL(pci_intx);
 EXPORT_SYMBOL(pci_set_dma_mask);