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path: root/drivers/pci/pci.c
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Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 0906599ebfde..315fea47e784 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -29,7 +29,17 @@ const char *pci_power_names[] = {
29}; 29};
30EXPORT_SYMBOL_GPL(pci_power_names); 30EXPORT_SYMBOL_GPL(pci_power_names);
31 31
32unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT; 32unsigned int pci_pm_d3_delay;
33
34static void pci_dev_d3_sleep(struct pci_dev *dev)
35{
36 unsigned int delay = dev->d3_delay;
37
38 if (delay < pci_pm_d3_delay)
39 delay = pci_pm_d3_delay;
40
41 msleep(delay);
42}
33 43
34#ifdef CONFIG_PCI_DOMAINS 44#ifdef CONFIG_PCI_DOMAINS
35int pci_domains_supported = 1; 45int pci_domains_supported = 1;
@@ -522,7 +532,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
522 /* Mandatory power management transition delays */ 532 /* Mandatory power management transition delays */
523 /* see PCI PM 1.1 5.6.1 table 18 */ 533 /* see PCI PM 1.1 5.6.1 table 18 */
524 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 534 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
525 msleep(pci_pm_d3_delay); 535 pci_dev_d3_sleep(dev);
526 else if (state == PCI_D2 || dev->current_state == PCI_D2) 536 else if (state == PCI_D2 || dev->current_state == PCI_D2)
527 udelay(PCI_PM_D2_DELAY); 537 udelay(PCI_PM_D2_DELAY);
528 538
@@ -1409,6 +1419,7 @@ void pci_pm_init(struct pci_dev *dev)
1409 } 1419 }
1410 1420
1411 dev->pm_cap = pm; 1421 dev->pm_cap = pm;
1422 dev->d3_delay = PCI_PM_D3_WAIT;
1412 1423
1413 dev->d1_support = false; 1424 dev->d1_support = false;
1414 dev->d2_support = false; 1425 dev->d2_support = false;
@@ -2247,12 +2258,12 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
2247 csr &= ~PCI_PM_CTRL_STATE_MASK; 2258 csr &= ~PCI_PM_CTRL_STATE_MASK;
2248 csr |= PCI_D3hot; 2259 csr |= PCI_D3hot;
2249 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2260 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2250 msleep(pci_pm_d3_delay); 2261 pci_dev_d3_sleep(dev);
2251 2262
2252 csr &= ~PCI_PM_CTRL_STATE_MASK; 2263 csr &= ~PCI_PM_CTRL_STATE_MASK;
2253 csr |= PCI_D0; 2264 csr |= PCI_D0;
2254 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2265 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2255 msleep(pci_pm_d3_delay); 2266 pci_dev_d3_sleep(dev);
2256 2267
2257 return 0; 2268 return 0;
2258} 2269}