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path: root/drivers/pci/msi.c
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Diffstat (limited to 'drivers/pci/msi.c')
-rw-r--r--drivers/pci/msi.c151
1 files changed, 26 insertions, 125 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 01869b1782e4..435c1958a7b7 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -94,12 +94,14 @@ static void msi_set_mask_bit(unsigned int irq, int flag)
94 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 94 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
95 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 95 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
96 writel(flag, entry->mask_base + offset); 96 writel(flag, entry->mask_base + offset);
97 readl(entry->mask_base + offset);
97 break; 98 break;
98 } 99 }
99 default: 100 default:
100 BUG(); 101 BUG();
101 break; 102 break;
102 } 103 }
104 entry->msi_attrib.masked = !!flag;
103} 105}
104 106
105void read_msi_msg(unsigned int irq, struct msi_msg *msg) 107void read_msi_msg(unsigned int irq, struct msi_msg *msg)
@@ -179,6 +181,7 @@ void write_msi_msg(unsigned int irq, struct msi_msg *msg)
179 default: 181 default:
180 BUG(); 182 BUG();
181 } 183 }
184 entry->msg = *msg;
182} 185}
183 186
184void mask_msi_irq(unsigned int irq) 187void mask_msi_irq(unsigned int irq)
@@ -225,164 +228,60 @@ static struct msi_desc* alloc_msi_entry(void)
225} 228}
226 229
227#ifdef CONFIG_PM 230#ifdef CONFIG_PM
228static int __pci_save_msi_state(struct pci_dev *dev)
229{
230 int pos, i = 0;
231 u16 control;
232 struct pci_cap_saved_state *save_state;
233 u32 *cap;
234
235 if (!dev->msi_enabled)
236 return 0;
237
238 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
239 if (pos <= 0)
240 return 0;
241
242 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
243 GFP_KERNEL);
244 if (!save_state) {
245 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
246 return -ENOMEM;
247 }
248 cap = &save_state->data[0];
249
250 pci_read_config_dword(dev, pos, &cap[i++]);
251 control = cap[0] >> 16;
252 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
253 if (control & PCI_MSI_FLAGS_64BIT) {
254 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
255 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
256 } else
257 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
258 if (control & PCI_MSI_FLAGS_MASKBIT)
259 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
260 save_state->cap_nr = PCI_CAP_ID_MSI;
261 pci_add_saved_cap(dev, save_state);
262 return 0;
263}
264
265static void __pci_restore_msi_state(struct pci_dev *dev) 231static void __pci_restore_msi_state(struct pci_dev *dev)
266{ 232{
267 int i = 0, pos; 233 int pos;
268 u16 control; 234 u16 control;
269 struct pci_cap_saved_state *save_state; 235 struct msi_desc *entry;
270 u32 *cap;
271 236
272 if (!dev->msi_enabled) 237 if (!dev->msi_enabled)
273 return; 238 return;
274 239
275 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 240 entry = get_irq_msi(dev->irq);
276 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 241 pos = entry->msi_attrib.pos;
277 if (!save_state || pos <= 0)
278 return;
279 cap = &save_state->data[0];
280 242
281 pci_intx(dev, 0); /* disable intx */ 243 pci_intx(dev, 0); /* disable intx */
282 control = cap[i++] >> 16;
283 msi_set_enable(dev, 0); 244 msi_set_enable(dev, 0);
284 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 245 write_msi_msg(dev->irq, &entry->msg);
285 if (control & PCI_MSI_FLAGS_64BIT) { 246 if (entry->msi_attrib.maskbit)
286 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 247 msi_set_mask_bit(dev->irq, entry->msi_attrib.masked);
287 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 248
288 } else 249 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
289 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 250 control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
290 if (control & PCI_MSI_FLAGS_MASKBIT) 251 if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked)
291 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 252 control |= PCI_MSI_FLAGS_ENABLE;
292 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 253 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
293 pci_remove_saved_cap(save_state);
294 kfree(save_state);
295}
296
297static int __pci_save_msix_state(struct pci_dev *dev)
298{
299 int pos;
300 int irq, head, tail = 0;
301 u16 control;
302 struct pci_cap_saved_state *save_state;
303
304 if (!dev->msix_enabled)
305 return 0;
306
307 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
308 if (pos <= 0)
309 return 0;
310
311 /* save the capability */
312 pci_read_config_word(dev, msi_control_reg(pos), &control);
313 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
314 GFP_KERNEL);
315 if (!save_state) {
316 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
317 return -ENOMEM;
318 }
319 *((u16 *)&save_state->data[0]) = control;
320
321 /* save the table */
322 irq = head = dev->first_msi_irq;
323 while (head != tail) {
324 struct msi_desc *entry;
325
326 entry = get_irq_msi(irq);
327 read_msi_msg(irq, &entry->msg_save);
328
329 tail = entry->link.tail;
330 irq = tail;
331 }
332
333 save_state->cap_nr = PCI_CAP_ID_MSIX;
334 pci_add_saved_cap(dev, save_state);
335 return 0;
336}
337
338int pci_save_msi_state(struct pci_dev *dev)
339{
340 int rc;
341
342 rc = __pci_save_msi_state(dev);
343 if (rc)
344 return rc;
345
346 rc = __pci_save_msix_state(dev);
347
348 return rc;
349} 254}
350 255
351static void __pci_restore_msix_state(struct pci_dev *dev) 256static void __pci_restore_msix_state(struct pci_dev *dev)
352{ 257{
353 u16 save;
354 int pos; 258 int pos;
355 int irq, head, tail = 0; 259 int irq, head, tail = 0;
356 struct msi_desc *entry; 260 struct msi_desc *entry;
357 struct pci_cap_saved_state *save_state; 261 u16 control;
358 262
359 if (!dev->msix_enabled) 263 if (!dev->msix_enabled)
360 return; 264 return;
361 265
362 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
363 if (!save_state)
364 return;
365 save = *((u16 *)&save_state->data[0]);
366 pci_remove_saved_cap(save_state);
367 kfree(save_state);
368
369 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
370 if (pos <= 0)
371 return;
372
373 /* route the table */ 266 /* route the table */
374 pci_intx(dev, 0); /* disable intx */ 267 pci_intx(dev, 0); /* disable intx */
375 msix_set_enable(dev, 0); 268 msix_set_enable(dev, 0);
376 irq = head = dev->first_msi_irq; 269 irq = head = dev->first_msi_irq;
270 entry = get_irq_msi(irq);
271 pos = entry->msi_attrib.pos;
377 while (head != tail) { 272 while (head != tail) {
378 entry = get_irq_msi(irq); 273 entry = get_irq_msi(irq);
379 write_msi_msg(irq, &entry->msg_save); 274 write_msi_msg(irq, &entry->msg);
275 msi_set_mask_bit(irq, entry->msi_attrib.masked);
380 276
381 tail = entry->link.tail; 277 tail = entry->link.tail;
382 irq = tail; 278 irq = tail;
383 } 279 }
384 280
385 pci_write_config_word(dev, msi_control_reg(pos), save); 281 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
282 control &= ~PCI_MSIX_FLAGS_MASKALL;
283 control |= PCI_MSIX_FLAGS_ENABLE;
284 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
386} 285}
387 286
388void pci_restore_msi_state(struct pci_dev *dev) 287void pci_restore_msi_state(struct pci_dev *dev)
@@ -420,6 +319,7 @@ static int msi_capability_init(struct pci_dev *dev)
420 entry->msi_attrib.is_64 = is_64bit_address(control); 319 entry->msi_attrib.is_64 = is_64bit_address(control);
421 entry->msi_attrib.entry_nr = 0; 320 entry->msi_attrib.entry_nr = 0;
422 entry->msi_attrib.maskbit = is_mask_bit_support(control); 321 entry->msi_attrib.maskbit = is_mask_bit_support(control);
322 entry->msi_attrib.masked = 1;
423 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 323 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
424 entry->msi_attrib.pos = pos; 324 entry->msi_attrib.pos = pos;
425 if (is_mask_bit_support(control)) { 325 if (is_mask_bit_support(control)) {
@@ -507,6 +407,7 @@ static int msix_capability_init(struct pci_dev *dev,
507 entry->msi_attrib.is_64 = 1; 407 entry->msi_attrib.is_64 = 1;
508 entry->msi_attrib.entry_nr = j; 408 entry->msi_attrib.entry_nr = j;
509 entry->msi_attrib.maskbit = 1; 409 entry->msi_attrib.maskbit = 1;
410 entry->msi_attrib.masked = 1;
510 entry->msi_attrib.default_irq = dev->irq; 411 entry->msi_attrib.default_irq = dev->irq;
511 entry->msi_attrib.pos = pos; 412 entry->msi_attrib.pos = pos;
512 entry->dev = dev; 413 entry->dev = dev;