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path: root/drivers/pci/intel-iommu.h
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Diffstat (limited to 'drivers/pci/intel-iommu.h')
-rw-r--r--drivers/pci/intel-iommu.h24
1 files changed, 22 insertions, 2 deletions
diff --git a/drivers/pci/intel-iommu.h b/drivers/pci/intel-iommu.h
index 2983ce895353..a81a74e2bd9e 100644
--- a/drivers/pci/intel-iommu.h
+++ b/drivers/pci/intel-iommu.h
@@ -56,6 +56,7 @@
56#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ 56#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
57#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ 57#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
58#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */ 58#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
59#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
59 60
60#define OFFSET_STRIDE (9) 61#define OFFSET_STRIDE (9)
61/* 62/*
@@ -157,16 +158,20 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
157#define DMA_GCMD_SRTP (((u32)1) << 30) 158#define DMA_GCMD_SRTP (((u32)1) << 30)
158#define DMA_GCMD_SFL (((u32)1) << 29) 159#define DMA_GCMD_SFL (((u32)1) << 29)
159#define DMA_GCMD_EAFL (((u32)1) << 28) 160#define DMA_GCMD_EAFL (((u32)1) << 28)
160#define DMA_GCMD_QIE (((u32)1) << 26)
161#define DMA_GCMD_WBF (((u32)1) << 27) 161#define DMA_GCMD_WBF (((u32)1) << 27)
162#define DMA_GCMD_QIE (((u32)1) << 26)
163#define DMA_GCMD_SIRTP (((u32)1) << 24)
164#define DMA_GCMD_IRE (((u32) 1) << 25)
162 165
163/* GSTS_REG */ 166/* GSTS_REG */
164#define DMA_GSTS_TES (((u32)1) << 31) 167#define DMA_GSTS_TES (((u32)1) << 31)
165#define DMA_GSTS_RTPS (((u32)1) << 30) 168#define DMA_GSTS_RTPS (((u32)1) << 30)
166#define DMA_GSTS_FLS (((u32)1) << 29) 169#define DMA_GSTS_FLS (((u32)1) << 29)
167#define DMA_GSTS_AFLS (((u32)1) << 28) 170#define DMA_GSTS_AFLS (((u32)1) << 28)
168#define DMA_GSTS_QIES (((u32)1) << 26)
169#define DMA_GSTS_WBFS (((u32)1) << 27) 171#define DMA_GSTS_WBFS (((u32)1) << 27)
172#define DMA_GSTS_QIES (((u32)1) << 26)
173#define DMA_GSTS_IRTPS (((u32)1) << 24)
174#define DMA_GSTS_IRES (((u32)1) << 25)
170 175
171/* CCMD_REG */ 176/* CCMD_REG */
172#define DMA_CCMD_ICC (((u64)1) << 63) 177#define DMA_CCMD_ICC (((u64)1) << 63)
@@ -245,6 +250,16 @@ struct q_inval {
245 int free_cnt; 250 int free_cnt;
246}; 251};
247 252
253#ifdef CONFIG_INTR_REMAP
254/* 1MB - maximum possible interrupt remapping table size */
255#define INTR_REMAP_PAGE_ORDER 8
256#define INTR_REMAP_TABLE_REG_SIZE 0xf
257
258struct ir_table {
259 struct irte *base;
260};
261#endif
262
248struct intel_iommu { 263struct intel_iommu {
249 void __iomem *reg; /* Pointer to hardware regs, virtual addr */ 264 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
250 u64 cap; 265 u64 cap;
@@ -266,6 +281,9 @@ struct intel_iommu {
266 struct sys_device sysdev; 281 struct sys_device sysdev;
267#endif 282#endif
268 struct q_inval *qi; /* Queued invalidation info */ 283 struct q_inval *qi; /* Queued invalidation info */
284#ifdef CONFIG_INTR_REMAP
285 struct ir_table *ir_table; /* Interrupt remapping info */
286#endif
269}; 287};
270 288
271static inline void __iommu_flush_cache( 289static inline void __iommu_flush_cache(
@@ -279,5 +297,7 @@ extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
279 297
280extern int alloc_iommu(struct dmar_drhd_unit *drhd); 298extern int alloc_iommu(struct dmar_drhd_unit *drhd);
281extern void free_iommu(struct intel_iommu *iommu); 299extern void free_iommu(struct intel_iommu *iommu);
300extern int dmar_enable_qi(struct intel_iommu *iommu);
301extern void qi_global_iec(struct intel_iommu *iommu);
282 302
283#endif 303#endif