1 files changed, 63 insertions, 207 deletions

diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index f3f686581a90..49402c399232 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -1004,194 +1004,6 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
         return 0;
 }
 
-/* iommu interrupt handling. Most stuff are MSI-like. */
-
-static const char *fault_reason_strings[] =
-{
-        "Software",
-        "Present bit in root entry is clear",
-        "Present bit in context entry is clear",
-        "Invalid context entry",
-        "Access beyond MGAW",
-        "PTE Write access is not set",
-        "PTE Read access is not set",
-        "Next page table ptr is invalid",
-        "Root table address invalid",
-        "Context table ptr is invalid",
-        "non-zero reserved fields in RTP",
-        "non-zero reserved fields in CTP",
-        "non-zero reserved fields in PTE",
-};
-#define MAX_FAULT_REASON_IDX    (ARRAY_SIZE(fault_reason_strings) - 1)
-
-const char *dmar_get_fault_reason(u8 fault_reason)
-{
-        if (fault_reason > MAX_FAULT_REASON_IDX)
-                return "Unknown";
-        else
-                return fault_reason_strings[fault_reason];
-}
-
-void dmar_msi_unmask(unsigned int irq)
-{
-        struct intel_iommu *iommu = get_irq_data(irq);
-        unsigned long flag;
-
-        /* unmask it */
-        spin_lock_irqsave(&iommu->register_lock, flag);
-        writel(0, iommu->reg + DMAR_FECTL_REG);
-        /* Read a reg to force flush the post write */
-        readl(iommu->reg + DMAR_FECTL_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
-}
-
-void dmar_msi_mask(unsigned int irq)
-{
-        unsigned long flag;
-        struct intel_iommu *iommu = get_irq_data(irq);
-
-        /* mask it */
-        spin_lock_irqsave(&iommu->register_lock, flag);
-        writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
-        /* Read a reg to force flush the post write */
-        readl(iommu->reg + DMAR_FECTL_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
-}
-
-void dmar_msi_write(int irq, struct msi_msg *msg)
-{
-        struct intel_iommu *iommu = get_irq_data(irq);
-        unsigned long flag;
-
-        spin_lock_irqsave(&iommu->register_lock, flag);
-        writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
-        writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
-        writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
-}
-
-void dmar_msi_read(int irq, struct msi_msg *msg)
-{
-        struct intel_iommu *iommu = get_irq_data(irq);
-        unsigned long flag;
-
-        spin_lock_irqsave(&iommu->register_lock, flag);
-        msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
-        msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
-        msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
-}
-
-static int iommu_page_fault_do_one(struct intel_iommu *iommu, int type,
-                u8 fault_reason, u16 source_id, unsigned long long addr)
-{
-        const char *reason;
-
-        reason = dmar_get_fault_reason(fault_reason);
-
-        printk(KERN_ERR
-                "DMAR:[%s] Request device [%02x:%02x.%d] "
-                "fault addr %llx \n"
-                "DMAR:[fault reason %02d] %s\n",
-                (type ? "DMA Read" : "DMA Write"),
-                (source_id >> 8), PCI_SLOT(source_id & 0xFF),
-                PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
-        return 0;
-}
-
-#define PRIMARY_FAULT_REG_LEN (16)
-static irqreturn_t iommu_page_fault(int irq, void *dev_id)
-{
-        struct intel_iommu *iommu = dev_id;
-        int reg, fault_index;
-        u32 fault_status;
-        unsigned long flag;
-
-        spin_lock_irqsave(&iommu->register_lock, flag);
-        fault_status = readl(iommu->reg + DMAR_FSTS_REG);
-
-        /* TBD: ignore advanced fault log currently */
-        if (!(fault_status & DMA_FSTS_PPF))
-                goto clear_overflow;
-
-        fault_index = dma_fsts_fault_record_index(fault_status);
-        reg = cap_fault_reg_offset(iommu->cap);
-        while (1) {
-                u8 fault_reason;
-                u16 source_id;
-                u64 guest_addr;
-                int type;
-                u32 data;
-
-                /* highest 32 bits */
-                data = readl(iommu->reg + reg +
-                                fault_index * PRIMARY_FAULT_REG_LEN + 12);
-                if (!(data & DMA_FRCD_F))
-                        break;
-
-                fault_reason = dma_frcd_fault_reason(data);
-                type = dma_frcd_type(data);
-
-                data = readl(iommu->reg + reg +
-                                fault_index * PRIMARY_FAULT_REG_LEN + 8);
-                source_id = dma_frcd_source_id(data);
-
-                guest_addr = dmar_readq(iommu->reg + reg +
-                                fault_index * PRIMARY_FAULT_REG_LEN);
-                guest_addr = dma_frcd_page_addr(guest_addr);
-                /* clear the fault */
-                writel(DMA_FRCD_F, iommu->reg + reg +
-                        fault_index * PRIMARY_FAULT_REG_LEN + 12);
-
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
-
-                iommu_page_fault_do_one(iommu, type, fault_reason,
-                                source_id, guest_addr);
-
-                fault_index++;
-                if (fault_index > cap_num_fault_regs(iommu->cap))
-                        fault_index = 0;
-                spin_lock_irqsave(&iommu->register_lock, flag);
-        }
-clear_overflow:
-        /* clear primary fault overflow */
-        fault_status = readl(iommu->reg + DMAR_FSTS_REG);
-        if (fault_status & DMA_FSTS_PFO)
-                writel(DMA_FSTS_PFO, iommu->reg + DMAR_FSTS_REG);
-
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
-        return IRQ_HANDLED;
-}
-
-int dmar_set_interrupt(struct intel_iommu *iommu)
-{
-        int irq, ret;
-
-        irq = create_irq();
-        if (!irq) {
-                printk(KERN_ERR "IOMMU: no free vectors\n");
-                return -EINVAL;
-        }
-
-        set_irq_data(irq, iommu);
-        iommu->irq = irq;
-
-        ret = arch_setup_dmar_msi(irq);
-        if (ret) {
-                set_irq_data(irq, NULL);
-                iommu->irq = 0;
-                destroy_irq(irq);
-                return 0;
-        }
-
-        /* Force fault register is cleared */
-        iommu_page_fault(irq, iommu);
-
-        ret = request_irq(irq, iommu_page_fault, 0, iommu->name, iommu);
-        if (ret)
-                printk(KERN_ERR "IOMMU: can't request irq\n");
-        return ret;
-}
 
 static int iommu_init_domains(struct intel_iommu *iommu)
 {
@@ -1987,7 +1799,7 @@ static int __init init_dmars(void)
         struct dmar_rmrr_unit *rmrr;
         struct pci_dev *pdev;
         struct intel_iommu *iommu;
-        int i, ret, unit = 0;
+        int i, ret;
 
         /*
          * for each drhd
@@ -2043,11 +1855,40 @@ static int __init init_dmars(void)
                 }
         }
 
+        /*
+         * Start from the sane iommu hardware state.
+         */
         for_each_drhd_unit(drhd) {
                 if (drhd->ignored)
                         continue;
 
                 iommu = drhd->iommu;
+
+                /*
+                 * If the queued invalidation is already initialized by us
+                 * (for example, while enabling interrupt-remapping) then
+                 * we got the things already rolling from a sane state.
+                 */
+                if (iommu->qi)
+                        continue;
+
+                /*
+                 * Clear any previous faults.
+                 */
+                dmar_fault(-1, iommu);
+                /*
+                 * Disable queued invalidation if supported and already enabled
+                 * before OS handover.
+                 */
+                dmar_disable_qi(iommu);
+        }
+
+        for_each_drhd_unit(drhd) {
+                if (drhd->ignored)
+                        continue;
+
+                iommu = drhd->iommu;
+
                 if (dmar_enable_qi(iommu)) {
                         /*
                          * Queued Invalidate not enabled, use Register Based
@@ -2109,7 +1950,6 @@ static int __init init_dmars(void)
                 if (drhd->ignored)
                         continue;
                 iommu = drhd->iommu;
-                sprintf (iommu->name, "dmar%d", unit++);
 
                 iommu_flush_write_buffer(iommu);
 
@@ -2284,11 +2124,13 @@ error:
         return 0;
 }
 
-dma_addr_t intel_map_single(struct device *hwdev, phys_addr_t paddr,
-                            size_t size, int dir)
+static dma_addr_t intel_map_page(struct device *dev, struct page *page,
+                                 unsigned long offset, size_t size,
+                                 enum dma_data_direction dir,
+                                 struct dma_attrs *attrs)
 {
-        return __intel_map_single(hwdev, paddr, size, dir,
-                                  to_pci_dev(hwdev)->dma_mask);
+        return __intel_map_single(dev, page_to_phys(page) + offset, size,
+                                  dir, to_pci_dev(dev)->dma_mask);
 }
 
 static void flush_unmaps(void)
@@ -2352,8 +2194,9 @@ static void add_unmap(struct dmar_domain *dom, struct iova *iova)
         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
 }
 
-void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
-                        int dir)
+static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
+                             size_t size, enum dma_data_direction dir,
+                             struct dma_attrs *attrs)
 {
         struct pci_dev *pdev = to_pci_dev(dev);
         struct dmar_domain *domain;
@@ -2397,8 +2240,14 @@ void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
         }
 }
 
-void *intel_alloc_coherent(struct device *hwdev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flags)
+static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
+                               int dir)
+{
+        intel_unmap_page(dev, dev_addr, size, dir, NULL);
+}
+
+static void *intel_alloc_coherent(struct device *hwdev, size_t size,
+                                  dma_addr_t *dma_handle, gfp_t flags)
 {
         void *vaddr;
         int order;
@@ -2421,8 +2270,8 @@ void *intel_alloc_coherent(struct device *hwdev, size_t size,
         return NULL;
 }
 
-void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
-                         dma_addr_t dma_handle)
+static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
+                                dma_addr_t dma_handle)
 {
         int order;
 
@@ -2435,8 +2284,9 @@ void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
 
 #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg)))
 
-void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
-                    int nelems, int dir)
+static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
+                           int nelems, enum dma_data_direction dir,
+                           struct dma_attrs *attrs)
 {
         int i;
         struct pci_dev *pdev = to_pci_dev(hwdev);
@@ -2493,8 +2343,8 @@ static int intel_nontranslate_map_sg(struct device *hddev,
         return nelems;
 }
 
-int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
-                 int dir)
+static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
+                        enum dma_data_direction dir, struct dma_attrs *attrs)
 {
         void *addr;
         int i;
@@ -2574,13 +2424,19 @@ int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
         return nelems;
 }
 
-static struct dma_mapping_ops intel_dma_ops = {
+static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return !dma_addr;
+}
+
+struct dma_map_ops intel_dma_ops = {
         .alloc_coherent = intel_alloc_coherent,
         .free_coherent = intel_free_coherent,
-        .map_single = intel_map_single,
-        .unmap_single = intel_unmap_single,
         .map_sg = intel_map_sg,
         .unmap_sg = intel_unmap_sg,
+        .map_page = intel_map_page,
+        .unmap_page = intel_unmap_page,
+        .mapping_error = intel_mapping_error,
 };
 
 static inline int iommu_domain_cache_init(void)