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path: root/drivers/pci/hotplug/shpchp_hpc.c
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Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c113
1 files changed, 57 insertions, 56 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 7a0bff364cd4..86dc39847769 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -300,10 +300,10 @@ static inline int shpc_wait_cmd(struct controller *ctrl)
300 !is_ctrl_busy(ctrl), timeout); 300 !is_ctrl_busy(ctrl), timeout);
301 if (!rc && is_ctrl_busy(ctrl)) { 301 if (!rc && is_ctrl_busy(ctrl)) {
302 retval = -EIO; 302 retval = -EIO;
303 err("Command not completed in 1000 msec\n"); 303 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
304 } else if (rc < 0) { 304 } else if (rc < 0) {
305 retval = -EINTR; 305 retval = -EINTR;
306 info("Command was interrupted by a signal\n"); 306 ctrl_info(ctrl, "Command was interrupted by a signal\n");
307 } 307 }
308 308
309 return retval; 309 return retval;
@@ -320,15 +320,14 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
320 320
321 if (!shpc_poll_ctrl_busy(ctrl)) { 321 if (!shpc_poll_ctrl_busy(ctrl)) {
322 /* After 1 sec and and the controller is still busy */ 322 /* After 1 sec and and the controller is still busy */
323 err("%s : Controller is still busy after 1 sec.\n", 323 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
324 __func__);
325 retval = -EBUSY; 324 retval = -EBUSY;
326 goto out; 325 goto out;
327 } 326 }
328 327
329 ++t_slot; 328 ++t_slot;
330 temp_word = (t_slot << 8) | (cmd & 0xFF); 329 temp_word = (t_slot << 8) | (cmd & 0xFF);
331 dbg("%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); 330 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
332 331
333 /* To make sure the Controller Busy bit is 0 before we send out the 332 /* To make sure the Controller Busy bit is 0 before we send out the
334 * command. 333 * command.
@@ -344,8 +343,9 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
344 343
345 cmd_status = hpc_check_cmd_status(slot->ctrl); 344 cmd_status = hpc_check_cmd_status(slot->ctrl);
346 if (cmd_status) { 345 if (cmd_status) {
347 err("%s: Failed to issued command 0x%x (error code = %d)\n", 346 ctrl_err(ctrl,
348 __func__, cmd, cmd_status); 347 "Failed to issued command 0x%x (error code = %d)\n",
348 cmd, cmd_status);
349 retval = -EIO; 349 retval = -EIO;
350 } 350 }
351 out: 351 out:
@@ -364,15 +364,15 @@ static int hpc_check_cmd_status(struct controller *ctrl)
364 break; 364 break;
365 case 1: 365 case 1:
366 retval = SWITCH_OPEN; 366 retval = SWITCH_OPEN;
367 err("%s: Switch opened!\n", __func__); 367 ctrl_err(ctrl, "Switch opened!\n");
368 break; 368 break;
369 case 2: 369 case 2:
370 retval = INVALID_CMD; 370 retval = INVALID_CMD;
371 err("%s: Invalid HPC command!\n", __func__); 371 ctrl_err(ctrl, "Invalid HPC command!\n");
372 break; 372 break;
373 case 4: 373 case 4:
374 retval = INVALID_SPEED_MODE; 374 retval = INVALID_SPEED_MODE;
375 err("%s: Invalid bus speed/mode!\n", __func__); 375 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
376 break; 376 break;
377 default: 377 default:
378 retval = cmd_status; 378 retval = cmd_status;
@@ -483,8 +483,8 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
483 return -ENODEV; 483 return -ENODEV;
484 } 484 }
485 485
486 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 486 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
487 __func__, slot_reg, pcix_cap, m66_cap); 487 __func__, slot_reg, pcix_cap, m66_cap);
488 488
489 switch (pcix_cap) { 489 switch (pcix_cap) {
490 case 0x0: 490 case 0x0:
@@ -509,7 +509,7 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
509 break; 509 break;
510 } 510 }
511 511
512 dbg("Adapter speed = %d\n", *value); 512 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
513 return retval; 513 return retval;
514} 514}
515 515
@@ -526,7 +526,7 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
526 retval = -1; 526 retval = -1;
527 } 527 }
528 528
529 dbg("Mode 1 ECC cap = %d\n", *mode); 529 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
530 return retval; 530 return retval;
531} 531}
532 532
@@ -629,7 +629,7 @@ static int hpc_power_on_slot(struct slot * slot)
629 629
630 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 630 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
631 if (retval) 631 if (retval)
632 err("%s: Write command failed!\n", __func__); 632 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
633 633
634 return retval; 634 return retval;
635} 635}
@@ -642,7 +642,7 @@ static int hpc_slot_enable(struct slot * slot)
642 retval = shpc_write_cmd(slot, slot->hp_slot, 642 retval = shpc_write_cmd(slot, slot->hp_slot,
643 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 643 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
644 if (retval) 644 if (retval)
645 err("%s: Write command failed!\n", __func__); 645 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
646 646
647 return retval; 647 return retval;
648} 648}
@@ -655,7 +655,7 @@ static int hpc_slot_disable(struct slot * slot)
655 retval = shpc_write_cmd(slot, slot->hp_slot, 655 retval = shpc_write_cmd(slot, slot->hp_slot,
656 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 656 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
657 if (retval) 657 if (retval)
658 err("%s: Write command failed!\n", __func__); 658 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
659 659
660 return retval; 660 return retval;
661} 661}
@@ -719,7 +719,7 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
719 719
720 retval = shpc_write_cmd(slot, 0, cmd); 720 retval = shpc_write_cmd(slot, 0, cmd);
721 if (retval) 721 if (retval)
722 err("%s: Write command failed!\n", __func__); 722 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
723 723
724 return retval; 724 return retval;
725} 725}
@@ -735,7 +735,7 @@ static irqreturn_t shpc_isr(int irq, void *dev_id)
735 if (!intr_loc) 735 if (!intr_loc)
736 return IRQ_NONE; 736 return IRQ_NONE;
737 737
738 dbg("%s: intr_loc = %x\n",__func__, intr_loc); 738 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
739 739
740 if(!shpchp_poll_mode) { 740 if(!shpchp_poll_mode) {
741 /* 741 /*
@@ -748,7 +748,7 @@ static irqreturn_t shpc_isr(int irq, void *dev_id)
748 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 748 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
749 749
750 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 750 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
751 dbg("%s: intr_loc2 = %x\n",__func__, intr_loc2); 751 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
752 } 752 }
753 753
754 if (intr_loc & CMD_INTR_PENDING) { 754 if (intr_loc & CMD_INTR_PENDING) {
@@ -773,8 +773,8 @@ static irqreturn_t shpc_isr(int irq, void *dev_id)
773 continue; 773 continue;
774 774
775 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 775 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
776 dbg("%s: Slot %x with intr, slot register = %x\n", 776 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
777 __func__, hp_slot, slot_reg); 777 hp_slot, slot_reg);
778 778
779 if (slot_reg & MRL_CHANGE_DETECTED) 779 if (slot_reg & MRL_CHANGE_DETECTED)
780 shpchp_handle_switch_change(hp_slot, ctrl); 780 shpchp_handle_switch_change(hp_slot, ctrl);
@@ -843,7 +843,7 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
843 } 843 }
844 844
845 *value = bus_speed; 845 *value = bus_speed;
846 dbg("Max bus speed = %d\n", bus_speed); 846 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
847 847
848 return retval; 848 return retval;
849} 849}
@@ -911,7 +911,7 @@ static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
911 break; 911 break;
912 } 912 }
913 913
914 dbg("Current bus speed = %d\n", bus_speed); 914 ctrl_dbg(ctrl, "Current bus speed = %d\n", bus_speed);
915 return retval; 915 return retval;
916} 916}
917 917
@@ -949,6 +949,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
949 u8 i; 949 u8 i;
950 950
951 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 951 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
952 ctrl_dbg(ctrl, "Hotplug Controller:\n");
952 953
953 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 954 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
954 PCI_DEVICE_ID_AMD_GOLAM_7450)) { 955 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
@@ -958,34 +959,33 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
958 } else { 959 } else {
959 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 960 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
960 if (!ctrl->cap_offset) { 961 if (!ctrl->cap_offset) {
961 err("%s : cap_offset == 0\n", __func__); 962 ctrl_err(ctrl, "Cannot find PCI capability\n");
962 goto abort; 963 goto abort;
963 } 964 }
964 dbg("%s: cap_offset = %x\n", __func__, ctrl->cap_offset); 965 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
965 966
966 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 967 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
967 if (rc) { 968 if (rc) {
968 err("%s: cannot read base_offset\n", __func__); 969 ctrl_err(ctrl, "Cannot read base_offset\n");
969 goto abort; 970 goto abort;
970 } 971 }
971 972
972 rc = shpc_indirect_read(ctrl, 3, &tempdword); 973 rc = shpc_indirect_read(ctrl, 3, &tempdword);
973 if (rc) { 974 if (rc) {
974 err("%s: cannot read slot config\n", __func__); 975 ctrl_err(ctrl, "Cannot read slot config\n");
975 goto abort; 976 goto abort;
976 } 977 }
977 num_slots = tempdword & SLOT_NUM; 978 num_slots = tempdword & SLOT_NUM;
978 dbg("%s: num_slots (indirect) %x\n", __func__, num_slots); 979 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
979 980
980 for (i = 0; i < 9 + num_slots; i++) { 981 for (i = 0; i < 9 + num_slots; i++) {
981 rc = shpc_indirect_read(ctrl, i, &tempdword); 982 rc = shpc_indirect_read(ctrl, i, &tempdword);
982 if (rc) { 983 if (rc) {
983 err("%s: cannot read creg (index = %d)\n", 984 ctrl_err(ctrl,
984 __func__, i); 985 "Cannot read creg (index = %d)\n", i);
985 goto abort; 986 goto abort;
986 } 987 }
987 dbg("%s: offset %d: value %x\n", __func__,i, 988 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
988 tempdword);
989 } 989 }
990 990
991 ctrl->mmio_base = 991 ctrl->mmio_base =
@@ -993,30 +993,31 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
993 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 993 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
994 } 994 }
995 995
996 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 996 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
997 pdev->subsystem_device); 997 pdev->vendor, pdev->device, pdev->subsystem_vendor,
998 pdev->subsystem_device);
998 999
999 rc = pci_enable_device(pdev); 1000 rc = pci_enable_device(pdev);
1000 if (rc) { 1001 if (rc) {
1001 err("%s: pci_enable_device failed\n", __func__); 1002 ctrl_err(ctrl, "pci_enable_device failed\n");
1002 goto abort; 1003 goto abort;
1003 } 1004 }
1004 1005
1005 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 1006 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1006 err("%s: cannot reserve MMIO region\n", __func__); 1007 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
1007 rc = -1; 1008 rc = -1;
1008 goto abort; 1009 goto abort;
1009 } 1010 }
1010 1011
1011 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 1012 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1012 if (!ctrl->creg) { 1013 if (!ctrl->creg) {
1013 err("%s: cannot remap MMIO region %lx @ %lx\n", __func__, 1014 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
1014 ctrl->mmio_size, ctrl->mmio_base); 1015 ctrl->mmio_size, ctrl->mmio_base);
1015 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1016 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1016 rc = -1; 1017 rc = -1;
1017 goto abort; 1018 goto abort;
1018 } 1019 }
1019 dbg("%s: ctrl->creg %p\n", __func__, ctrl->creg); 1020 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
1020 1021
1021 mutex_init(&ctrl->crit_sect); 1022 mutex_init(&ctrl->crit_sect);
1022 mutex_init(&ctrl->cmd_lock); 1023 mutex_init(&ctrl->cmd_lock);
@@ -1035,21 +1036,21 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1035 1036
1036 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1037 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1038 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1038 dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword); 1039 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1039 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1040 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1040 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1041 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1041 tempdword &= ~SERR_INTR_RSVDZ_MASK; 1042 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1042 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1043 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1043 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1044 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1044 dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword); 1045 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1045 1046
1046 /* Mask the MRL sensor SERR Mask of individual slot in 1047 /* Mask the MRL sensor SERR Mask of individual slot in
1047 * Slot SERR-INT Mask & clear all the existing event if any 1048 * Slot SERR-INT Mask & clear all the existing event if any
1048 */ 1049 */
1049 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1050 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1050 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1051 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1051 dbg("%s: Default Logical Slot Register %d value %x\n", __func__, 1052 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1052 hp_slot, slot_reg); 1053 hp_slot, slot_reg);
1053 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1054 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1054 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1055 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1055 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1056 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
@@ -1066,24 +1067,24 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1066 /* Installs the interrupt handler */ 1067 /* Installs the interrupt handler */
1067 rc = pci_enable_msi(pdev); 1068 rc = pci_enable_msi(pdev);
1068 if (rc) { 1069 if (rc) {
1069 info("Can't get msi for the hotplug controller\n"); 1070 ctrl_info(ctrl,
1070 info("Use INTx for the hotplug controller\n"); 1071 "Can't get msi for the hotplug controller\n");
1072 ctrl_info(ctrl,
1073 "Use INTx for the hotplug controller\n");
1071 } 1074 }
1072 1075
1073 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 1076 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1074 MY_NAME, (void *)ctrl); 1077 MY_NAME, (void *)ctrl);
1075 dbg("%s: request_irq %d for hpc%d (returns %d)\n", 1078 ctrl_dbg(ctrl, "request_irq %d for hpc%d (returns %d)\n",
1076 __func__, ctrl->pci_dev->irq, 1079 ctrl->pci_dev->irq,
1077 atomic_read(&shpchp_num_controllers), rc); 1080 atomic_read(&shpchp_num_controllers), rc);
1078 if (rc) { 1081 if (rc) {
1079 err("Can't get irq %d for the hotplug controller\n", 1082 ctrl_err(ctrl, "Can't get irq %d for the hotplug "
1080 ctrl->pci_dev->irq); 1083 "controller\n", ctrl->pci_dev->irq);
1081 goto abort_iounmap; 1084 goto abort_iounmap;
1082 } 1085 }
1083 } 1086 }
1084 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __func__, 1087 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1085 pdev->bus->number, PCI_SLOT(pdev->devfn),
1086 PCI_FUNC(pdev->devfn), pdev->irq);
1087 1088
1088 /* 1089 /*
1089 * If this is the first controller to be initialized, 1090 * If this is the first controller to be initialized,
@@ -1102,8 +1103,8 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1102 */ 1103 */
1103 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1104 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1104 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1105 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1105 dbg("%s: Default Logical Slot Register %d value %x\n", __func__, 1106 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1106 hp_slot, slot_reg); 1107 hp_slot, slot_reg);
1107 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1108 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1108 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1109 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1109 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1110 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
@@ -1116,7 +1117,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1116 SERR_INTR_RSVDZ_MASK); 1117 SERR_INTR_RSVDZ_MASK);
1117 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1118 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1118 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1119 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1119 dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword); 1120 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1120 } 1121 }
1121 1122
1122 return 0; 1123 return 0;