diff options
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/shpchp_hpc.c | 155 |
1 files changed, 19 insertions, 136 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index b7bede4b7c27..7e9347eea5b1 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c | |||
@@ -35,38 +35,6 @@ | |||
35 | 35 | ||
36 | #include "shpchp.h" | 36 | #include "shpchp.h" |
37 | 37 | ||
38 | #ifdef DEBUG | ||
39 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | ||
40 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | ||
41 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | ||
42 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | ||
43 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | ||
44 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | ||
45 | /* Redefine this flagword to set debug level */ | ||
46 | #define DEBUG_LEVEL DBG_K_STANDARD | ||
47 | |||
48 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | ||
49 | |||
50 | #define DBG_PRINT( dbg_flags, args... ) \ | ||
51 | do { \ | ||
52 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | ||
53 | { \ | ||
54 | int len; \ | ||
55 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | ||
56 | __FILE__, __LINE__, __FUNCTION__ ); \ | ||
57 | sprintf( __dbg_str_buf + len, args ); \ | ||
58 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | ||
59 | } \ | ||
60 | } while (0) | ||
61 | |||
62 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | ||
63 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | ||
64 | #else | ||
65 | #define DEFINE_DBG_BUFFER | ||
66 | #define DBG_ENTER_ROUTINE | ||
67 | #define DBG_LEAVE_ROUTINE | ||
68 | #endif /* DEBUG */ | ||
69 | |||
70 | /* Slot Available Register I field definition */ | 38 | /* Slot Available Register I field definition */ |
71 | #define SLOT_33MHZ 0x0000001f | 39 | #define SLOT_33MHZ 0x0000001f |
72 | #define SLOT_66MHZ_PCIX 0x00001f00 | 40 | #define SLOT_66MHZ_PCIX 0x00001f00 |
@@ -211,7 +179,6 @@ | |||
211 | #define SLOT_EVENT_LATCH 0x2 | 179 | #define SLOT_EVENT_LATCH 0x2 |
212 | #define SLOT_SERR_INT_MASK 0x3 | 180 | #define SLOT_SERR_INT_MASK 0x3 |
213 | 181 | ||
214 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | ||
215 | static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); | 182 | static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); |
216 | 183 | ||
217 | static irqreturn_t shpc_isr(int irq, void *dev_id); | 184 | static irqreturn_t shpc_isr(int irq, void *dev_id); |
@@ -268,8 +235,6 @@ static void int_poll_timeout(unsigned long data) | |||
268 | { | 235 | { |
269 | struct controller *ctrl = (struct controller *)data; | 236 | struct controller *ctrl = (struct controller *)data; |
270 | 237 | ||
271 | DBG_ENTER_ROUTINE | ||
272 | |||
273 | /* Poll for interrupt events. regs == NULL => polling */ | 238 | /* Poll for interrupt events. regs == NULL => polling */ |
274 | shpc_isr(0, ctrl); | 239 | shpc_isr(0, ctrl); |
275 | 240 | ||
@@ -278,8 +243,6 @@ static void int_poll_timeout(unsigned long data) | |||
278 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ | 243 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
279 | 244 | ||
280 | start_int_poll_timer(ctrl, shpchp_poll_time); | 245 | start_int_poll_timer(ctrl, shpchp_poll_time); |
281 | |||
282 | DBG_LEAVE_ROUTINE | ||
283 | } | 246 | } |
284 | 247 | ||
285 | /* | 248 | /* |
@@ -353,8 +316,6 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | |||
353 | int retval = 0; | 316 | int retval = 0; |
354 | u16 temp_word; | 317 | u16 temp_word; |
355 | 318 | ||
356 | DBG_ENTER_ROUTINE | ||
357 | |||
358 | mutex_lock(&slot->ctrl->cmd_lock); | 319 | mutex_lock(&slot->ctrl->cmd_lock); |
359 | 320 | ||
360 | if (!shpc_poll_ctrl_busy(ctrl)) { | 321 | if (!shpc_poll_ctrl_busy(ctrl)) { |
@@ -389,19 +350,13 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | |||
389 | } | 350 | } |
390 | out: | 351 | out: |
391 | mutex_unlock(&slot->ctrl->cmd_lock); | 352 | mutex_unlock(&slot->ctrl->cmd_lock); |
392 | |||
393 | DBG_LEAVE_ROUTINE | ||
394 | return retval; | 353 | return retval; |
395 | } | 354 | } |
396 | 355 | ||
397 | static int hpc_check_cmd_status(struct controller *ctrl) | 356 | static int hpc_check_cmd_status(struct controller *ctrl) |
398 | { | 357 | { |
399 | u16 cmd_status; | ||
400 | int retval = 0; | 358 | int retval = 0; |
401 | 359 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; | |
402 | DBG_ENTER_ROUTINE | ||
403 | |||
404 | cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; | ||
405 | 360 | ||
406 | switch (cmd_status >> 1) { | 361 | switch (cmd_status >> 1) { |
407 | case 0: | 362 | case 0: |
@@ -423,7 +378,6 @@ static int hpc_check_cmd_status(struct controller *ctrl) | |||
423 | retval = cmd_status; | 378 | retval = cmd_status; |
424 | } | 379 | } |
425 | 380 | ||
426 | DBG_LEAVE_ROUTINE | ||
427 | return retval; | 381 | return retval; |
428 | } | 382 | } |
429 | 383 | ||
@@ -431,13 +385,8 @@ static int hpc_check_cmd_status(struct controller *ctrl) | |||
431 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | 385 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
432 | { | 386 | { |
433 | struct controller *ctrl = slot->ctrl; | 387 | struct controller *ctrl = slot->ctrl; |
434 | u32 slot_reg; | 388 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
435 | u8 state; | 389 | u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
436 | |||
437 | DBG_ENTER_ROUTINE | ||
438 | |||
439 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | ||
440 | state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; | ||
441 | 390 | ||
442 | switch (state) { | 391 | switch (state) { |
443 | case ATN_LED_STATE_ON: | 392 | case ATN_LED_STATE_ON: |
@@ -454,20 +403,14 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
454 | break; | 403 | break; |
455 | } | 404 | } |
456 | 405 | ||
457 | DBG_LEAVE_ROUTINE | ||
458 | return 0; | 406 | return 0; |
459 | } | 407 | } |
460 | 408 | ||
461 | static int hpc_get_power_status(struct slot * slot, u8 *status) | 409 | static int hpc_get_power_status(struct slot * slot, u8 *status) |
462 | { | 410 | { |
463 | struct controller *ctrl = slot->ctrl; | 411 | struct controller *ctrl = slot->ctrl; |
464 | u32 slot_reg; | 412 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
465 | u8 state; | 413 | u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
466 | |||
467 | DBG_ENTER_ROUTINE | ||
468 | |||
469 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | ||
470 | state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; | ||
471 | 414 | ||
472 | switch (state) { | 415 | switch (state) { |
473 | case SLOT_STATE_PWRONLY: | 416 | case SLOT_STATE_PWRONLY: |
@@ -484,7 +427,6 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) | |||
484 | break; | 427 | break; |
485 | } | 428 | } |
486 | 429 | ||
487 | DBG_LEAVE_ROUTINE | ||
488 | return 0; | 430 | return 0; |
489 | } | 431 | } |
490 | 432 | ||
@@ -492,30 +434,21 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) | |||
492 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | 434 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
493 | { | 435 | { |
494 | struct controller *ctrl = slot->ctrl; | 436 | struct controller *ctrl = slot->ctrl; |
495 | u32 slot_reg; | 437 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
496 | |||
497 | DBG_ENTER_ROUTINE | ||
498 | 438 | ||
499 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | ||
500 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ | 439 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
501 | 440 | ||
502 | DBG_LEAVE_ROUTINE | ||
503 | return 0; | 441 | return 0; |
504 | } | 442 | } |
505 | 443 | ||
506 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | 444 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) |
507 | { | 445 | { |
508 | struct controller *ctrl = slot->ctrl; | 446 | struct controller *ctrl = slot->ctrl; |
509 | u32 slot_reg; | 447 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
510 | u8 state; | 448 | u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
511 | |||
512 | DBG_ENTER_ROUTINE | ||
513 | 449 | ||
514 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | ||
515 | state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; | ||
516 | *status = (state != 0x3) ? 1 : 0; | 450 | *status = (state != 0x3) ? 1 : 0; |
517 | 451 | ||
518 | DBG_LEAVE_ROUTINE | ||
519 | return 0; | 452 | return 0; |
520 | } | 453 | } |
521 | 454 | ||
@@ -523,11 +456,8 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |||
523 | { | 456 | { |
524 | struct controller *ctrl = slot->ctrl; | 457 | struct controller *ctrl = slot->ctrl; |
525 | 458 | ||
526 | DBG_ENTER_ROUTINE | ||
527 | |||
528 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); | 459 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
529 | 460 | ||
530 | DBG_LEAVE_ROUTINE | ||
531 | return 0; | 461 | return 0; |
532 | } | 462 | } |
533 | 463 | ||
@@ -539,8 +469,6 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |||
539 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); | 469 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
540 | u8 pi, pcix_cap; | 470 | u8 pi, pcix_cap; |
541 | 471 | ||
542 | DBG_ENTER_ROUTINE | ||
543 | |||
544 | if ((retval = hpc_get_prog_int(slot, &pi))) | 472 | if ((retval = hpc_get_prog_int(slot, &pi))) |
545 | return retval; | 473 | return retval; |
546 | 474 | ||
@@ -582,21 +510,15 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |||
582 | } | 510 | } |
583 | 511 | ||
584 | dbg("Adapter speed = %d\n", *value); | 512 | dbg("Adapter speed = %d\n", *value); |
585 | DBG_LEAVE_ROUTINE | ||
586 | return retval; | 513 | return retval; |
587 | } | 514 | } |
588 | 515 | ||
589 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | 516 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) |
590 | { | 517 | { |
591 | struct controller *ctrl = slot->ctrl; | ||
592 | u16 sec_bus_status; | ||
593 | u8 pi; | ||
594 | int retval = 0; | 518 | int retval = 0; |
595 | 519 | struct controller *ctrl = slot->ctrl; | |
596 | DBG_ENTER_ROUTINE | 520 | u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); |
597 | 521 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
598 | pi = shpc_readb(ctrl, PROG_INTERFACE); | ||
599 | sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); | ||
600 | 522 | ||
601 | if (pi == 2) { | 523 | if (pi == 2) { |
602 | *mode = (sec_bus_status & 0x0100) >> 8; | 524 | *mode = (sec_bus_status & 0x0100) >> 8; |
@@ -605,21 +527,14 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |||
605 | } | 527 | } |
606 | 528 | ||
607 | dbg("Mode 1 ECC cap = %d\n", *mode); | 529 | dbg("Mode 1 ECC cap = %d\n", *mode); |
608 | |||
609 | DBG_LEAVE_ROUTINE | ||
610 | return retval; | 530 | return retval; |
611 | } | 531 | } |
612 | 532 | ||
613 | static int hpc_query_power_fault(struct slot * slot) | 533 | static int hpc_query_power_fault(struct slot * slot) |
614 | { | 534 | { |
615 | struct controller *ctrl = slot->ctrl; | 535 | struct controller *ctrl = slot->ctrl; |
616 | u32 slot_reg; | 536 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
617 | |||
618 | DBG_ENTER_ROUTINE | ||
619 | |||
620 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | ||
621 | 537 | ||
622 | DBG_LEAVE_ROUTINE | ||
623 | /* Note: Logic 0 => fault */ | 538 | /* Note: Logic 0 => fault */ |
624 | return !(slot_reg & POWER_FAULT); | 539 | return !(slot_reg & POWER_FAULT); |
625 | } | 540 | } |
@@ -666,8 +581,6 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
666 | int i; | 581 | int i; |
667 | u32 slot_reg, serr_int; | 582 | u32 slot_reg, serr_int; |
668 | 583 | ||
669 | DBG_ENTER_ROUTINE | ||
670 | |||
671 | /* | 584 | /* |
672 | * Mask event interrupts and SERRs of all slots | 585 | * Mask event interrupts and SERRs of all slots |
673 | */ | 586 | */ |
@@ -708,61 +621,43 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
708 | */ | 621 | */ |
709 | if (atomic_dec_and_test(&shpchp_num_controllers)) | 622 | if (atomic_dec_and_test(&shpchp_num_controllers)) |
710 | destroy_workqueue(shpchp_wq); | 623 | destroy_workqueue(shpchp_wq); |
711 | |||
712 | DBG_LEAVE_ROUTINE | ||
713 | } | 624 | } |
714 | 625 | ||
715 | static int hpc_power_on_slot(struct slot * slot) | 626 | static int hpc_power_on_slot(struct slot * slot) |
716 | { | 627 | { |
717 | int retval; | 628 | int retval; |
718 | 629 | ||
719 | DBG_ENTER_ROUTINE | ||
720 | |||
721 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); | 630 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
722 | if (retval) { | 631 | if (retval) |
723 | err("%s: Write command failed!\n", __FUNCTION__); | 632 | err("%s: Write command failed!\n", __FUNCTION__); |
724 | return retval; | ||
725 | } | ||
726 | |||
727 | DBG_LEAVE_ROUTINE | ||
728 | 633 | ||
729 | return 0; | 634 | return retval; |
730 | } | 635 | } |
731 | 636 | ||
732 | static int hpc_slot_enable(struct slot * slot) | 637 | static int hpc_slot_enable(struct slot * slot) |
733 | { | 638 | { |
734 | int retval; | 639 | int retval; |
735 | 640 | ||
736 | DBG_ENTER_ROUTINE | ||
737 | |||
738 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ | 641 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
739 | retval = shpc_write_cmd(slot, slot->hp_slot, | 642 | retval = shpc_write_cmd(slot, slot->hp_slot, |
740 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); | 643 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); |
741 | if (retval) { | 644 | if (retval) |
742 | err("%s: Write command failed!\n", __FUNCTION__); | 645 | err("%s: Write command failed!\n", __FUNCTION__); |
743 | return retval; | ||
744 | } | ||
745 | 646 | ||
746 | DBG_LEAVE_ROUTINE | 647 | return retval; |
747 | return 0; | ||
748 | } | 648 | } |
749 | 649 | ||
750 | static int hpc_slot_disable(struct slot * slot) | 650 | static int hpc_slot_disable(struct slot * slot) |
751 | { | 651 | { |
752 | int retval; | 652 | int retval; |
753 | 653 | ||
754 | DBG_ENTER_ROUTINE | ||
755 | |||
756 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ | 654 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
757 | retval = shpc_write_cmd(slot, slot->hp_slot, | 655 | retval = shpc_write_cmd(slot, slot->hp_slot, |
758 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); | 656 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); |
759 | if (retval) { | 657 | if (retval) |
760 | err("%s: Write command failed!\n", __FUNCTION__); | 658 | err("%s: Write command failed!\n", __FUNCTION__); |
761 | return retval; | ||
762 | } | ||
763 | 659 | ||
764 | DBG_LEAVE_ROUTINE | 660 | return retval; |
765 | return 0; | ||
766 | } | 661 | } |
767 | 662 | ||
768 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) | 663 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) |
@@ -771,8 +666,6 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) | |||
771 | struct controller *ctrl = slot->ctrl; | 666 | struct controller *ctrl = slot->ctrl; |
772 | u8 pi, cmd; | 667 | u8 pi, cmd; |
773 | 668 | ||
774 | DBG_ENTER_ROUTINE | ||
775 | |||
776 | pi = shpc_readb(ctrl, PROG_INTERFACE); | 669 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
777 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) | 670 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
778 | return -EINVAL; | 671 | return -EINVAL; |
@@ -828,7 +721,6 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) | |||
828 | if (retval) | 721 | if (retval) |
829 | err("%s: Write command failed!\n", __FUNCTION__); | 722 | err("%s: Write command failed!\n", __FUNCTION__); |
830 | 723 | ||
831 | DBG_LEAVE_ROUTINE | ||
832 | return retval; | 724 | return retval; |
833 | } | 725 | } |
834 | 726 | ||
@@ -920,8 +812,6 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |||
920 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); | 812 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); |
921 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); | 813 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); |
922 | 814 | ||
923 | DBG_ENTER_ROUTINE | ||
924 | |||
925 | if (pi == 2) { | 815 | if (pi == 2) { |
926 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) | 816 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
927 | bus_speed = PCI_SPEED_133MHz_PCIX_533; | 817 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
@@ -954,7 +844,7 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |||
954 | 844 | ||
955 | *value = bus_speed; | 845 | *value = bus_speed; |
956 | dbg("Max bus speed = %d\n", bus_speed); | 846 | dbg("Max bus speed = %d\n", bus_speed); |
957 | DBG_LEAVE_ROUTINE | 847 | |
958 | return retval; | 848 | return retval; |
959 | } | 849 | } |
960 | 850 | ||
@@ -967,8 +857,6 @@ static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |||
967 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | 857 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
968 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); | 858 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
969 | 859 | ||
970 | DBG_ENTER_ROUTINE | ||
971 | |||
972 | if ((pi == 1) && (speed_mode > 4)) { | 860 | if ((pi == 1) && (speed_mode > 4)) { |
973 | *value = PCI_SPEED_UNKNOWN; | 861 | *value = PCI_SPEED_UNKNOWN; |
974 | return -ENODEV; | 862 | return -ENODEV; |
@@ -1024,7 +912,6 @@ static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |||
1024 | } | 912 | } |
1025 | 913 | ||
1026 | dbg("Current bus speed = %d\n", bus_speed); | 914 | dbg("Current bus speed = %d\n", bus_speed); |
1027 | DBG_LEAVE_ROUTINE | ||
1028 | return retval; | 915 | return retval; |
1029 | } | 916 | } |
1030 | 917 | ||
@@ -1061,8 +948,6 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1061 | u32 tempdword, slot_reg, slot_config; | 948 | u32 tempdword, slot_reg, slot_config; |
1062 | u8 i; | 949 | u8 i; |
1063 | 950 | ||
1064 | DBG_ENTER_ROUTINE | ||
1065 | |||
1066 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ | 951 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
1067 | 952 | ||
1068 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == | 953 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
@@ -1235,13 +1120,11 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1235 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); | 1120 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1236 | } | 1121 | } |
1237 | 1122 | ||
1238 | DBG_LEAVE_ROUTINE | ||
1239 | return 0; | 1123 | return 0; |
1240 | 1124 | ||
1241 | /* We end up here for the many possible ways to fail this API. */ | 1125 | /* We end up here for the many possible ways to fail this API. */ |
1242 | abort_iounmap: | 1126 | abort_iounmap: |
1243 | iounmap(ctrl->creg); | 1127 | iounmap(ctrl->creg); |
1244 | abort: | 1128 | abort: |
1245 | DBG_LEAVE_ROUTINE | ||
1246 | return rc; | 1129 | return rc; |
1247 | } | 1130 | } |